ram/aspeed: Re-init ECC if requested but not enabled

If a machine has a new u-boot installed that enables ECC, but it has not
had a power cycle since being updated, the DDR will not re-initalise and

ram/aspeed: Re-init ECC if requested but not enabled

If a machine has a new u-boot installed that enables ECC, but it has not
had a power cycle since being updated, the DDR will not re-initalise and
ECC will stay disabled.

Similarly for the reverse case, where ECC was enabled but a new u-boot
disables it.

Detect if ECC has been requested by the firmware and check against the
hardware state. If it does not match, and the DDR has already been
initialised, proceed as if the DDR has not been set up.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Adriana Kobylak <anoo@us.ibm.com>
Tested-by: Adriana Kobylak <anoo@us.ibm.com>
Link: https://lore.kernel.org/r/20220921074629.2265812-1-joel@jms.id.au

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ram/aspeed: Remove ECC config option

Always build the code now that it is enabled by device tree.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: ht

ram/aspeed: Remove ECC config option

Always build the code now that it is enabled by device tree.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220921074439.2265651-3-joel@jms.id.au
Change-Id: I98fdc3a7a09347624ec73f03819003f34cb39a30

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ram/aspeed: Use device tree to configure ECC

Instead of configuring ECC based on the build config, use a device tree
property to selectively enable ECC at runtime.

There are two properties:

aspe

ram/aspeed: Use device tree to configure ECC

Instead of configuring ECC based on the build config, use a device tree
property to selectively enable ECC at runtime.

There are two properties:

aspeed,ecc-enabled;
aspeed,ecc-size-mb = "512";

The enabled property is a boolean that enables ECC if it is present.

The size is the number of MB that should be covered by ECC. Setting it
to zero, or omitting it, defaults the ECC size to "auto detect".

edac: sdram@1e6e0000 {
compatible = "aspeed,ast2600-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
aspeed,ecc-enabled;
aspeed,ecc-size-mb = "512";
};

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20220921074439.2265651-2-joel@jms.id.au
Change-Id: Ib5519a29129e7a713be1e172dbd4e44776f0dbe0

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aspeed: ast2600: Keep PLL power on

According to the PLL vendor, we should keep PLL power on so don't toggle
the power down bit in PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtec

aspeed: ast2600: Keep PLL power on

According to the PLL vendor, we should keep PLL power on so don't toggle
the power down bit in PLL initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I6dbba8bbb0c51a569a2ced6fdd3d69645b9f4391

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ram: aspeed: DDR4 DRAM and PHY ODT/Ron options depend on AST2600

Only AST2600 DRAM driver supports DDR4 DRAM and PHY ODT/Ron adjustment.
So let these options depend on CONFIG_ASPEED_AST2600.

Signed

ram: aspeed: DDR4 DRAM and PHY ODT/Ron options depend on AST2600

Only AST2600 DRAM driver supports DDR4 DRAM and PHY ODT/Ron adjustment.
So let these options depend on CONFIG_ASPEED_AST2600.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Id4449c6703773dcc9585cab8f27b71c027ad6579

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ram: ast2600: add option for DRAM ODT 80 ohm

Add CONFIG_ASPEED_DDR4_DRAM_ODT80 to change the DRAM ODT to 80 ohm. The
default value keeps on 48 ohm.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.

ram: ast2600: add option for DRAM ODT 80 ohm

Add CONFIG_ASPEED_DDR4_DRAM_ODT80 to change the DRAM ODT to 80 ohm. The
default value keeps on 48 ohm.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I8a0775309fac689a607ed4a3077b9eded61d8828

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ram: ast2600: fix typo of CONFIG_ASPEED_DDR4_DRAM_RON_48

Fix the typo for missing "CONFIG_" of CONFIG_ASPEED_DDR4_DRAM_RON_48

Fixes: cb2cc580a14a ("ram: ast2600: add option to configure DRAM output

ram: ast2600: fix typo of CONFIG_ASPEED_DDR4_DRAM_RON_48

Fix the typo for missing "CONFIG_" of CONFIG_ASPEED_DDR4_DRAM_RON_48

Fixes: cb2cc580a14a ("ram: ast2600: add option to configure DRAM output impedance")

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I7cc4a9ac904e5562a8a5a4d7075b3cd5fe1f5810

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Revert "Revert "ram: ast2600: add option for write data eye training result offset""

This reverts commit 260266628ecd7052a5d0a44f87940fea2c6dbaf4.

Reason for revert: rebase dram driver

Change-Id:

Revert "Revert "ram: ast2600: add option for write data eye training result offset""

This reverts commit 260266628ecd7052a5d0a44f87940fea2c6dbaf4.

Reason for revert: rebase dram driver

Change-Id: If9644975969922093d6be6d32f30303e4b165d07

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Revert "ram: ast2600: add option for write data eye training result offset"

This reverts commit 841e08048f8fde541c710d2cd3b9982e1523eb81.

Reason for revert: rebase sdram_ast2600 driver

Change-Id:

Revert "ram: ast2600: add option for write data eye training result offset"

This reverts commit 841e08048f8fde541c710d2cd3b9982e1523eb81.

Reason for revert: rebase sdram_ast2600 driver

Change-Id: Ic6ada37982099c7f0750cffd862c65ff29fef9a5

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ram: ast2600: add option for write data eye training result offset

Add an option to fine-tune the DDR PHY write data eye training result.
The default value is 0x10.

Signed-off-by: Dylan Hung <dylan

ram: ast2600: add option for write data eye training result offset

Add an option to fine-tune the DDR PHY write data eye training result.
The default value is 0x10.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: If95fc958267ce18e85d686f3f33fe0858cdc532b

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ram: ast2600: remove CA and read data eye manual delay

According to the PHY vendor:
phyr0a8[31:24] - CA training manual mode delay, shall be 0
phyr198[15:8] - read data eye training result manual of

ram: ast2600: remove CA and read data eye manual delay

According to the PHY vendor:
phyr0a8[31:24] - CA training manual mode delay, shall be 0
phyr198[15:8] - read data eye training result manual offset, shall be 0

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I6aa6d4a23e7f28306af44bfba43e521383c9070b

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ram: ast2600: align the RL and WL setting

Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Ch

ram: ast2600: align the RL and WL setting

Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9151ef465ddb45b96bb0c5d61c01d516a92127c4

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ram: ast2600: bug fix of incorrect polling for MCR60[0]

"~data" is a typo, the original intention should be "!data". Since
"data" had beed masked by SDRAM_PHYCTRL0_INIT, use "data == 0" for the
if

ram: ast2600: bug fix of incorrect polling for MCR60[0]

"~data" is a typo, the original intention should be "!data". Since
"data" had beed masked by SDRAM_PHYCTRL0_INIT, use "data == 0" for the
if statement to make it easier for understanding.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I58e7c913d2c36ad6452919ac024fa9a42026db17

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ram: ast2600: use macro to represent DRAM MR

Use macro to represent DRAM mode registers. Both DDR-PHY and DDR
controller have their own registers for MR configuration, use the same
values for both

ram: ast2600: use macro to represent DRAM MR

Use macro to represent DRAM mode registers. Both DDR-PHY and DDR
controller have their own registers for MR configuration, use the same
values for both side.

Also, this commit modifies the default RTT and RON setting
RTT_WR: disable
RTT_NOM: 48 ohm
RTT_PARK: 48 ohm
DRAM output driver impedance: 34 ohm
PHY Ron: 34 ohm
PHY ODT: 80 ohm

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I38be1ef106a914dcfb5da3149ff59ca6ec4f3fbb

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ram: ast2600: add option to configure DRAM output impedance

The DRAM output impedance is controlled by MR1[A2:A1]. Add an option to
make it configurable.

Signed-off-by: Dylan Hung <dylan_hung@aspe

ram: ast2600: add option to configure DRAM output impedance

The DRAM output impedance is controlled by MR1[A2:A1]. Add an option to
make it configurable.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I0f2c5e9bd196a2dbb81e5a8a588f33079340a7ae

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ram: ast2600: add option for PHY ODT 80 ohm

Add option to select PHY ODT 80 ohm

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Ia0e862de4f223e675414428abe1cc0cfeea8a1b9

ram: ast2600: add macro to represent PHY_RON setting

Use macro to represent PHY Ron setting in PHY registers.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Iaf540e239f4be9ae4ad38

ram: ast2600: add macro to represent PHY_RON setting

Use macro to represent PHY Ron setting in PHY registers.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Iaf540e239f4be9ae4ad385cdfdf72c42aafd0c0c

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ram: ast2600: revise DDR-PHY training report

1. use FIELD_GET to parse the bitfield
2. parse and print the Read and Write Vref training result
3. print the gate training result

Signed-off-by: Dylan

ram: ast2600: revise DDR-PHY training report

1. use FIELD_GET to parse the bitfield
2. parse and print the Read and Write Vref training result
3. print the gate training result

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I389dd13d609932e3ec52fe5cc1034420f941dd5a

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ram: aspeed: add AST2600 ODT configuration

PHY side: 1e6e0130[10:8]
- b'100 = 60 ohm
- b'101 = 48 ohm
- b'110 = 40 ohm (default)

DRAM side: 1e6e0158[10:8] & 1e6e0020[26:24]
- b'001 = 60 ohm
- b'101

ram: aspeed: add AST2600 ODT configuration

PHY side: 1e6e0130[10:8]
- b'100 = 60 ohm
- b'101 = 48 ohm
- b'110 = 40 ohm (default)

DRAM side: 1e6e0158[10:8] & 1e6e0020[26:24]
- b'001 = 60 ohm
- b'101 = 48 ohm
- b'011 = 40 ohm (default)

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I38883cbdd6de5a0f042573506c88a10f16d14f83

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ram: aspeed: revise coding style

revise coding style, no logic change.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Icece6ea5ef1dc98f71579b6a897532ca3cbe15ba

ram: aspeed: fix incorrect printf

somehow it is unable to print capital hex in u-boot (maybe toolchain or
limited resource in early boot). So change the format in lowercase.

Signed-off-by: Dylan Hu

ram: aspeed: fix incorrect printf

somehow it is unable to print capital hex in u-boot (maybe toolchain or
limited resource in early boot). So change the format in lowercase.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Ic6fdf4032fdf738a7c719576349ecbaaf5a9183c

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ram: aspeed: revise tRFI configuration

remove hard code of the tRFI configuration and add comments

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Idc0da42874da136569a487ea06925eda

ram: aspeed: revise tRFI configuration

remove hard code of the tRFI configuration and add comments

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Idc0da42874da136569a487ea06925eda0f9e4988

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ram: aspeed: remove dead code and refine comment

refine comment of the Vref training results

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Ie85809f3e48e924db1837d6aa0151f5ab124f9

ram: aspeed: remove dead code and refine comment

refine comment of the Vref training results

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: Ie85809f3e48e924db1837d6aa0151f5ab124f93b

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ram: aspeed: remove incorrect Vref information

The Vref information shall follow the JEDEC DDR4 specification, not the
linear mapping. So remove the incorrect message print.

Signed-off-by: Dylan H

ram: aspeed: remove incorrect Vref information

The Vref information shall follow the JEDEC DDR4 specification, not the
linear mapping. So remove the incorrect message print.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I29e730f45ea7f5c1f5ad0e31158e2ad6ae7721c4

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ram: aspeed: update sdram setting

Update sdram setting to improve OS installation stability.

1. Set USB REQ as high priority
2. Adjust REQ queued threshold value
3. Adjust REQ arbitration policy as

ram: aspeed: update sdram setting

Update sdram setting to improve OS installation stability.

1. Set USB REQ as high priority
2. Adjust REQ queued threshold value
3. Adjust REQ arbitration policy as fixed
4. Not limit REQ4 (video) in request queue
5. Adjust REQ4 (video) maximum grant length

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Change-Id: I83aed1e9c1fcd586c16bcbf098ecb0042f2e75f7

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