1/* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11/* 12 * Board specific setup info 13 * 14 ****************************************************************************** 15 * ASPEED Technology Inc. 16 * 17 * Version : 2 18 * Release date: 2019.02.19 19 * 20 * Priority of fix item: 21 * [P1] = critical 22 * [P2] = nice to have 23 * [P3] = minor 24 * 25 * Change List : 26 * V0 |2018.03.28 : 1.[P1] Initial release for simulation 27 * 28 * Optional define variable 29 * 30 ****************************************************************************** 31 */ 32 33#include <config.h> 34#include <version.h> 35#include <asm/secure.h> 36#include <asm/armv7.h> 37#include <linux/linkage.h> 38 39/* 40 * SMP mailbox 41 * +----------------------+ 42 * | | 43 * | mailbox insn. for | 44 * | cpuN polling SMP go | 45 * | | 46 * +----------------------+ 0xC 47 * | mailbox ready signal | 48 * +----------------------+ 0x8 49 * | cpuN GO signal | 50 * +----------------------+ 0x4 51 * | cpuN entrypoint | 52 * +----------------------+ AST_SMP_MAILBOX_BASE 53 */ 54 55#define AST_SMP_MAILBOX_BASE 0x1E6E2180 56#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) 57#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) 58#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) 59#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) 60 61/* AST2600 HW registers */ 62#define AST_SCU_BASE 0x1E6E2000 63#define AST_SCU_PROT_KEY1 (AST_SCU_BASE) 64#define AST_SCU_PROT_KEY2 (AST_SCU_BASE + 0x010) 65#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014) 66#define AST_SCU_HW_STRAP1 (AST_SCU_BASE + 0x500) 67 68#define AST_FMC_BASE 0x1E620000 69#define AST_FMC_WDT1_CTRL_MODE (AST_FMC_BASE + 0x060) 70#define AST_FMC_WDT2_CTRL_MODE (AST_FMC_BASE + 0x064) 71 72/* Revision ID */ 73#define REV_ID_AST2600A0 0x05000303 74 75ENTRY(ast_bootmode) 76 ldr r1, =AST_SCU_HW_STRAP1 77 ldr r0, [r1] 78 tst r0, #0x4 79 moveq r0, #0x0 @; AST_BOOTMODE_SPI 80 movne r0, #0x1 @; AST_BOOTMODE_EMMC 81 mov pc, lr 82ENDPROC(ast_bootmode) 83 84.macro timer_init 85#ifdef CONFIG_FPGA_ASPEED 86 movw r0, #0x0 87 movt r0, #0x2500 88#else 89 ldr r0, =AST_SCU_REV_ID 90 ldr r0, [r0] 91 92 ldr r1, =REV_ID_AST2600A0 93 cmp r0, r1 94 95 movweq r0, #0x0800 96 movteq r0, #0x2FAF @; 800MHz for A0 97 movwne r0, #0x8C00 98 movtne r0, #0x4786 @; 1.2GHz for A1 99#endif 100 /* write CNTFRQ */ 101 mcr p15, 0, r0, c14, c0, 0 102.endm 103 104 105.globl lowlevel_init 106 107lowlevel_init: 108#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 109 mov pc, lr 110#else 111 /* setup timer frequency for ARM generic timer */ 112 timer_init 113 114 /* 115 * we treat cpu0 as the primary core and 116 * put secondary core (cpuN) to sleep 117 */ 118 mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register 119 ands r0, r0, #0xFF @; Mask off, leaving the CPU ID field 120 ldr r2, =0xABBAAB00 121 orr r2, r2, r0 122 123 beq do_primary_core_setup 124 125 /* hold cpuN until mailbox is ready */ 126poll_mailbox_ready: 127 wfe 128 ldr r0, =AST_SMP_MBOX_FIELD_READY 129 ldr r0, [r0] 130 ldr r1, =0xBABECAFE 131 cmp r1, r0 132 bne poll_mailbox_ready 133 134 /* parameters for relocated SMP go polling insn. */ 135 ldr r0, =AST_SMP_MBOX_FIELD_GOSIGN 136 ldr r1, =AST_SMP_MBOX_FIELD_ENTRY 137 138 /* no return */ 139 ldr pc, =AST_SMP_MBOX_FIELD_POLLINSN 140 141do_primary_core_setup: 142 /* unlock SCU */ 143 ldr r0, =0x1688A8A8 @; magic key to unlock SCU 144 ldr r1, =AST_SCU_PROT_KEY1 145 str r0, [r1] 146 ldr r1, =AST_SCU_PROT_KEY2 147 str r0, [r1] 148 149 /* disable FMC WDT for SPI address mode detection */ 150 mov r0, #0 151 ldr r1, =AST_FMC_WDT1_CTRL_MODE 152 str r0, [r1] 153 ldr r1, =AST_FMC_WDT2_CTRL_MODE 154 str r0, [r1] 155 156 /* relocate mailbox insn. for cpuN polling SMP go signal */ 157 adrl r0, mailbox_insn 158 adrl r1, mailbox_insn_end 159 160 ldr r2, =#AST_SMP_MBOX_FIELD_POLLINSN 161 162relocate_mailbox_insn: 163 ldr r3, [r0], #0x4 164 str r3, [r2], #0x4 165 cmp r0, r1 166 bne relocate_mailbox_insn 167 168 /* notify cpuN mailbox is ready */ 169 ldr r0, =AST_SMP_MBOX_FIELD_READY 170 ldr r1, =0xBABECAFE 171 str r1, [r0] 172 sev 173 174 /* back to arch calling code */ 175 mov pc, lr 176 177/* 178 * insn. inside mailbox to poll SMP go signal. 179 * 180 * Note that as this code will be relocated, any 181 * pc-relative assembly should NOT be used. 182 */ 183mailbox_insn: 184 /* 185 * r0 ~ r3 are parameters: 186 * r0 = AST_SMP_MBOX_FIELD_GOSIGN 187 * r1 = AST_SMP_MBOX_FIELD_ENTRY 188 * r2 = per-cpu go sign value 189 * r3 = no used now 190 */ 191poll_mailbox_smp_go: 192 wfe 193 ldr r4, [r0] 194 cmp r2, r4 195 bne poll_mailbox_smp_go 196 197 /* SMP GO signal confirmed, release cpuN */ 198 ldr pc, [r1] 199 200mailbox_insn_end: 201 /* should never reach */ 202 b . 203 204#endif 205