xref: /openbmc/u-boot/drivers/ram/aspeed/sdram_ast2600.c (revision d6f57adb772ff60825daa5774acd62ea5916cf15)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) ASPEED Technology Inc.
4  *
5  */
6 
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <ram.h>
12 #include <regmap.h>
13 #include <reset.h>
14 #include <asm/io.h>
15 #include <asm/arch/scu_ast2600.h>
16 #include <asm/arch/sdram_ast2600.h>
17 #include <linux/err.h>
18 #include <linux/kernel.h>
19 #include <dt-bindings/clock/ast2600-clock.h>
20 #include "sdram_phy_ast2600.h"
21 
22 /* in order to speed up DRAM init time, write pre-defined values to registers
23  * directly */
24 #define AST2600_SDRAMMC_MANUAL_CLK
25 
26 /* register offset */
27 #define AST_SCU_FPGA_STATUS	0x004
28 #define AST_SCU_HANDSHAKE	0x100
29 #define AST_SCU_MPLL		0x220
30 #define AST_SCU_MPLL_EXT	0x224
31 #define AST_SCU_FPGA_PLL	0x400
32 #define AST_SCU_HW_STRAP	0x500
33 
34 
35 /* bit-field of AST_SCU_HW_STRAP */
36 #define SCU_HWSTRAP_VGAMEM_SHIFT	13
37 #define SCU_HWSTRAP_VGAMEM_MASK		GENMASK(14, 13)
38 
39 
40 /* bit-field of AST_SCU_HANDSHAKE */
41 #define SCU_SDRAM_INIT_READY_MASK	BIT(6)
42 #define SCU_SDRAM_INIT_BY_SOC_MASK	BIT(7)
43 
44 /* bit-field of AST_SCU_MPLL */
45 #define SCU_MPLL_RESET			BIT(25)
46 #define SCU_MPLL_BYPASS			BIT(24)
47 #define SCU_MPLL_TURN_OFF		BIT(23)
48 #define SCU_MPLL_FREQ_MASK		GENMASK(22, 0)
49 
50 #define SCU_MPLL_FREQ_400M		0x0008405F
51 #define SCU_MPLL_EXT_400M		0x00000031
52 //#define SCU_MPLL_FREQ_400M		0x0038007F
53 //#define SCU_MPLL_EXT_400M		0x0000003F
54 #define SCU_MPLL_FREQ_200M		0x0078007F
55 #define SCU_MPLL_EXT_200M		0x0000003F
56 
57 /* MPLL configuration */
58 #if defined(CONFIG_ASPEED_DDR4_800)
59 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_200M
60 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_200M
61 #elif defined(CONFIG_ASPEED_DDR4_1600)
62 #define SCU_MPLL_FREQ_CFG		SCU_MPLL_FREQ_400M
63 #define SCU_MPLL_EXT_CFG		SCU_MPLL_EXT_400M
64 #else
65 #error "undefined DDR4 target rate\n"
66 #endif
67 
68 /* AC timing and SDRAM mode registers */
69 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
70 /* mode register settings for FPGA are fixed */
71 #define DDR4_MR01_MODE		0x03010100
72 #define DDR4_MR23_MODE		0x00000000
73 #define DDR4_MR45_MODE		0x04C00000
74 #define DDR4_MR6_MODE		0x00000050
75 #define DDR4_TRFC_FPGA		0x17263434
76 
77 /* FPGA need for an additional initialization procedure: search read window */
78 #define SEARCH_RDWIN_ANCHOR_0   (CONFIG_SYS_SDRAM_BASE + 0x0000)
79 #define SEARCH_RDWIN_ANCHOR_1   (CONFIG_SYS_SDRAM_BASE + 0x0004)
80 #define SEARCH_RDWIN_PTRN_0     0x12345678
81 #define SEARCH_RDWIN_PTRN_1     0xaabbccdd
82 #define SEARCH_RDWIN_PTRN_SUM   0xbcf02355
83 #else
84 /* mode register setting for real chip are derived from the model GDDR4-1600 */
85 #define DDR4_MR01_MODE		0x03010510
86 #define DDR4_MR23_MODE		0x00000000
87 #define DDR4_MR45_MODE		0x04000000
88 #define DDR4_MR6_MODE           0x00000400
89 #define DDR4_TRFC_1600		0x467299f1
90 #define DDR4_TRFC_800		0x23394c78
91 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                           \
92 	  defined(CONFIG_ASPEED_PALLADIUM)" */
93 
94 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
95 #define DDR4_TRFC			DDR4_TRFC_FPGA
96 #else
97 /* real chip setting */
98 #if defined(CONFIG_ASPEED_DDR4_1600)
99 #define DDR4_TRFC			DDR4_TRFC_1600
100 #define DDR4_PHY_TRAIN_TRFC		0xc30
101 #elif defined(CONFIG_ASPEED_DDR4_800)
102 #define DDR4_TRFC			DDR4_TRFC_800
103 #define DDR4_PHY_TRAIN_TRFC		0x618
104 #else
105 #error "undefined tRFC setting"
106 #endif	/* end of "#if (SCU_MPLL_FREQ_CFG == SCU_MPLL_FREQ_400M)" */
107 #endif  /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                          \
108 	   defined(CONFIG_ASPEED_PALLADIUM)" */
109 
110 /* supported SDRAM size */
111 #define SDRAM_SIZE_1KB		(1024U)
112 #define SDRAM_SIZE_1MB		(SDRAM_SIZE_1KB * SDRAM_SIZE_1KB)
113 #define SDRAM_MIN_SIZE		(256 * SDRAM_SIZE_1MB)
114 #define SDRAM_MAX_SIZE		(2048 * SDRAM_SIZE_1MB)
115 
116 
117 DECLARE_GLOBAL_DATA_PTR;
118 
119 /*
120  * Bandwidth configuration parameters for different SDRAM requests.
121  * These are hardcoded settings taken from Aspeed SDK.
122  */
123 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
124 static const u32 ddr4_ac_timing[4] = {0x030C0207, 0x04451133, 0x0E010200,
125                                       0x00000140};
126 
127 static const u32 ddr_max_grant_params[4] = {0x88888888, 0x88888888, 0x88888888,
128                                             0x88888888};
129 #else
130 static const u32 ddr4_ac_timing[4] = {0x040e0307, 0x0f4711f1, 0x0e060304,
131                                       0x00001240};
132 
133 static const u32 ddr_max_grant_params[4] = {0x44444444, 0x44444444, 0x44444444,
134                                             0x44444444};
135 #endif
136 
137 struct dram_info {
138 	struct ram_info info;
139 	struct clk ddr_clk;
140 	struct ast2600_sdrammc_regs *regs;
141 	void __iomem *scu;
142 	struct ast2600_ddr_phy *phy;
143 	void __iomem *phy_setting;
144 	void __iomem *phy_status;
145 	ulong clock_rate;
146 };
147 
148 static void ast2600_sdramphy_kick_training(struct dram_info *info)
149 {
150 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
151         struct ast2600_sdrammc_regs *regs = info->regs;
152         u32 volatile data;
153 
154         writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]);
155 	udelay(5);
156         writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]);
157 	udelay(1000);
158 
159 	while (1) {
160 		data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT;
161 		if (~data) {
162 			break;
163 		}
164 	}
165 
166 #if 0
167 	while (1) {
168 		data = readl(0x1e6e0400) & BIT(1);
169 		if (data) {
170 			break;
171 		}
172 	}
173 #endif
174 #endif
175 }
176 
177 /**
178  * @brief	load DDR-PHY configurations table to the PHY registers
179  * @param[in]	p_tbl - pointer to the configuration table
180  * @param[in]	info - pointer to the DRAM info struct
181  *
182  * There are two sets of MRS (Mode Registers) configuration in ast2600 memory
183  * system: one is in the SDRAM MC (memory controller) which is used in run
184  * time, and the other is in the DDR-PHY IP which is used during DDR-PHY
185  * training.  To make these two configurations align, we overwrite the DDR-PHY
186  * setting by the MC setting before DDR-PHY training.
187 */
188 static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info)
189 {
190 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
191 	u32 reg_base = (u32)info->phy_setting;
192 	u32 addr = p_tbl[0];
193         u32 data;
194         int i = 1;
195 
196         debug("%s:reg base = 0x%08x, 1st addr = 0x%08x\n", __func__, reg_base,
197                addr);
198 
199         /* load PHY configuration table into PHY-setting registers */
200         while (1) {
201                 if (addr < reg_base) {
202                         debug("invalid DDR-PHY addr: 0x%08x\n", addr);
203                         break;
204                 }
205                 data = p_tbl[i++];
206 
207                 if (DDR_PHY_TBL_END == data) {
208                         break;
209                 } else if (DDR_PHY_TBL_CHG_ADDR == data) {
210                         addr = p_tbl[i++];
211                 } else {
212                         writel(data, addr);
213                         addr += 4;
214                 }
215         }
216 
217 	data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0);
218 	data |= DDR4_PHY_TRAIN_TRFC;
219 	writel(data, info->phy_setting + 0x84);
220 
221 #ifdef CONFIG_ASPEED_DDR4_800
222 
223 	debug("Overwrite DDR-PHY MRS by MCR config\n");
224 	/* MR0 and MR1 */
225 	data = readl(&info->regs->mr01_mode_setting);
226 	data =
227 	    ((data & GENMASK(15, 0)) << 16) | ((data & GENMASK(31, 16)) >> 16);
228 	writel(data, reg_base + 0x58);
229 	debug("[%08x] 0x%08x\n", reg_base + 0x58, data);
230 
231 	/* MR2 and MR3 */
232 	data = readl(&info->regs->mr23_mode_setting);
233 	writel(data, reg_base + 0x54);
234 	debug("[%08x] 0x%08x\n", reg_base + 0x54, data);
235 
236 	/* MR4 and MR5 */
237 	data = readl(&info->regs->mr45_mode_setting);
238 	writel(data, reg_base + 0x5c);
239 	debug("[%08x] 0x%08x\n", reg_base + 0x5c, data);
240 
241 	/* MR6 */
242 	data = readl(&info->regs->mr6_mode_setting);
243 	writel(data, reg_base + 0x60);
244 	debug("[%08x] 0x%08x\n", reg_base + 0x60, data);
245 #endif
246 #endif
247 }
248 
249 static void ast2600_sdramphy_show_status(struct dram_info *info)
250 {
251 #if !defined(CONFIG_FPGA_ASPEED) && !defined(CONFIG_ASPEED_PALLADIUM)
252         u32 value, tmp;
253         u32 reg_base = (u32)info->phy_status;
254 
255 	debug("\nSDRAM PHY training report:\n");
256 	/* training status */
257         value = readl(reg_base + 0x00);
258 	debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value);
259         if (value & BIT(3)) {
260                 debug("\tinitial PVT calibration fail\n");
261         }
262         if (value & BIT(5)) {
263                 debug("\truntime calibration fail\n");
264         }
265 
266 	/* PU & PD */
267 	value = readl(reg_base + 0x30);
268 	debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value);
269         debug("  PU = 0x%02x\n", value & 0xff);
270         debug("  PD = 0x%02x\n", (value >> 16) & 0xff);
271 
272 	/* read eye window */
273         value = readl(reg_base + 0x68);
274 	debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value);
275 	debug("  rising edge of read data eye training pass window\n");
276 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
277 	debug("    B0:%d%%\n", tmp);
278 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
279         debug("    B1:%d%%\n", tmp);
280 
281 	value = readl(reg_base + 0xC8);
282 	debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value);
283 	debug("  falling edge of read data eye training pass window\n");
284 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
285 	debug("    B0:%d%%\n", tmp);
286 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
287         debug("    B1:%d%%\n", tmp);
288 
289         /* write eye window */
290         value = readl(reg_base + 0x7c);
291 	debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value);
292 	debug("  rising edge of write data eye training pass window\n");
293 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
294 	debug("    B0:%d%%\n", tmp);
295 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255;
296         debug("    B1:%d%%\n", tmp);
297 
298 	/* read Vref training result */
299         value = readl(reg_base + 0x88);
300 	debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value);
301         debug("  read Vref training result\n");
302 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127;
303 	debug("    B0:%d%%\n", tmp);
304 	tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127;
305         debug("    B1:%d%%\n", tmp);
306 
307         /* write Vref training result */
308         value = readl(reg_base + 0x90);
309 	debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value);
310 	tmp = (((value & GENMASK(5, 0)) >> 0) * 100) / 127;
311         debug("  write Vref training result = %d%%\n", tmp);
312 
313         /* gate train */
314 	value = readl(reg_base + 0x50);
315 	debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value);
316 	debug("  gate training pass window\n");
317 	tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255;
318 	debug("    module 0: %d.%03d\n", (value >> 8) & 0xff, tmp);
319         tmp = (((value & GENMASK(23, 16)) >> 0) * 100) / 255;
320 	debug("    module 1: %d.%03d\n", (value >> 24) & 0xff, tmp);
321 #endif
322 }
323 
324 #define MC_TEST_PATTERN_N 8
325 static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = {
326     0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877,
327     0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253};
328 
329 #define DRAM_MapAdr	81000000
330 #define TIMEOUT_DRAM	5000000
331 int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode)
332 {
333 	unsigned int data;
334 	unsigned int timeout = 0;
335 	struct ast2600_sdrammc_regs *regs = info->regs;
336 
337 	writel(0, &regs->ecc_test_ctrl);
338 	if (mode == 0) {
339 		writel(0x00000085 | (datagen << 3), &regs->ecc_test_ctrl);
340 	} else {
341 		writel(0x000000C1 | (datagen << 3), &regs->ecc_test_ctrl);
342 	}
343 
344 	do {
345 		data = readl(&regs->ecc_test_ctrl) & GENMASK(13, 12);
346 
347 		if (data & BIT(13))
348 			return (0);
349 
350 		if (++timeout > TIMEOUT_DRAM) {
351 			printf("Timeout!!\n");
352 			writel(0, &regs->ecc_test_ctrl);
353 
354 			return (0);
355 		}
356 	} while (!data);
357 
358 	writel(0, &regs->ecc_test_ctrl);
359 
360 	return (1);
361 }
362 
363 int ast2600_sdrammc_cbr_test(struct dram_info *info)
364 {
365 	struct ast2600_sdrammc_regs *regs = info->regs;
366 	u32 i;
367 
368 	writel((DRAM_MapAdr | 0x7fffff), &regs->test_addr);
369 
370 	/* single */
371 	for (i=0; i<8; i++) {
372   		if(!ast2600_sdrammc_dg_test(info, i, 0))   return(0);
373 	}
374 
375 	/* burst */
376 	for (i=0; i<8; i++) {
377   		if(!ast2600_sdrammc_dg_test(info, i, i))   return(0);
378 	}
379 
380 	return(1);
381 }
382 
383 static int ast2600_sdrammc_test(struct dram_info *info)
384 {
385 	struct ast2600_sdrammc_regs *regs = info->regs;
386 
387 	u32 pass_cnt = 0;
388 	u32 fail_cnt = 0;
389 	u32 target_cnt = 2;
390 	u32 test_cnt = 0;
391 	u32 pattern;
392 	u32 i = 0;
393 	bool finish = false;
394 
395 	debug("sdram mc test:\n");
396 	while (finish == false) {
397 		pattern = as2600_sdrammc_test_pattern[i++];
398 		i = i % MC_TEST_PATTERN_N;
399 		debug("  pattern = %08X : ",pattern);
400 		writel(pattern, regs->test_init_val);
401 
402 		if (!ast2600_sdrammc_cbr_test(info)) {
403 			debug("fail\n");
404 			fail_cnt++;
405 		} else {
406 			debug("pass\n");
407 			pass_cnt++;
408 		}
409 
410 		if (++test_cnt == target_cnt) {
411 			finish = true;
412 		}
413 	}
414 	debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt,
415 	       target_cnt);
416 	return fail_cnt;
417 }
418 
419 /**
420  * scu500[14:13]
421  * 	2b'00: VGA memory size = 8MB
422  * 	2b'01: VGA memory size = 16MB
423  * 	2b'10: VGA memory size = 32MB
424  * 	2b'11: VGA memory size = 64MB
425  *
426  * mcr04[3:2]
427  * 	2b'00: VGA memory size = 8MB
428  * 	2b'01: VGA memory size = 16MB
429  * 	2b'10: VGA memory size = 32MB
430  * 	2b'11: VGA memory size = 64MB
431 */
432 static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info)
433 {
434         u32 vga_hwconf;
435         size_t vga_mem_size_base = 8 * 1024 * 1024;
436 
437 	vga_hwconf =
438 	    (readl(info->scu + AST_SCU_HW_STRAP) & SCU_HWSTRAP_VGAMEM_MASK) >>
439 	    SCU_HWSTRAP_VGAMEM_SHIFT;
440 
441 	clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK,
442 			((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) &
443 			 SDRAM_CONF_VGA_SIZE_MASK));
444 
445 	return vga_mem_size_base << vga_hwconf;
446 }
447 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
448 static void ast2600_sdrammc_fpga_set_pll(struct dram_info *info)
449 {
450         u32 data;
451         u32 scu_base = (u32)info->scu;
452 
453         writel(0x00000303, scu_base + AST_SCU_FPGA_PLL);
454 
455         do {
456                 data = readl(scu_base + AST_SCU_FPGA_STATUS);
457         } while (!(data & 0x100));
458 
459         writel(0x00000103, scu_base + AST_SCU_FPGA_PLL);
460 }
461 
462 static int ast2600_sdrammc_search_read_window(struct dram_info *info)
463 {
464         u32 pll, pll_min, pll_max, dat1, offset;
465         u32 win = 0x03, gwin = 0, gwinsize = 0;
466         u32 phy_setting = (u32)info->phy_setting;
467 
468 #ifdef CONFIG_ASPEED_PALLADIUM
469 	writel(0xc, phy_setting + 0x0000);
470 	return (1);
471 #endif
472         writel(SEARCH_RDWIN_PTRN_0, SEARCH_RDWIN_ANCHOR_0);
473         writel(SEARCH_RDWIN_PTRN_1, SEARCH_RDWIN_ANCHOR_1);
474 
475         while (gwin == 0) {
476                 while (!(win & 0x80)) {
477                         debug("Window = 0x%X\n", win);
478                         writel(win, phy_setting + 0x0000);
479 
480                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
481                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
482                         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
483                                 ast2600_sdrammc_fpga_set_pll(info);
484                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
485                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
486                         }
487 
488                         pll_min = 0xfff;
489                         pll_max = 0x0;
490                         pll = 0;
491                         while (pll_max > 0 || pll < 256) {
492                                 ast2600_sdrammc_fpga_set_pll(info);
493                                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
494                                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
495                                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
496                                         if (pll_min > pll) {
497                                                 pll_min = pll;
498                                         }
499                                         if (pll_max < pll) {
500                                                 pll_max = pll;
501                                         }
502                                         debug("%3d_(%3d:%3d)\n", pll, pll_min,
503                                                pll_max);
504                                 } else if (pll_max > 0) {
505                                         pll_min = pll_max - pll_min;
506                                         if (gwinsize < pll_min) {
507                                                 gwin = win;
508                                                 gwinsize = pll_min;
509                                         }
510                                         break;
511                                 }
512                                 pll += 1;
513                         }
514 
515                         if (gwin != 0 && pll_max == 0) {
516                                 break;
517                         }
518                         win = win << 1;
519                 }
520                 if (gwin == 0) {
521                         win = 0x7;
522                 }
523         }
524         debug("Set PLL Read Gating Window = %x\n", gwin);
525         writel(gwin, phy_setting + 0x0000);
526 
527         debug("PLL Read Window training\n");
528         pll_min = 0xfff;
529         pll_max = 0x0;
530 
531         debug("Search Window Start\n");
532         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
533         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
534         while (dat1 == SEARCH_RDWIN_PTRN_SUM) {
535                 ast2600_sdrammc_fpga_set_pll(info);
536                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
537                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
538         }
539 
540         debug("Search Window Margin\n");
541         pll = 0;
542         while (pll_max > 0 || pll < 256) {
543                 ast2600_sdrammc_fpga_set_pll(info);
544                 dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
545                 dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
546                 if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
547                         if (pll_min > pll) {
548                                 pll_min = pll;
549                         }
550                         if (pll_max < pll) {
551                                 pll_max = pll;
552                         }
553                         debug("%3d_(%3d:%3d)\n", pll, pll_min, pll_max);
554                 } else if (pll_max > 0 && (pll_max - pll_min) > 20) {
555                         break;
556                 } else if (pll_max > 0) {
557                         pll_min = 0xfff;
558                         pll_max = 0x0;
559                 }
560                 pll += 1;
561         }
562         if (pll_min < pll_max) {
563                 debug("PLL Read window = %d\n", (pll_max - pll_min));
564                 offset = (pll_max - pll_min) >> 1;
565                 pll_min = 0xfff;
566                 pll = 0;
567                 while (pll < (pll_min + offset)) {
568                         ast2600_sdrammc_fpga_set_pll(info);
569                         dat1 = readl(SEARCH_RDWIN_ANCHOR_0);
570                         dat1 += readl(SEARCH_RDWIN_ANCHOR_1);
571                         if (dat1 == SEARCH_RDWIN_PTRN_SUM) {
572                                 if (pll_min > pll) {
573                                         pll_min = pll;
574                                 }
575                                 debug("%d\n", pll);
576                         } else {
577                                 pll_min = 0xfff;
578                                 pll_max = 0x0;
579                         }
580                         pll += 1;
581                 }
582                 return (1);
583         } else {
584                 debug("PLL Read window training fail\n");
585                 return (0);
586         }
587 }
588 #endif /* end of "#if defined(CONFIG_FPGA_ASPEED) ||                           \
589 	  defined(CONFIG_ASPEED_PALLADIUM)" */
590 
591 /*
592  * Find out RAM size and save it in dram_info
593  *
594  * The procedure is taken from Aspeed SDK
595  */
596 static void ast2600_sdrammc_calc_size(struct dram_info *info)
597 {
598 	/* The controller supports 256/512/1024/2048 MB ram */
599 	size_t ram_size = SDRAM_MIN_SIZE;
600 	const int write_test_offset = 0x100000;
601 	u32 test_pattern = 0xdeadbeef;
602 	u32 cap_param = SDRAM_CONF_CAP_2048M;
603 	u32 refresh_timing_param = DDR4_TRFC;
604 	const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
605 
606 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
607 	     ram_size >>= 1) {
608 		writel(test_pattern, write_addr_base + (ram_size >> 1));
609 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
610 	}
611 
612 	/* One last write to overwrite all wrapped values */
613 	writel(test_pattern, write_addr_base);
614 
615 	/* Reset the pattern and see which value was really written */
616 	test_pattern = 0xdeadbeef;
617 	for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
618 	     ram_size >>= 1) {
619 		if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
620 			break;
621 
622 		--cap_param;
623 		refresh_timing_param >>= 8;
624 		test_pattern = (test_pattern >> 4) | (test_pattern << 28);
625 	}
626 
627 	clrsetbits_le32(&info->regs->ac_timing[1],
628 			(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
629 			((refresh_timing_param & SDRAM_AC_TRFC_MASK)
630 			 << SDRAM_AC_TRFC_SHIFT));
631 
632 	info->info.base = CONFIG_SYS_SDRAM_BASE;
633 	info->info.size = ram_size - (48 * SDRAM_SIZE_1MB) -
634 			  ast2600_sdrammc_get_vga_mem_size(info);
635 	clrsetbits_le32(
636 	    &info->regs->config, SDRAM_CONF_CAP_MASK,
637 	    ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK));
638 }
639 
640 static int ast2600_sdrammc_init_ddr4(struct dram_info *info)
641 {
642         const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN |
643                                MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS |
644                                MCR34_ODT_EN | MCR34_ODT_AUTO_ON |
645                                (0x1 << MCR34_ODT_EXT_SHIFT);
646 
647         /* init SDRAM-PHY only on real chip */
648 	ast2600_sdramphy_init(ast2600_sdramphy_config, info);
649         writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS),
650                &info->regs->power_ctrl);
651 	udelay(5);
652 	ast2600_sdramphy_kick_training(info);
653 	udelay(500);
654         writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing);
655 
656         writel(MCR30_SET_MR(3), &info->regs->mode_setting_control);
657         writel(MCR30_SET_MR(6), &info->regs->mode_setting_control);
658         writel(MCR30_SET_MR(5), &info->regs->mode_setting_control);
659         writel(MCR30_SET_MR(4), &info->regs->mode_setting_control);
660         writel(MCR30_SET_MR(2), &info->regs->mode_setting_control);
661         writel(MCR30_SET_MR(1), &info->regs->mode_setting_control);
662         writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN,
663                &info->regs->mode_setting_control);
664 
665 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
666 
667         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
668                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT),
669                &info->regs->refresh_timing);
670 #else
671         writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN |
672                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT),
673                &info->regs->refresh_timing);
674 #endif
675 
676         /* wait self-refresh idle */
677         while (readl(&info->regs->power_ctrl) & MCR34_SELF_REFRESH_STATUS_MASK)
678                 ;
679 
680 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
681         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
682                    SDRAM_REFRESH_ZQCS_EN |
683                    (0x5d << SDRAM_REFRESH_PERIOD_SHIFT) |
684                    (0x4000 << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
685                &info->regs->refresh_timing);
686 #else
687         writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN |
688                    SDRAM_REFRESH_ZQCS_EN |
689                    (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) |
690                    (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT),
691                &info->regs->refresh_timing);
692 #endif
693 
694         writel(power_ctrl, &info->regs->power_ctrl);
695 	udelay(500);
696 
697 #if defined(CONFIG_FPGA_ASPEED)
698         /* toggle Vref training */
699         setbits_le32(&info->regs->mr6_mode_setting, 0x80);
700         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
701                &info->regs->mode_setting_control);
702         clrbits_le32(&info->regs->mr6_mode_setting, 0x80);
703         writel(MCR30_RESET_DLL_DELAY_EN | MCR30_SET_MR(6),
704                &info->regs->mode_setting_control);
705 #endif
706 	return 0;
707 }
708 
709 static void ast2600_sdrammc_unlock(struct dram_info *info)
710 {
711 	writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
712 	while (!readl(&info->regs->protection_key))
713 		;
714 }
715 
716 static void ast2600_sdrammc_lock(struct dram_info *info)
717 {
718 	writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
719 	while (readl(&info->regs->protection_key))
720 		;
721 }
722 
723 static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs)
724 {
725 	int i;
726 
727         writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl);
728         writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key);
729         writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT,
730                &regs->arbitration_ctrl);
731         writel(0xFFBBFFF4, &regs->req_limit_mask);
732 
733 	for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
734                 writel(ddr_max_grant_params[i], &regs->max_grant_len[i]);
735 
736         writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl);
737 
738         /* FIXME: the sample code does NOT match the datasheet */
739         writel(0x07FFFFFF, &regs->ecc_range_ctrl);
740 
741         writel(0, &regs->ecc_test_ctrl);
742         writel(0, &regs->test_addr);
743         writel(0, &regs->test_fail_dq_bit);
744         writel(0, &regs->test_init_val);
745 
746         writel(0xFFFFFFFF, &regs->req_input_ctrl);
747         writel(0, &regs->req_high_pri_ctrl);
748 
749         udelay(600);
750 
751 #ifdef CONFIG_ASPEED_DDR4_DUALX8
752 	writel(0x37, &regs->config);
753 #else
754 	writel(0x17, &regs->config);
755 #endif
756 
757 	/* load controller setting */
758 	for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
759 		writel(ddr4_ac_timing[i], &regs->ac_timing[i]);
760 
761 	writel(DDR4_MR01_MODE, &regs->mr01_mode_setting);
762 	writel(DDR4_MR23_MODE, &regs->mr23_mode_setting);
763 	writel(DDR4_MR45_MODE, &regs->mr45_mode_setting);
764 	writel(DDR4_MR6_MODE, &regs->mr6_mode_setting);
765 }
766 
767 #ifdef CONFIG_ASPEED_ECC
768 static void ast2600_sdrammc_ecc_enable(struct dram_info *info)
769 {
770 	struct ast2600_sdrammc_regs *regs = info->regs;
771 	u32 reg;
772 
773 	writel((info->info.size >> 20) << 20, &regs->ecc_range_ctrl);
774 	reg = readl(&regs->config) |
775 	      (SDRAM_CONF_ECC_EN | SDRAM_CONF_ECC_AUTO_SCRUBBING);
776 	writel(reg, &regs->config);
777 
778 
779         writel(0, &regs->test_init_val);
780         writel(0, &regs->test_addr);
781         writel(0x221, &regs->ecc_test_ctrl);
782         while (0 == (readl(&regs->ecc_test_ctrl) & BIT(12)));
783         writel(0, &regs->ecc_test_ctrl);
784         writel(BIT(31), &regs->intr_ctrl);
785         writel(0, &regs->intr_ctrl);
786 
787 	/* reported size is updated */
788 	info->info.size = (info->info.size / 9) * 8;
789 }
790 #endif
791 
792 static int ast2600_sdrammc_probe(struct udevice *dev)
793 {
794 	struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
795 	struct ast2600_sdrammc_regs *regs = priv->regs;
796 	struct udevice *clk_dev;
797 	int ret;
798 	volatile uint32_t reg;
799 
800 	/* find SCU base address from clock device */
801 	ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu),
802                                           &clk_dev);
803 	if (ret) {
804 		debug("clock device not defined\n");
805 		return ret;
806 	}
807 
808 	priv->scu = devfdt_get_addr_ptr(clk_dev);
809 	if (IS_ERR(priv->scu)) {
810 		debug("%s(): can't get SCU\n", __func__);
811 		return PTR_ERR(priv->scu);
812 	}
813 
814 	if (readl(priv->scu + AST_SCU_HANDSHAKE) & SCU_SDRAM_INIT_READY_MASK) {
815 		debug("%s(): DDR SDRAM had been initialized\n", __func__);
816 		ast2600_sdrammc_calc_size(priv);
817 		return 0;
818 	}
819 
820 #ifdef AST2600_SDRAMMC_MANUAL_CLK
821 	reg = readl(priv->scu + AST_SCU_MPLL);
822 	reg &= ~(BIT(24) | GENMASK(22, 0));
823 	reg |= (BIT(25) | BIT(23) | SCU_MPLL_FREQ_CFG);
824 	writel(reg, priv->scu + AST_SCU_MPLL);
825         writel(SCU_MPLL_EXT_CFG, priv->scu + AST_SCU_MPLL_EXT);
826 	udelay(100);
827 	reg &= ~(BIT(25) | BIT(23));
828 	writel(reg, priv->scu + AST_SCU_MPLL);
829 	while(0 == (readl(priv->scu + AST_SCU_MPLL_EXT) & BIT(31)));
830 #else
831 	ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
832 	if (ret) {
833 		debug("DDR:No CLK\n");
834 		return ret;
835 	}
836 	clk_set_rate(&priv->ddr_clk, priv->clock_rate);
837 #endif
838 
839 #if 0
840 	/* FIXME: enable the following code if reset-driver is ready */
841 	struct reset_ctl reset_ctl;
842 	ret = reset_get_by_index(dev, 0, &reset_ctl);
843 	if (ret) {
844 		debug("%s(): Failed to get reset signal\n", __func__);
845 		return ret;
846 	}
847 
848 	ret = reset_assert(&reset_ctl);
849 	if (ret) {
850 		debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
851 		return ret;
852 	}
853 #endif
854 
855 	ast2600_sdrammc_unlock(priv);
856 	ast2600_sdrammc_common_init(regs);
857 
858 	ast2600_sdrammc_init_ddr4(priv);
859 
860 #if defined(CONFIG_FPGA_ASPEED) || defined(CONFIG_ASPEED_PALLADIUM)
861         ast2600_sdrammc_search_read_window(priv);
862 #else
863 	/* make sure DDR-PHY is ready before access */
864 	do {
865 		reg = readl(priv->phy_status) & BIT(1);
866 	} while(reg == 0);
867 #endif
868 
869 	ast2600_sdramphy_show_status(priv);
870 	ast2600_sdrammc_calc_size(priv);
871 
872         if (0 != ast2600_sdrammc_test(priv)) {
873 		printf("%s: DDR4 init fail\n", __func__);
874 		return -EINVAL;
875 	}
876 
877 #ifdef CONFIG_ASPEED_ECC
878 	ast2600_sdrammc_ecc_enable(priv);
879 #endif
880 
881 	writel(readl(priv->scu + AST_SCU_HANDSHAKE) | SCU_SDRAM_INIT_READY_MASK,
882 	       priv->scu + AST_SCU_HANDSHAKE);
883 
884 	clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
885 	ast2600_sdrammc_lock(priv);
886 	return 0;
887 }
888 
889 static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev)
890 {
891 	struct dram_info *priv = dev_get_priv(dev);
892 
893 	priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
894 	priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1);
895 	priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2);
896 
897 	priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
898 					  "clock-frequency", 0);
899 	if (!priv->clock_rate) {
900 		debug("DDR Clock Rate not defined\n");
901 		return -EINVAL;
902 	}
903 
904 	return 0;
905 }
906 
907 static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
908 {
909 	struct dram_info *priv = dev_get_priv(dev);
910 
911 	*info = priv->info;
912 
913 	return 0;
914 }
915 
916 static struct ram_ops ast2600_sdrammc_ops = {
917 	.get_info = ast2600_sdrammc_get_info,
918 };
919 
920 static const struct udevice_id ast2600_sdrammc_ids[] = {
921 	{ .compatible = "aspeed,ast2600-sdrammc" },
922 	{ }
923 };
924 
925 U_BOOT_DRIVER(sdrammc_ast2600) = {
926 	.name = "aspeed_ast2600_sdrammc",
927 	.id = UCLASS_RAM,
928 	.of_match = ast2600_sdrammc_ids,
929 	.ops = &ast2600_sdrammc_ops,
930 	.ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata,
931 	.probe = ast2600_sdrammc_probe,
932 	.priv_auto_alloc_size = sizeof(struct dram_info),
933 };
934