1bef0c53 | 23-Sep-2018 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: fix linking of standalone programs
Use the global MIPS specific u-boot.lds for linking standalone programs instead of the outdated ones in examples/standalone/. Also pass --gc-sections in LDFL
MIPS: fix linking of standalone programs
Use the global MIPS specific u-boot.lds for linking standalone programs instead of the outdated ones in examples/standalone/. Also pass --gc-sections in LDFLAGS_STANDALONE to optimize the size of standalone programs. Finally remove the deprecated config.mk files in arch/mips/cpu/mips[32,64]/.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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ee422142 | 24-Apr-2017 |
Álvaro Fernández Rojas <noltari@gmail.com> |
MIPS: add initial infrastructure for Broadcom MIPS SoCs
CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez
MIPS: add initial infrastructure for Broadcom MIPS SoCs
CFE checks CPU Thread in a different way (using register $22): mfc0 t1, C0_BCM_CONFIG, 3 # $22 li t2, CP0_CMT_TPID # (1 << 31) and t1, t2 bnez t1, 2f # if we are running on thread 1, skip init nop
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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924ad866 | 04-Jun-2016 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: add possibility to setup initial stack and global data in SRAM
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together w
MIPS: add possibility to setup initial stack and global data in SRAM
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which a SoC can select if it supports some kind of SRAM. Together with CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be set up in that SRAM. This can be used to provide a C environment also for lowlevel_init().
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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c3e72ab8 | 25-Sep-2016 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: factor out code for initial stack and global data
Move the code for setting up the initial stack and global data to a macro to be able to use it more than once.
Signed-off-by: Daniel Schwierz
MIPS: factor out code for initial stack and global data
Move the code for setting up the initial stack and global data to a macro to be able to use it more than once.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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65d297af | 07-Feb-2016 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: fix iand optimize setup of CP0 registers
Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exc
MIPS: fix iand optimize setup of CP0 registers
Clear cp0 status while preserving implementation specific bits. Set bits BEV and ERL as the arch specification requires after a reset or soft-reset exception.
Extend and fix initialization of watch registers. Check if additional watch register sets are implemented and initialize them too.
Initialize cp0 count as early as possible to get the most accurate boot timing.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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345490fc | 07-Feb-2016 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: fix ROM exception vectors
When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI e
MIPS: fix ROM exception vectors
When booting from ROM, early exceptions can't be handled properly. Instead of busy-looping give the developer the possibilty to examine the situation. Invoke an UHI exception operation which can be read as unhandled exception by a hardware debugger if one is attached. If the debugger doesn't support UHI, the exception is read as unexpected breakpoint.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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31d36f74 | 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Hang if run on a secondary CPU
Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on mul
MIPS: Hang if run on a secondary CPU
Some systems are configured such that multiple CPUs begin running from their reset vector following a system reset. If this occurs then U-Boot will be run on multiple CPUs simultaneously, which causes all sorts of issues as the multiple instances of U-Boot clobber each other.
Prevent this from happening by simply hanging with an infinite loop if we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum as appropriate, is non-zero.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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f8981277 | 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: If we don't need DDR for cache init, init cache first
On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
MIPS: If we don't need DDR for cache init, init cache first
On systems where cache initialisation doesn't require zeroed memory (ie. systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined) perform cache initialisation prior to lowlevel_init & DDR initialisation. This allows for DDR initialisation code to run cached & thus significantly faster.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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4f9226b4 | 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Preserve Config implementation-defined bits
The coprocessor 0 Config register includes 9 implementation defined bits, which in some processors do things like enable write combining or other fu
MIPS: Preserve Config implementation-defined bits
The coprocessor 0 Config register includes 9 implementation defined bits, which in some processors do things like enable write combining or other functionality. We ought not to wipe them to 0 during boot. Rather than doing so, preserve their value & only clear the bits standardised by the MIPS architecture.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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