1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * 5 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_TRATS_H 11 #define __CONFIG_TRATS_H 12 13 #include <configs/exynos4-common.h> 14 15 #define CONFIG_TRATS 16 17 #define CONFIG_TIZEN /* TIZEN lib */ 18 19 #define CONFIG_SYS_L2CACHE_OFF 20 #ifndef CONFIG_SYS_L2CACHE_OFF 21 #define CONFIG_SYS_L2_PL310 22 #define CONFIG_SYS_PL310_BASE 0x10502000 23 #endif 24 25 /* TRATS has 4 banks of DRAM */ 26 #define CONFIG_NR_DRAM_BANKS 4 27 #define CONFIG_SYS_SDRAM_BASE 0x40000000 28 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 29 #define CONFIG_SYS_TEXT_BASE 0x63300000 30 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 31 32 /* memtest works on */ 33 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 34 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) 35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) 36 37 #define CONFIG_SYS_TEXT_BASE 0x63300000 38 39 /* select serial console configuration */ 40 #define CONFIG_SERIAL2 41 #define CONFIG_BAUDRATE 115200 42 43 /* Console configuration */ 44 45 /* MACH_TYPE_TRATS macro will be removed once added to mach-types */ 46 #define MACH_TYPE_TRATS 3928 47 #define CONFIG_MACH_TYPE MACH_TYPE_TRATS 48 49 #define CONFIG_BOOTARGS "Please use defined boot" 50 #define CONFIG_BOOTCOMMAND "run autoboot" 51 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" 52 53 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 54 - GENERATED_GBL_DATA_SIZE) 55 56 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ 57 58 #define CONFIG_SYS_MONITOR_BASE 0x00000000 59 60 #define CONFIG_BOOTBLOCK "10" 61 #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" 62 63 #define CONFIG_ENV_IS_IN_MMC 64 #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV 65 #define CONFIG_ENV_SIZE 4096 66 #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ 67 68 #define CONFIG_ENV_OVERWRITE 69 70 #define CONFIG_ENV_VARS_UBOOT_CONFIG 71 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 72 73 /* Tizen - partitions definitions */ 74 #define PARTS_CSA "csa-mmc" 75 #define PARTS_BOOT "boot" 76 #define PARTS_QBOOT "qboot" 77 #define PARTS_CSC "csc" 78 #define PARTS_ROOT "platform" 79 #define PARTS_DATA "data" 80 #define PARTS_UMS "ums" 81 82 #define PARTS_DEFAULT \ 83 "uuid_disk=${uuid_gpt_disk};" \ 84 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ 85 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ 86 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ 87 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ 88 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ 89 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ 90 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ 91 92 #define CONFIG_DFU_ALT \ 93 "u-boot raw 0x80 0x400;" \ 94 "/uImage ext4 0 2;" \ 95 "/modem.bin ext4 0 2;" \ 96 "/exynos4210-trats.dtb ext4 0 2;" \ 97 ""PARTS_CSA" part 0 1;" \ 98 ""PARTS_BOOT" part 0 2;" \ 99 ""PARTS_QBOOT" part 0 3;" \ 100 ""PARTS_CSC" part 0 4;" \ 101 ""PARTS_ROOT" part 0 5;" \ 102 ""PARTS_DATA" part 0 6;" \ 103 ""PARTS_UMS" part 0 7;" \ 104 "params.bin raw 0x38 0x8;" \ 105 "/Image.itb ext4 0 2\0" 106 107 #define CONFIG_EXTRA_ENV_SETTINGS \ 108 "bootk=" \ 109 "run loaduimage;" \ 110 "if run loaddtb; then " \ 111 "bootm 0x40007FC0 - ${fdtaddr};" \ 112 "fi;" \ 113 "bootm 0x40007FC0;\0" \ 114 "updatebackup=" \ 115 "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ 116 "mmc dev 0 0\0" \ 117 "updatebootb=" \ 118 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ 119 "lpj=lpj=3981312\0" \ 120 "nfsboot=" \ 121 "setenv bootargs root=/dev/nfs rw " \ 122 "nfsroot=${nfsroot},nolock,tcp " \ 123 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 124 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ 125 "; run bootk\0" \ 126 "ramfsboot=" \ 127 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ 128 "${console} ${meminfo} " \ 129 "initrd=0x43000000,8M ramdisk=8192\0" \ 130 "mmcboot=" \ 131 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 132 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ 133 "run bootk\0" \ 134 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ 135 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 136 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ 137 "verify=n\0" \ 138 "rootfstype=ext4\0" \ 139 "console=" CONFIG_DEFAULT_CONSOLE \ 140 "meminfo=crashkernel=32M@0x50000000\0" \ 141 "nfsroot=/nfsroot/arm\0" \ 142 "bootblock=" CONFIG_BOOTBLOCK "\0" \ 143 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ 144 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ 145 "${fdtfile}\0" \ 146 "mmcdev=0\0" \ 147 "mmcbootpart=2\0" \ 148 "mmcrootpart=5\0" \ 149 "opts=always_resume=1\0" \ 150 "partitions=" PARTS_DEFAULT \ 151 "dfu_alt_info=" CONFIG_DFU_ALT \ 152 "spladdr=0x40000100\0" \ 153 "splsize=0x200\0" \ 154 "splfile=falcon.bin\0" \ 155 "spl_export=" \ 156 "setexpr spl_imgsize ${splsize} + 8 ;" \ 157 "setenv spl_imgsize 0x${spl_imgsize};" \ 158 "setexpr spl_imgaddr ${spladdr} - 8 ;" \ 159 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ 160 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ 161 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 162 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ 163 "spl export atags 0x40007FC0;" \ 164 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ 165 "mw.l ${spl_addr_tmp} ${splsize};" \ 166 "ext4write mmc ${mmcdev}:${mmcbootpart}" \ 167 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ 168 "setenv spl_imgsize;" \ 169 "setenv spl_imgaddr;" \ 170 "setenv spl_addr_tmp;\0" \ 171 CONFIG_EXTRA_ENV_ITB \ 172 "fdtaddr=40800000\0" \ 173 174 /* Falcon mode definitions */ 175 #define CONFIG_CMD_SPL 176 #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 177 178 /* GPT */ 179 #define CONFIG_RANDOM_UUID 180 181 /* I2C */ 182 #include <asm/arch/gpio.h> 183 184 #define CONFIG_SYS_I2C 185 #define CONFIG_SYS_I2C_S3C24X0 186 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 187 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE 188 #define CONFIG_MAX_I2C_NUM 8 189 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 190 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 191 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 192 #define CONFIG_SOFT_I2C_READ_REPEATED_START 193 #define CONFIG_SYS_I2C_INIT_BOARD 194 195 /* I2C FG */ 196 #define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41 197 #define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40 198 199 /* POWER */ 200 #define CONFIG_POWER 201 #define CONFIG_POWER_I2C 202 #define CONFIG_POWER_MAX8997 203 204 #define CONFIG_POWER_FG 205 #define CONFIG_POWER_FG_MAX17042 206 #define CONFIG_POWER_MUIC 207 #define CONFIG_POWER_MUIC_MAX8997 208 #define CONFIG_POWER_BATTERY 209 #define CONFIG_POWER_BATTERY_TRATS 210 211 /* Security subsystem - enable hw_rand() */ 212 #define CONFIG_EXYNOS_ACE_SHA 213 #define CONFIG_LIB_HW_RAND 214 215 /* Common misc for Samsung */ 216 #define CONFIG_MISC_COMMON 217 218 #define CONFIG_MISC_INIT_R 219 220 /* Download menu - Samsung common */ 221 #define CONFIG_LCD_MENU 222 #define CONFIG_LCD_MENU_BOARD 223 224 /* Download menu - definitions for check keys */ 225 #ifndef __ASSEMBLY__ 226 #include <power/max8997_pmic.h> 227 228 #define KEY_PWR_PMIC_NAME "MAX8997_PMIC" 229 #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 230 #define KEY_PWR_STATUS_MASK (1 << 0) 231 #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 232 #define KEY_PWR_INTERRUPT_MASK (1 << 0) 233 234 #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 235 #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 236 #endif /* __ASSEMBLY__ */ 237 238 /* LCD console */ 239 #define LCD_BPP LCD_COLOR16 240 #define CONFIG_SYS_WHITE_ON_BLACK 241 242 /* LCD */ 243 #define CONFIG_BMP_16BPP 244 #define CONFIG_FB_ADDR 0x52504000 245 #define CONFIG_EXYNOS_MIPI_DSIM 246 #define CONFIG_VIDEO_BMP_GZIP 247 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) 248 249 #endif /* __CONFIG_H */ 250