1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2013 4 * Texas Instruments Incorporated, <www.ti.com> 5 * 6 * Lokesh Vutla <lokeshvutla@ti.com> 7 * 8 * Based on previous work by: 9 * Aneesh V <aneesh@ti.com> 10 * Steve Sakoman <steve@sakoman.com> 11 */ 12 #include <common.h> 13 #include <palmas.h> 14 #include <sata.h> 15 #include <linux/string.h> 16 #include <asm/gpio.h> 17 #include <usb.h> 18 #include <linux/usb/gadget.h> 19 #include <asm/omap_common.h> 20 #include <asm/omap_sec_common.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/dra7xx_iodelay.h> 23 #include <asm/emif.h> 24 #include <asm/arch/sys_proto.h> 25 #include <asm/arch/mmc_host_def.h> 26 #include <asm/arch/sata.h> 27 #include <environment.h> 28 #include <dwc3-uboot.h> 29 #include <dwc3-omap-uboot.h> 30 #include <ti-usb-phy-uboot.h> 31 #include <miiphy.h> 32 33 #include "mux_data.h" 34 #include "../common/board_detect.h" 35 36 #define board_is_dra76x_evm() board_ti_is("DRA76/7x") 37 #define board_is_dra74x_evm() board_ti_is("5777xCPU") 38 #define board_is_dra72x_evm() board_ti_is("DRA72x-T") 39 #define board_is_dra71x_evm() board_ti_is("DRA79x,D") 40 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \ 41 (strncmp("H", board_ti_get_rev(), 1) <= 0)) 42 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \ 43 (strncmp("C", board_ti_get_rev(), 1) <= 0)) 44 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ 45 board_ti_get_emif2_size() 46 47 #ifdef CONFIG_DRIVER_TI_CPSW 48 #include <cpsw.h> 49 #endif 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 /* GPIO 7_11 */ 54 #define GPIO_DDR_VTT_EN 203 55 56 #define SYSINFO_BOARD_NAME_MAX_LEN 37 57 58 const struct omap_sysinfo sysinfo = { 59 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" 60 }; 61 62 static const struct emif_regs emif1_ddr3_532_mhz_1cs = { 63 .sdram_config_init = 0x61851ab2, 64 .sdram_config = 0x61851ab2, 65 .sdram_config2 = 0x08000000, 66 .ref_ctrl = 0x000040F1, 67 .ref_ctrl_final = 0x00001035, 68 .sdram_tim1 = 0xCCCF36B3, 69 .sdram_tim2 = 0x308F7FDA, 70 .sdram_tim3 = 0x427F88A8, 71 .read_idle_ctrl = 0x00050000, 72 .zq_config = 0x0007190B, 73 .temp_alert_config = 0x00000000, 74 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 75 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 76 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 77 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 78 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 79 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 80 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 81 .emif_rd_wr_lvl_rmp_win = 0x00000000, 82 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 83 .emif_rd_wr_lvl_ctl = 0x00000000, 84 .emif_rd_wr_exec_thresh = 0x00000305 85 }; 86 87 static const struct emif_regs emif2_ddr3_532_mhz_1cs = { 88 .sdram_config_init = 0x61851B32, 89 .sdram_config = 0x61851B32, 90 .sdram_config2 = 0x08000000, 91 .ref_ctrl = 0x000040F1, 92 .ref_ctrl_final = 0x00001035, 93 .sdram_tim1 = 0xCCCF36B3, 94 .sdram_tim2 = 0x308F7FDA, 95 .sdram_tim3 = 0x427F88A8, 96 .read_idle_ctrl = 0x00050000, 97 .zq_config = 0x0007190B, 98 .temp_alert_config = 0x00000000, 99 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 100 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 101 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 102 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 103 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 104 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 105 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 106 .emif_rd_wr_lvl_rmp_win = 0x00000000, 107 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 108 .emif_rd_wr_lvl_ctl = 0x00000000, 109 .emif_rd_wr_exec_thresh = 0x00000305 110 }; 111 112 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { 113 .sdram_config_init = 0x61862B32, 114 .sdram_config = 0x61862B32, 115 .sdram_config2 = 0x08000000, 116 .ref_ctrl = 0x0000514C, 117 .ref_ctrl_final = 0x0000144A, 118 .sdram_tim1 = 0xD113781C, 119 .sdram_tim2 = 0x30717FE3, 120 .sdram_tim3 = 0x409F86A8, 121 .read_idle_ctrl = 0x00050000, 122 .zq_config = 0x5007190B, 123 .temp_alert_config = 0x00000000, 124 .emif_ddr_phy_ctlr_1_init = 0x0024400D, 125 .emif_ddr_phy_ctlr_1 = 0x0E24400D, 126 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 127 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, 128 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, 129 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, 130 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, 131 .emif_rd_wr_lvl_rmp_win = 0x00000000, 132 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 133 .emif_rd_wr_lvl_ctl = 0x00000000, 134 .emif_rd_wr_exec_thresh = 0x00000305 135 }; 136 137 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { 138 .sdram_config_init = 0x61862BB2, 139 .sdram_config = 0x61862BB2, 140 .sdram_config2 = 0x00000000, 141 .ref_ctrl = 0x0000514D, 142 .ref_ctrl_final = 0x0000144A, 143 .sdram_tim1 = 0xD1137824, 144 .sdram_tim2 = 0x30B37FE3, 145 .sdram_tim3 = 0x409F8AD8, 146 .read_idle_ctrl = 0x00050000, 147 .zq_config = 0x5007190B, 148 .temp_alert_config = 0x00000000, 149 .emif_ddr_phy_ctlr_1_init = 0x0824400E, 150 .emif_ddr_phy_ctlr_1 = 0x0E24400E, 151 .emif_ddr_ext_phy_ctrl_1 = 0x04040100, 152 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, 153 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, 154 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, 155 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, 156 .emif_rd_wr_lvl_rmp_win = 0x00000000, 157 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 158 .emif_rd_wr_lvl_ctl = 0x00000000, 159 .emif_rd_wr_exec_thresh = 0x00000305 160 }; 161 162 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { 163 .sdram_config_init = 0x61851ab2, 164 .sdram_config = 0x61851ab2, 165 .sdram_config2 = 0x08000000, 166 .ref_ctrl = 0x000040F1, 167 .ref_ctrl_final = 0x00001035, 168 .sdram_tim1 = 0xCCCF36B3, 169 .sdram_tim2 = 0x30BF7FDA, 170 .sdram_tim3 = 0x427F8BA8, 171 .read_idle_ctrl = 0x00050000, 172 .zq_config = 0x0007190B, 173 .temp_alert_config = 0x00000000, 174 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 175 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 176 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 177 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 178 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 179 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 180 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 181 .emif_rd_wr_lvl_rmp_win = 0x00000000, 182 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 183 .emif_rd_wr_lvl_ctl = 0x00000000, 184 .emif_rd_wr_exec_thresh = 0x00000305 185 }; 186 187 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { 188 .sdram_config_init = 0x61851B32, 189 .sdram_config = 0x61851B32, 190 .sdram_config2 = 0x08000000, 191 .ref_ctrl = 0x000040F1, 192 .ref_ctrl_final = 0x00001035, 193 .sdram_tim1 = 0xCCCF36B3, 194 .sdram_tim2 = 0x308F7FDA, 195 .sdram_tim3 = 0x427F88A8, 196 .read_idle_ctrl = 0x00050000, 197 .zq_config = 0x0007190B, 198 .temp_alert_config = 0x00000000, 199 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 200 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 201 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 202 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 203 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 204 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 205 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 206 .emif_rd_wr_lvl_rmp_win = 0x00000000, 207 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 208 .emif_rd_wr_lvl_ctl = 0x00000000, 209 .emif_rd_wr_exec_thresh = 0x00000305 210 }; 211 212 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = { 213 .sdram_config_init = 0x61862B32, 214 .sdram_config = 0x61862B32, 215 .sdram_config2 = 0x00000000, 216 .ref_ctrl = 0x0000514C, 217 .ref_ctrl_final = 0x0000144A, 218 .sdram_tim1 = 0xD113783C, 219 .sdram_tim2 = 0x30B47FE3, 220 .sdram_tim3 = 0x409F8AD8, 221 .read_idle_ctrl = 0x00050000, 222 .zq_config = 0x5007190B, 223 .temp_alert_config = 0x00000000, 224 .emif_ddr_phy_ctlr_1_init = 0x0824400D, 225 .emif_ddr_phy_ctlr_1 = 0x0E24400D, 226 .emif_ddr_ext_phy_ctrl_1 = 0x04040100, 227 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, 228 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, 229 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, 230 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, 231 .emif_rd_wr_lvl_rmp_win = 0x00000000, 232 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 233 .emif_rd_wr_lvl_ctl = 0x00000000, 234 .emif_rd_wr_exec_thresh = 0x00000305 235 }; 236 237 const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = { 238 .sdram_config_init = 0x61862B32, 239 .sdram_config = 0x61862B32, 240 .sdram_config2 = 0x00000000, 241 .ref_ctrl = 0x0000514C, 242 .ref_ctrl_final = 0x0000144A, 243 .sdram_tim1 = 0xD113781C, 244 .sdram_tim2 = 0x30B47FE3, 245 .sdram_tim3 = 0x409F8AD8, 246 .read_idle_ctrl = 0x00050000, 247 .zq_config = 0x5007190B, 248 .temp_alert_config = 0x00000000, 249 .emif_ddr_phy_ctlr_1_init = 0x0824400D, 250 .emif_ddr_phy_ctlr_1 = 0x0E24400D, 251 .emif_ddr_ext_phy_ctrl_1 = 0x04040100, 252 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, 253 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, 254 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, 255 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, 256 .emif_rd_wr_lvl_rmp_win = 0x00000000, 257 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 258 .emif_rd_wr_lvl_ctl = 0x00000000, 259 .emif_rd_wr_exec_thresh = 0x00000305 260 }; 261 262 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 263 { 264 u64 ram_size; 265 266 ram_size = board_ti_get_emif_size(); 267 268 switch (omap_revision()) { 269 case DRA752_ES1_0: 270 case DRA752_ES1_1: 271 case DRA752_ES2_0: 272 switch (emif_nr) { 273 case 1: 274 if (ram_size > CONFIG_MAX_MEM_MAPPED) 275 *regs = &emif1_ddr3_532_mhz_1cs_2G; 276 else 277 *regs = &emif1_ddr3_532_mhz_1cs; 278 break; 279 case 2: 280 if (ram_size > CONFIG_MAX_MEM_MAPPED) 281 *regs = &emif2_ddr3_532_mhz_1cs_2G; 282 else 283 *regs = &emif2_ddr3_532_mhz_1cs; 284 break; 285 } 286 break; 287 case DRA762_ABZ_ES1_0: 288 case DRA762_ACD_ES1_0: 289 case DRA762_ES1_0: 290 if (emif_nr == 1) 291 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76; 292 else 293 *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76; 294 break; 295 case DRA722_ES1_0: 296 case DRA722_ES2_0: 297 case DRA722_ES2_1: 298 if (ram_size < CONFIG_MAX_MEM_MAPPED) 299 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; 300 else 301 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; 302 break; 303 default: 304 *regs = &emif1_ddr3_532_mhz_1cs; 305 } 306 } 307 308 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = { 309 .dmm_lisa_map_0 = 0x0, 310 .dmm_lisa_map_1 = 0x80640300, 311 .dmm_lisa_map_2 = 0xC0500220, 312 .dmm_lisa_map_3 = 0xFF020100, 313 .is_ma_present = 0x1 314 }; 315 316 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { 317 .dmm_lisa_map_0 = 0x0, 318 .dmm_lisa_map_1 = 0x0, 319 .dmm_lisa_map_2 = 0x80600100, 320 .dmm_lisa_map_3 = 0xFF020100, 321 .is_ma_present = 0x1 322 }; 323 324 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { 325 .dmm_lisa_map_0 = 0x0, 326 .dmm_lisa_map_1 = 0x0, 327 .dmm_lisa_map_2 = 0x80740300, 328 .dmm_lisa_map_3 = 0xFF020100, 329 .is_ma_present = 0x1 330 }; 331 332 /* 333 * DRA722 EVM EMIF1 2GB CONFIGURATION 334 * EMIF1 4 devices of 512Mb x 8 Micron 335 */ 336 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = { 337 .dmm_lisa_map_0 = 0x0, 338 .dmm_lisa_map_1 = 0x0, 339 .dmm_lisa_map_2 = 0x80700100, 340 .dmm_lisa_map_3 = 0xFF020100, 341 .is_ma_present = 0x1 342 }; 343 344 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 345 { 346 u64 ram_size; 347 348 ram_size = board_ti_get_emif_size(); 349 350 switch (omap_revision()) { 351 case DRA762_ABZ_ES1_0: 352 case DRA762_ACD_ES1_0: 353 case DRA762_ES1_0: 354 case DRA752_ES1_0: 355 case DRA752_ES1_1: 356 case DRA752_ES2_0: 357 if (ram_size > CONFIG_MAX_MEM_MAPPED) 358 *dmm_lisa_regs = &lisa_map_dra7_2GB; 359 else 360 *dmm_lisa_regs = &lisa_map_dra7_1536MB; 361 break; 362 case DRA722_ES1_0: 363 case DRA722_ES2_0: 364 case DRA722_ES2_1: 365 default: 366 if (ram_size < CONFIG_MAX_MEM_MAPPED) 367 *dmm_lisa_regs = &lisa_map_2G_x_2; 368 else 369 *dmm_lisa_regs = &lisa_map_2G_x_4; 370 break; 371 } 372 } 373 374 struct vcores_data dra752_volts = { 375 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 376 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 377 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 378 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 379 .mpu.pmic = &tps659038, 380 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 381 382 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 383 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 384 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 385 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 386 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 387 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 388 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 389 .eve.addr = TPS659038_REG_ADDR_SMPS45, 390 .eve.pmic = &tps659038, 391 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 392 393 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 394 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 395 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 396 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 397 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 398 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 399 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 400 .gpu.addr = TPS659038_REG_ADDR_SMPS6, 401 .gpu.pmic = &tps659038, 402 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 403 404 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 405 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 406 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 407 .core.addr = TPS659038_REG_ADDR_SMPS7, 408 .core.pmic = &tps659038, 409 410 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 411 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 412 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 413 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 414 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 415 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 416 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 417 .iva.addr = TPS659038_REG_ADDR_SMPS8, 418 .iva.pmic = &tps659038, 419 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 420 }; 421 422 struct vcores_data dra76x_volts = { 423 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 424 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 425 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 426 .mpu.addr = LP87565_REG_ADDR_BUCK01, 427 .mpu.pmic = &lp87565, 428 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 429 430 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 431 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 432 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 433 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 434 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 435 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 436 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 437 .eve.addr = TPS65917_REG_ADDR_SMPS1, 438 .eve.pmic = &tps659038, 439 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 440 441 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 442 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 443 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 444 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 445 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 446 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 447 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 448 .gpu.addr = LP87565_REG_ADDR_BUCK23, 449 .gpu.pmic = &lp87565, 450 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 451 452 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 453 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 454 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 455 .core.addr = TPS65917_REG_ADDR_SMPS3, 456 .core.pmic = &tps659038, 457 458 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 459 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 460 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 461 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 462 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 463 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 464 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 465 .iva.addr = TPS65917_REG_ADDR_SMPS4, 466 .iva.pmic = &tps659038, 467 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 468 }; 469 470 struct vcores_data dra722_volts = { 471 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 472 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 473 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 474 .mpu.addr = TPS65917_REG_ADDR_SMPS1, 475 .mpu.pmic = &tps659038, 476 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 477 478 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 479 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 480 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 481 .core.addr = TPS65917_REG_ADDR_SMPS2, 482 .core.pmic = &tps659038, 483 484 /* 485 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x 486 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. 487 */ 488 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 489 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 490 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 491 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 492 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 493 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 494 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 495 .gpu.addr = TPS65917_REG_ADDR_SMPS3, 496 .gpu.pmic = &tps659038, 497 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 498 499 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 500 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 501 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 502 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 503 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 504 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 505 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 506 .eve.addr = TPS65917_REG_ADDR_SMPS3, 507 .eve.pmic = &tps659038, 508 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 509 510 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 511 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 512 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 513 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 514 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 515 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 516 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 517 .iva.addr = TPS65917_REG_ADDR_SMPS3, 518 .iva.pmic = &tps659038, 519 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 520 }; 521 522 struct vcores_data dra718_volts = { 523 /* 524 * In the case of dra71x GPU MPU and CORE 525 * are all powered up by BUCK0 of LP873X PMIC 526 */ 527 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 528 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 529 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 530 .mpu.addr = LP873X_REG_ADDR_BUCK0, 531 .mpu.pmic = &lp8733, 532 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 533 534 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 535 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 536 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 537 .core.addr = LP873X_REG_ADDR_BUCK0, 538 .core.pmic = &lp8733, 539 540 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 541 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 542 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 543 .gpu.addr = LP873X_REG_ADDR_BUCK0, 544 .gpu.pmic = &lp8733, 545 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 546 547 /* 548 * The DSPEVE and IVA rails are grouped on DRA71x-evm 549 * and are powered by BUCK1 of LP873X PMIC 550 */ 551 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 552 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 553 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 554 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 555 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 556 .eve.addr = LP873X_REG_ADDR_BUCK1, 557 .eve.pmic = &lp8733, 558 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 559 560 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 561 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 562 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 563 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 564 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 565 .iva.addr = LP873X_REG_ADDR_BUCK1, 566 .iva.pmic = &lp8733, 567 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 568 }; 569 570 int get_voltrail_opp(int rail_offset) 571 { 572 int opp; 573 574 switch (rail_offset) { 575 case VOLT_MPU: 576 opp = DRA7_MPU_OPP; 577 /* DRA71x supports only OPP_NOM for MPU */ 578 if (board_is_dra71x_evm()) 579 opp = OPP_NOM; 580 break; 581 case VOLT_CORE: 582 opp = DRA7_CORE_OPP; 583 /* DRA71x supports only OPP_NOM for CORE */ 584 if (board_is_dra71x_evm()) 585 opp = OPP_NOM; 586 break; 587 case VOLT_GPU: 588 opp = DRA7_GPU_OPP; 589 /* DRA71x supports only OPP_NOM for GPU */ 590 if (board_is_dra71x_evm()) 591 opp = OPP_NOM; 592 break; 593 case VOLT_EVE: 594 opp = DRA7_DSPEVE_OPP; 595 /* 596 * DRA71x does not support OPP_OD for EVE. 597 * If OPP_OD is selected by menuconfig, fallback 598 * to OPP_NOM. 599 */ 600 if (board_is_dra71x_evm() && opp == OPP_OD) 601 opp = OPP_NOM; 602 break; 603 case VOLT_IVA: 604 opp = DRA7_IVA_OPP; 605 /* 606 * DRA71x does not support OPP_OD for IVA. 607 * If OPP_OD is selected by menuconfig, fallback 608 * to OPP_NOM. 609 */ 610 if (board_is_dra71x_evm() && opp == OPP_OD) 611 opp = OPP_NOM; 612 break; 613 default: 614 opp = OPP_NOM; 615 } 616 617 return opp; 618 } 619 620 /** 621 * @brief board_init 622 * 623 * @return 0 624 */ 625 int board_init(void) 626 { 627 gpmc_init(); 628 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 629 630 return 0; 631 } 632 633 int dram_init_banksize(void) 634 { 635 u64 ram_size; 636 637 ram_size = board_ti_get_emif_size(); 638 639 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 640 gd->bd->bi_dram[0].size = get_effective_memsize(); 641 if (ram_size > CONFIG_MAX_MEM_MAPPED) { 642 gd->bd->bi_dram[1].start = 0x200000000; 643 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; 644 } 645 646 return 0; 647 } 648 649 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) 650 static int device_okay(const char *path) 651 { 652 int node; 653 654 node = fdt_path_offset(gd->fdt_blob, path); 655 if (node < 0) 656 return 0; 657 658 return fdtdec_get_is_enabled(gd->fdt_blob, node); 659 } 660 #endif 661 662 int board_late_init(void) 663 { 664 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 665 char *name = "unknown"; 666 667 if (is_dra72x()) { 668 if (board_is_dra72x_revc_or_later()) 669 name = "dra72x-revc"; 670 else if (board_is_dra71x_evm()) 671 name = "dra71x"; 672 else 673 name = "dra72x"; 674 } else if (is_dra76x_abz()) { 675 name = "dra76x_abz"; 676 } else if (is_dra76x_acd()) { 677 name = "dra76x_acd"; 678 } else { 679 name = "dra7xx"; 680 } 681 682 set_board_info_env(name); 683 684 /* 685 * Default FIT boot on HS devices. Non FIT images are not allowed 686 * on HS devices. 687 */ 688 if (get_device_type() == HS_DEVICE) 689 env_set("boot_fit", "1"); 690 691 omap_die_id_serial(); 692 omap_set_fastboot_vars(); 693 694 /* 695 * Hook the LDO1 regulator to EN pin. This applies only to LP8733 696 * Rest all regulators are hooked to EN Pin at reset. 697 */ 698 if (board_is_dra71x_evm()) 699 palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7); 700 #endif 701 #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL) 702 if (device_okay("/ocp/omap_dwc3_1@48880000")) 703 enable_usb_clocks(0); 704 if (device_okay("/ocp/omap_dwc3_2@488c0000")) 705 enable_usb_clocks(1); 706 #endif 707 return 0; 708 } 709 710 #ifdef CONFIG_SPL_BUILD 711 void do_board_detect(void) 712 { 713 int rc; 714 715 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, 716 CONFIG_EEPROM_CHIP_ADDRESS); 717 if (rc) 718 printf("ti_i2c_eeprom_init failed %d\n", rc); 719 } 720 721 #else 722 723 void do_board_detect(void) 724 { 725 char *bname = NULL; 726 int rc; 727 728 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, 729 CONFIG_EEPROM_CHIP_ADDRESS); 730 if (rc) 731 printf("ti_i2c_eeprom_init failed %d\n", rc); 732 733 if (board_is_dra74x_evm()) { 734 bname = "DRA74x EVM"; 735 } else if (board_is_dra72x_evm()) { 736 bname = "DRA72x EVM"; 737 } else if (board_is_dra71x_evm()) { 738 bname = "DRA71x EVM"; 739 } else if (board_is_dra76x_evm()) { 740 bname = "DRA76x EVM"; 741 } else { 742 /* If EEPROM is not populated */ 743 if (is_dra72x()) 744 bname = "DRA72x EVM"; 745 else 746 bname = "DRA74x EVM"; 747 } 748 749 if (bname) 750 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 751 "Board: %s REV %s\n", bname, board_ti_get_rev()); 752 } 753 #endif /* CONFIG_SPL_BUILD */ 754 755 void vcores_init(void) 756 { 757 if (board_is_dra74x_evm()) { 758 *omap_vcores = &dra752_volts; 759 } else if (board_is_dra72x_evm()) { 760 *omap_vcores = &dra722_volts; 761 } else if (board_is_dra71x_evm()) { 762 *omap_vcores = &dra718_volts; 763 } else if (board_is_dra76x_evm()) { 764 *omap_vcores = &dra76x_volts; 765 } else { 766 /* If EEPROM is not populated */ 767 if (is_dra72x()) 768 *omap_vcores = &dra722_volts; 769 else 770 *omap_vcores = &dra752_volts; 771 } 772 } 773 774 void set_muxconf_regs(void) 775 { 776 do_set_mux32((*ctrl)->control_padconf_core_base, 777 early_padconf, ARRAY_SIZE(early_padconf)); 778 } 779 780 #ifdef CONFIG_IODELAY_RECALIBRATION 781 void recalibrate_iodelay(void) 782 { 783 struct pad_conf_entry const *pads, *delta_pads = NULL; 784 struct iodelay_cfg_entry const *iodelay; 785 int npads, niodelays, delta_npads = 0; 786 int ret; 787 788 switch (omap_revision()) { 789 case DRA722_ES1_0: 790 case DRA722_ES2_0: 791 case DRA722_ES2_1: 792 pads = dra72x_core_padconf_array_common; 793 npads = ARRAY_SIZE(dra72x_core_padconf_array_common); 794 if (board_is_dra71x_evm()) { 795 pads = dra71x_core_padconf_array; 796 npads = ARRAY_SIZE(dra71x_core_padconf_array); 797 iodelay = dra71_iodelay_cfg_array; 798 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array); 799 } else if (board_is_dra72x_revc_or_later()) { 800 delta_pads = dra72x_rgmii_padconf_array_revc; 801 delta_npads = 802 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); 803 iodelay = dra72_iodelay_cfg_array_revc; 804 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); 805 } else { 806 delta_pads = dra72x_rgmii_padconf_array_revb; 807 delta_npads = 808 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); 809 iodelay = dra72_iodelay_cfg_array_revb; 810 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); 811 } 812 break; 813 case DRA752_ES1_0: 814 case DRA752_ES1_1: 815 pads = dra74x_core_padconf_array; 816 npads = ARRAY_SIZE(dra74x_core_padconf_array); 817 iodelay = dra742_es1_1_iodelay_cfg_array; 818 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); 819 break; 820 case DRA762_ACD_ES1_0: 821 case DRA762_ES1_0: 822 pads = dra76x_core_padconf_array; 823 npads = ARRAY_SIZE(dra76x_core_padconf_array); 824 iodelay = dra76x_es1_0_iodelay_cfg_array; 825 niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array); 826 break; 827 default: 828 case DRA752_ES2_0: 829 case DRA762_ABZ_ES1_0: 830 pads = dra74x_core_padconf_array; 831 npads = ARRAY_SIZE(dra74x_core_padconf_array); 832 iodelay = dra742_es2_0_iodelay_cfg_array; 833 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); 834 /* Setup port1 and port2 for rgmii with 'no-id' mode */ 835 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | 836 RGMII1_ID_MODE_N_MASK); 837 break; 838 } 839 /* Setup I/O isolation */ 840 ret = __recalibrate_iodelay_start(); 841 if (ret) 842 goto err; 843 844 /* Do the muxing here */ 845 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); 846 847 /* Now do the weird minor deltas that should be safe */ 848 if (delta_npads) 849 do_set_mux32((*ctrl)->control_padconf_core_base, 850 delta_pads, delta_npads); 851 852 if (is_dra76x()) 853 /* Set mux for MCAN instead of DCAN1 */ 854 clrsetbits_le32((*ctrl)->control_core_control_spare_rw, 855 MCAN_SEL_ALT_MASK, MCAN_SEL); 856 857 /* Setup IOdelay configuration */ 858 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); 859 err: 860 /* Closeup.. remove isolation */ 861 __recalibrate_iodelay_end(ret); 862 } 863 #endif 864 865 #if defined(CONFIG_MMC) 866 int board_mmc_init(bd_t *bis) 867 { 868 omap_mmc_init(0, 0, 0, -1, -1); 869 omap_mmc_init(1, 0, 0, -1, -1); 870 return 0; 871 } 872 873 void board_mmc_poweron_ldo(uint voltage) 874 { 875 if (board_is_dra71x_evm()) { 876 if (voltage == LDO_VOLT_3V0) 877 voltage = 0x19; 878 else if (voltage == LDO_VOLT_1V8) 879 voltage = 0xa; 880 lp873x_mmc1_poweron_ldo(voltage); 881 } else if (board_is_dra76x_evm()) { 882 palmas_mmc1_poweron_ldo(LDO4_VOLTAGE, LDO4_CTRL, voltage); 883 } else { 884 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); 885 } 886 } 887 888 static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = { 889 .hw_rev = "rev11", 890 .unsupported_caps = MMC_CAP(MMC_HS_200) | 891 MMC_CAP(UHS_SDR104), 892 .max_freq = 96000000, 893 }; 894 895 static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = { 896 .hw_rev = "rev11", 897 .unsupported_caps = MMC_CAP(MMC_HS_200) | 898 MMC_CAP(UHS_SDR104) | 899 MMC_CAP(UHS_SDR50), 900 .max_freq = 48000000, 901 }; 902 903 const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) 904 { 905 switch (omap_revision()) { 906 case DRA752_ES1_0: 907 case DRA752_ES1_1: 908 if (addr == OMAP_HSMMC1_BASE) 909 return &dra7x_es1_1_mmc1_fixups; 910 else 911 return &dra7x_es1_1_mmc23_fixups; 912 default: 913 return NULL; 914 } 915 } 916 #endif 917 918 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 919 int spl_start_uboot(void) 920 { 921 /* break into full u-boot on 'c' */ 922 if (serial_tstc() && serial_getc() == 'c') 923 return 1; 924 925 #ifdef CONFIG_SPL_ENV_SUPPORT 926 env_init(); 927 env_load(); 928 if (env_get_yesno("boot_os") != 1) 929 return 1; 930 #endif 931 932 return 0; 933 } 934 #endif 935 936 #ifdef CONFIG_DRIVER_TI_CPSW 937 extern u32 *const omap_si_rev; 938 939 static void cpsw_control(int enabled) 940 { 941 /* VTP can be added here */ 942 943 return; 944 } 945 946 static struct cpsw_slave_data cpsw_slaves[] = { 947 { 948 .slave_reg_ofs = 0x208, 949 .sliver_reg_ofs = 0xd80, 950 .phy_addr = 2, 951 }, 952 { 953 .slave_reg_ofs = 0x308, 954 .sliver_reg_ofs = 0xdc0, 955 .phy_addr = 3, 956 }, 957 }; 958 959 static struct cpsw_platform_data cpsw_data = { 960 .mdio_base = CPSW_MDIO_BASE, 961 .cpsw_base = CPSW_BASE, 962 .mdio_div = 0xff, 963 .channels = 8, 964 .cpdma_reg_ofs = 0x800, 965 .slaves = 2, 966 .slave_data = cpsw_slaves, 967 .ale_reg_ofs = 0xd00, 968 .ale_entries = 1024, 969 .host_port_reg_ofs = 0x108, 970 .hw_stats_reg_ofs = 0x900, 971 .bd_ram_ofs = 0x2000, 972 .mac_control = (1 << 5), 973 .control = cpsw_control, 974 .host_port_num = 0, 975 .version = CPSW_CTRL_VERSION_2, 976 }; 977 978 int board_eth_init(bd_t *bis) 979 { 980 int ret; 981 uint8_t mac_addr[6]; 982 uint32_t mac_hi, mac_lo; 983 uint32_t ctrl_val; 984 985 /* try reading mac address from efuse */ 986 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 987 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 988 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 989 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 990 mac_addr[2] = mac_hi & 0xFF; 991 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 992 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 993 mac_addr[5] = mac_lo & 0xFF; 994 995 if (!env_get("ethaddr")) { 996 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 997 998 if (is_valid_ethaddr(mac_addr)) 999 eth_env_set_enetaddr("ethaddr", mac_addr); 1000 } 1001 1002 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 1003 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 1004 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 1005 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 1006 mac_addr[2] = mac_hi & 0xFF; 1007 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 1008 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 1009 mac_addr[5] = mac_lo & 0xFF; 1010 1011 if (!env_get("eth1addr")) { 1012 if (is_valid_ethaddr(mac_addr)) 1013 eth_env_set_enetaddr("eth1addr", mac_addr); 1014 } 1015 1016 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 1017 ctrl_val |= 0x22; 1018 writel(ctrl_val, (*ctrl)->control_core_control_io1); 1019 1020 if (*omap_si_rev == DRA722_ES1_0) 1021 cpsw_data.active_slave = 1; 1022 1023 if (board_is_dra72x_revc_or_later()) { 1024 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID; 1025 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID; 1026 } 1027 1028 ret = cpsw_register(&cpsw_data); 1029 if (ret < 0) 1030 printf("Error %d registering CPSW switch\n", ret); 1031 1032 return ret; 1033 } 1034 #endif 1035 1036 #ifdef CONFIG_BOARD_EARLY_INIT_F 1037 /* VTT regulator enable */ 1038 static inline void vtt_regulator_enable(void) 1039 { 1040 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 1041 return; 1042 1043 /* Do not enable VTT for DRA722 or DRA76x */ 1044 if (is_dra72x() || is_dra76x()) 1045 return; 1046 1047 /* 1048 * EVM Rev G and later use gpio7_11 for DDR3 termination. 1049 * This is safe enough to do on older revs. 1050 */ 1051 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 1052 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 1053 } 1054 1055 int board_early_init_f(void) 1056 { 1057 vtt_regulator_enable(); 1058 return 0; 1059 } 1060 #endif 1061 1062 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 1063 int ft_board_setup(void *blob, bd_t *bd) 1064 { 1065 ft_cpu_setup(blob, bd); 1066 1067 return 0; 1068 } 1069 #endif 1070 1071 #ifdef CONFIG_SPL_LOAD_FIT 1072 int board_fit_config_name_match(const char *name) 1073 { 1074 if (is_dra72x()) { 1075 if (board_is_dra71x_evm()) { 1076 if (!strcmp(name, "dra71-evm")) 1077 return 0; 1078 }else if(board_is_dra72x_revc_or_later()) { 1079 if (!strcmp(name, "dra72-evm-revc")) 1080 return 0; 1081 } else if (!strcmp(name, "dra72-evm")) { 1082 return 0; 1083 } 1084 } else if (is_dra76x_acd() && !strcmp(name, "dra76-evm")) { 1085 return 0; 1086 } else if (!is_dra72x() && !is_dra76x_acd() && 1087 !strcmp(name, "dra7-evm")) { 1088 return 0; 1089 } 1090 1091 return -1; 1092 } 1093 #endif 1094 1095 #ifdef CONFIG_TI_SECURE_DEVICE 1096 void board_fit_image_post_process(void **p_image, size_t *p_size) 1097 { 1098 secure_boot_verify_image(p_image, p_size); 1099 } 1100 1101 void board_tee_image_process(ulong tee_image, size_t tee_size) 1102 { 1103 secure_tee_install((u32)tee_image); 1104 } 1105 1106 #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE) 1107 int fastboot_set_reboot_flag(void) 1108 { 1109 printf("Setting reboot to fastboot flag ...\n"); 1110 env_set("dofastboot", "1"); 1111 env_save(); 1112 return 0; 1113 } 1114 #endif 1115 1116 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 1117 #endif 1118