1 /* 2 * Copyright 2014-2015 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <asm/io.h> 9 #include <linux/errno.h> 10 #include <asm/arch/fsl_serdes.h> 11 #include <asm/arch/soc.h> 12 #include <fsl-mc/ldpaa_wriop.h> 13 14 #ifdef CONFIG_SYS_FSL_SRDS_1 15 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; 16 #endif 17 #ifdef CONFIG_SYS_FSL_SRDS_2 18 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; 19 #endif 20 21 #ifdef CONFIG_FSL_MC_ENET 22 int xfi_dpmac[XFI8 + 1]; 23 int sgmii_dpmac[SGMII16 + 1]; 24 #endif 25 26 int is_serdes_configured(enum srds_prtcl device) 27 { 28 int ret = 0; 29 30 #ifdef CONFIG_SYS_FSL_SRDS_1 31 if (!serdes1_prtcl_map[NONE]) 32 fsl_serdes_init(); 33 34 ret |= serdes1_prtcl_map[device]; 35 #endif 36 #ifdef CONFIG_SYS_FSL_SRDS_2 37 if (!serdes2_prtcl_map[NONE]) 38 fsl_serdes_init(); 39 40 ret |= serdes2_prtcl_map[device]; 41 #endif 42 43 return !!ret; 44 } 45 46 int serdes_get_first_lane(u32 sd, enum srds_prtcl device) 47 { 48 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 49 u32 cfg = gur_in32(&gur->rcwsr[28]); 50 int i; 51 52 switch (sd) { 53 #ifdef CONFIG_SYS_FSL_SRDS_1 54 case FSL_SRDS_1: 55 cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; 56 cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; 57 break; 58 #endif 59 #ifdef CONFIG_SYS_FSL_SRDS_2 60 case FSL_SRDS_2: 61 cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; 62 cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; 63 break; 64 #endif 65 default: 66 printf("invalid SerDes%d\n", sd); 67 break; 68 } 69 /* Is serdes enabled at all? */ 70 if (cfg == 0) 71 return -ENODEV; 72 73 for (i = 0; i < SRDS_MAX_LANES; i++) { 74 if (serdes_get_prtcl(sd, cfg, i) == device) 75 return i; 76 } 77 78 return -ENODEV; 79 } 80 81 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, 82 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) 83 { 84 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); 85 u32 cfg; 86 int lane; 87 88 if (serdes_prtcl_map[NONE]) 89 return; 90 91 memset(serdes_prtcl_map, 0, sizeof(u8) * SERDES_PRCTL_COUNT); 92 93 cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; 94 cfg >>= sd_prctl_shift; 95 printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); 96 97 if (!is_serdes_prtcl_valid(sd, cfg)) 98 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); 99 100 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 101 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); 102 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT)) 103 debug("Unknown SerDes lane protocol %d\n", lane_prtcl); 104 else { 105 serdes_prtcl_map[lane_prtcl] = 1; 106 #ifdef CONFIG_FSL_MC_ENET 107 switch (lane_prtcl) { 108 case QSGMII_A: 109 wriop_init_dpmac(sd, 5, (int)lane_prtcl); 110 wriop_init_dpmac(sd, 6, (int)lane_prtcl); 111 wriop_init_dpmac(sd, 7, (int)lane_prtcl); 112 wriop_init_dpmac(sd, 8, (int)lane_prtcl); 113 break; 114 case QSGMII_B: 115 wriop_init_dpmac(sd, 1, (int)lane_prtcl); 116 wriop_init_dpmac(sd, 2, (int)lane_prtcl); 117 wriop_init_dpmac(sd, 3, (int)lane_prtcl); 118 wriop_init_dpmac(sd, 4, (int)lane_prtcl); 119 break; 120 case QSGMII_C: 121 wriop_init_dpmac(sd, 13, (int)lane_prtcl); 122 wriop_init_dpmac(sd, 14, (int)lane_prtcl); 123 wriop_init_dpmac(sd, 15, (int)lane_prtcl); 124 wriop_init_dpmac(sd, 16, (int)lane_prtcl); 125 break; 126 case QSGMII_D: 127 wriop_init_dpmac(sd, 9, (int)lane_prtcl); 128 wriop_init_dpmac(sd, 10, (int)lane_prtcl); 129 wriop_init_dpmac(sd, 11, (int)lane_prtcl); 130 wriop_init_dpmac(sd, 12, (int)lane_prtcl); 131 break; 132 default: 133 if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8) 134 wriop_init_dpmac(sd, 135 xfi_dpmac[lane_prtcl], 136 (int)lane_prtcl); 137 138 if (lane_prtcl >= SGMII1 && 139 lane_prtcl <= SGMII16) 140 wriop_init_dpmac(sd, sgmii_dpmac[ 141 lane_prtcl], 142 (int)lane_prtcl); 143 break; 144 } 145 #endif 146 } 147 } 148 149 /* Set the first element to indicate serdes has been initialized */ 150 serdes_prtcl_map[NONE] = 1; 151 } 152 153 void fsl_serdes_init(void) 154 { 155 #ifdef CONFIG_FSL_MC_ENET 156 int i , j; 157 158 for (i = XFI1, j = 1; i <= XFI8; i++, j++) 159 xfi_dpmac[i] = j; 160 161 for (i = SGMII1, j = 1; i <= SGMII16; i++, j++) 162 sgmii_dpmac[i] = j; 163 #endif 164 165 #ifdef CONFIG_SYS_FSL_SRDS_1 166 serdes_init(FSL_SRDS_1, 167 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, 168 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK, 169 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT, 170 serdes1_prtcl_map); 171 #endif 172 #ifdef CONFIG_SYS_FSL_SRDS_2 173 serdes_init(FSL_SRDS_2, 174 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, 175 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK, 176 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT, 177 serdes2_prtcl_map); 178 #endif 179 } 180