1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_CYRUS 11 12 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 13 #error Must call Cyrus CONFIG with a specific CPU enabled. 14 #endif 15 16 #define CONFIG_SDCARD 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_PCIE3 19 #define CONFIG_PCIE4 20 #ifdef CONFIG_ARCH_P5020 21 #define CONFIG_SYS_FSL_RAID_ENGINE 22 #define CONFIG_SYS_DPAA_RMAN 23 #endif 24 #define CONFIG_SYS_DPAA_PME 25 26 /* 27 * Corenet DS style board configuration file 28 */ 29 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 31 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 32 #if defined(CONFIG_ARCH_P5020) 33 #define CONFIG_SYS_CLK_FREQ 133000000 34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 35 #elif defined(CONFIG_ARCH_P5040) 36 #define CONFIG_SYS_CLK_FREQ 100000000 37 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_MP /* support multiple processors */ 43 44 #define CONFIG_SYS_MMC_MAX_DEVICE 1 45 46 #ifndef CONFIG_SYS_TEXT_BASE 47 #define CONFIG_SYS_TEXT_BASE 0xeff40000 48 #endif 49 50 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 51 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 52 #define CONFIG_PCIE1 /* PCIE controller 1 */ 53 #define CONFIG_PCIE2 /* PCIE controller 2 */ 54 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 55 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 56 57 #define CONFIG_ENV_OVERWRITE 58 59 #if defined(CONFIG_SDCARD) 60 #define CONFIG_SYS_EXTRA_ENV_RELOC 61 #define CONFIG_FSL_FIXED_MMC_LOCATION 62 #define CONFIG_SYS_MMC_ENV_DEV 0 63 #define CONFIG_ENV_SIZE 0x2000 64 #define CONFIG_ENV_OFFSET (512 * 1658) 65 #endif 66 67 /* 68 * These can be toggled for performance analysis, otherwise use default. 69 */ 70 #define CONFIG_SYS_CACHE_STASHING 71 #define CONFIG_BACKSIDE_L2_CACHE 72 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 73 #define CONFIG_BTB /* toggle branch predition */ 74 #define CONFIG_DDR_ECC 75 #ifdef CONFIG_DDR_ECC 76 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 77 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 78 #endif 79 80 #define CONFIG_ENABLE_36BIT_PHYS 81 82 #ifdef CONFIG_PHYS_64BIT 83 #define CONFIG_ADDR_MAP 84 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 85 #endif 86 87 /* test POST memory test */ 88 #undef CONFIG_POST 89 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 90 #define CONFIG_SYS_MEMTEST_END 0x00400000 91 #define CONFIG_SYS_ALT_MEMTEST 92 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 93 94 /* 95 * Config the L3 Cache as L3 SRAM 96 */ 97 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 98 #ifdef CONFIG_PHYS_64BIT 99 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 100 #else 101 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 102 #endif 103 #define CONFIG_SYS_L3_SIZE (1024 << 10) 104 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 105 106 #ifdef CONFIG_PHYS_64BIT 107 #define CONFIG_SYS_DCSRBAR 0xf0000000 108 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 109 #endif 110 111 /* 112 * DDR Setup 113 */ 114 #define CONFIG_VERY_BIG_RAM 115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 117 118 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 119 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 120 121 #define CONFIG_DDR_SPD 122 123 #define CONFIG_SYS_SPD_BUS_NUM 1 124 #define SPD_EEPROM_ADDRESS1 0x51 125 #define SPD_EEPROM_ADDRESS2 0x52 126 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 127 128 /* 129 * Local Bus Definitions 130 */ 131 132 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 133 #ifdef CONFIG_PHYS_64BIT 134 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 135 #else 136 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 137 #endif 138 139 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 142 #else 143 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 144 #endif 145 146 /* Set the local bus clock 1/16 of platform clock */ 147 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 148 149 #define CONFIG_SYS_BR0_PRELIM \ 150 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 151 #define CONFIG_SYS_BR1_PRELIM \ 152 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 153 154 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 155 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 156 157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 158 159 #if defined(CONFIG_RAMBOOT_PBL) 160 #define CONFIG_SYS_RAMBOOT 161 #endif 162 163 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 164 #define CONFIG_MISC_INIT_R 165 166 #define CONFIG_HWCONFIG 167 168 /* define to use L1 as initial stack */ 169 #define CONFIG_L1_INIT_RAM 170 #define CONFIG_SYS_INIT_RAM_LOCK 171 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 172 #ifdef CONFIG_PHYS_64BIT 173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 174 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 175 /* The assembler doesn't like typecast */ 176 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 177 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 178 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 179 #else 180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 183 #endif 184 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 185 186 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 187 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 188 189 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 190 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 191 192 /* Serial Port - controlled on board with jumper J8 193 * open - index 2 194 * shorted - index 1 195 */ 196 #define CONFIG_CONS_INDEX 1 197 #define CONFIG_SYS_NS16550_SERIAL 198 #define CONFIG_SYS_NS16550_REG_SIZE 1 199 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 200 201 #define CONFIG_SYS_BAUDRATE_TABLE \ 202 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 203 204 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 205 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 206 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 207 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 208 209 /* I2C */ 210 #define CONFIG_SYS_I2C 211 #define CONFIG_SYS_I2C_FSL 212 #define CONFIG_I2C_MULTI_BUS 213 #define CONFIG_I2C_CMD_TREE 214 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 215 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 216 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 217 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 218 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 219 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 220 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 221 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 222 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 223 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 224 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 225 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 226 227 #define CONFIG_ID_EEPROM 228 #define CONFIG_SYS_I2C_EEPROM_NXID 229 #define CONFIG_SYS_EEPROM_BUS_NUM 0 230 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 231 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 232 233 #define CONFIG_SYS_I2C_GENERIC_MAC 234 #define CONFIG_SYS_I2C_MAC1_BUS 3 235 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 236 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 237 #define CONFIG_SYS_I2C_MAC2_BUS 0 238 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 239 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 240 241 #define CONFIG_RTC_MCP79411 1 242 #define CONFIG_SYS_RTC_BUS_NUM 3 243 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 244 245 /* 246 * eSPI - Enhanced SPI 247 */ 248 249 /* 250 * General PCI 251 * Memory space is mapped 1-1, but I/O space must start from 0. 252 */ 253 254 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 255 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 256 #ifdef CONFIG_PHYS_64BIT 257 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 258 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 259 #else 260 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 261 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 262 #endif 263 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 264 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 265 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 266 #ifdef CONFIG_PHYS_64BIT 267 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 268 #else 269 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 270 #endif 271 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 272 273 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 274 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 275 #ifdef CONFIG_PHYS_64BIT 276 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 277 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 278 #else 279 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 280 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 281 #endif 282 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 283 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 284 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 287 #else 288 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 289 #endif 290 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 291 292 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 293 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 294 #ifdef CONFIG_PHYS_64BIT 295 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 296 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 297 #else 298 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 299 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 300 #endif 301 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 302 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 303 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 304 #ifdef CONFIG_PHYS_64BIT 305 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 306 #else 307 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 308 #endif 309 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 310 311 /* controller 4, Base address 203000 */ 312 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 313 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 314 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 315 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 316 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 317 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 318 319 /* Qman/Bman */ 320 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 321 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 322 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 323 #ifdef CONFIG_PHYS_64BIT 324 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 325 #else 326 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 327 #endif 328 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 329 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 330 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 331 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 332 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 333 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 334 CONFIG_SYS_BMAN_CENA_SIZE) 335 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 336 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 337 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 338 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 339 #ifdef CONFIG_PHYS_64BIT 340 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 341 #else 342 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 343 #endif 344 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 345 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 346 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 347 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 348 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 349 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 350 CONFIG_SYS_QMAN_CENA_SIZE) 351 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 352 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 353 354 #define CONFIG_SYS_DPAA_FMAN 355 /* Default address of microcode for the Linux Fman driver */ 356 /* 357 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 358 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 359 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 360 */ 361 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 362 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 363 364 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 365 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 366 367 #ifdef CONFIG_SYS_DPAA_FMAN 368 #define CONFIG_FMAN_ENET 369 #endif 370 371 #ifdef CONFIG_PCI 372 #define CONFIG_PCI_INDIRECT_BRIDGE 373 374 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 375 #endif /* CONFIG_PCI */ 376 377 /* SATA */ 378 #ifdef CONFIG_FSL_SATA_V2 379 #define CONFIG_LIBATA 380 #define CONFIG_FSL_SATA 381 382 #define CONFIG_SYS_SATA_MAX_DEVICE 2 383 #define CONFIG_SATA1 384 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 385 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 386 #define CONFIG_SATA2 387 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 388 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 389 390 #define CONFIG_LBA48 391 #endif 392 393 #ifdef CONFIG_FMAN_ENET 394 #define CONFIG_SYS_TBIPA_VALUE 8 395 #define CONFIG_MII /* MII PHY management */ 396 #define CONFIG_ETHPRIME "FM1@DTSEC4" 397 #endif 398 399 /* 400 * Environment 401 */ 402 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 403 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 404 405 /* 406 * USB 407 */ 408 #define CONFIG_HAS_FSL_DR_USB 409 #define CONFIG_HAS_FSL_MPH_USB 410 411 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 412 #define CONFIG_USB_EHCI_FSL 413 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 414 #define CONFIG_EHCI_IS_TDI 415 /* _VIA_CONTROL_EP */ 416 #endif 417 418 #ifdef CONFIG_MMC 419 #define CONFIG_FSL_ESDHC 420 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 421 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 422 #endif 423 424 /* 425 * Miscellaneous configurable options 426 */ 427 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 428 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 429 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 430 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 431 432 /* 433 * For booting Linux, the board info and command line data 434 * have to be in the first 64 MB of memory, since this is 435 * the maximum mapped by the Linux kernel during initialization. 436 */ 437 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 438 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 439 440 #ifdef CONFIG_CMD_KGDB 441 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 442 #endif 443 444 /* 445 * Environment Configuration 446 */ 447 #define CONFIG_ROOTPATH "/opt/nfsroot" 448 #define CONFIG_BOOTFILE "uImage" 449 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 450 451 /* default location for tftp and bootm */ 452 #define CONFIG_LOADADDR 1000000 453 454 #define __USB_PHY_TYPE utmi 455 456 #define CONFIG_EXTRA_ENV_SETTINGS \ 457 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 458 "bank_intlv=cs0_cs1;" \ 459 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 460 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 461 "netdev=eth0\0" \ 462 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 463 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 464 "consoledev=ttyS0\0" \ 465 "ramdiskaddr=2000000\0" \ 466 "fdtaddr=1e00000\0" \ 467 "bdev=sda3\0" 468 469 #define CONFIG_HDBOOT \ 470 "setenv bootargs root=/dev/$bdev rw " \ 471 "console=$consoledev,$baudrate $othbootargs;" \ 472 "tftp $loadaddr $bootfile;" \ 473 "tftp $fdtaddr $fdtfile;" \ 474 "bootm $loadaddr - $fdtaddr" 475 476 #define CONFIG_NFSBOOTCOMMAND \ 477 "setenv bootargs root=/dev/nfs rw " \ 478 "nfsroot=$serverip:$rootpath " \ 479 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 480 "console=$consoledev,$baudrate $othbootargs;" \ 481 "tftp $loadaddr $bootfile;" \ 482 "tftp $fdtaddr $fdtfile;" \ 483 "bootm $loadaddr - $fdtaddr" 484 485 #define CONFIG_RAMBOOTCOMMAND \ 486 "setenv bootargs root=/dev/ram rw " \ 487 "console=$consoledev,$baudrate $othbootargs;" \ 488 "tftp $ramdiskaddr $ramdiskfile;" \ 489 "tftp $loadaddr $bootfile;" \ 490 "tftp $fdtaddr $fdtfile;" \ 491 "bootm $loadaddr $ramdiskaddr $fdtaddr" 492 493 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 494 495 #include <asm/fsl_secure_boot.h> 496 497 #ifdef CONFIG_SECURE_BOOT 498 #endif 499 500 #endif /* __CONFIG_H */ 501