1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5329EVB_H 15 #define _M5329EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 25 #undef CONFIG_WATCHDOG 26 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 27 28 #ifdef CONFIG_NANDFLASH_SIZE 29 # define CONFIG_CMD_NAND 30 #endif 31 32 #define CONFIG_SYS_UNIFY_CACHE 33 34 #define CONFIG_MCFFEC 35 #ifdef CONFIG_MCFFEC 36 # define CONFIG_MII 1 37 # define CONFIG_MII_INIT 1 38 # define CONFIG_SYS_DISCOVER_PHY 39 # define CONFIG_SYS_RX_ETH_BUFFER 8 40 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 41 42 # define CONFIG_SYS_FEC0_PINMUX 0 43 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 44 # define MCFFEC_TOUT_LOOP 50000 45 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 46 # ifndef CONFIG_SYS_DISCOVER_PHY 47 # define FECDUPLEX FULL 48 # define FECSPEED _100BASET 49 # else 50 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 52 # endif 53 # endif /* CONFIG_SYS_DISCOVER_PHY */ 54 #endif 55 56 #define CONFIG_MCFRTC 57 #undef RTC_DEBUG 58 59 /* Timer */ 60 #define CONFIG_MCFTMR 61 #undef CONFIG_MCFPIT 62 63 /* I2C */ 64 #define CONFIG_SYS_I2C 65 #define CONFIG_SYS_I2C_FSL 66 #define CONFIG_SYS_FSL_I2C_SPEED 80000 67 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 68 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 69 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 70 71 #define CONFIG_UDP_CHECKSUM 72 73 #ifdef CONFIG_MCFFEC 74 # define CONFIG_IPADDR 192.162.1.2 75 # define CONFIG_NETMASK 255.255.255.0 76 # define CONFIG_SERVERIP 192.162.1.1 77 # define CONFIG_GATEWAYIP 192.162.1.1 78 #endif /* FEC_ENET */ 79 80 #define CONFIG_HOSTNAME M5329EVB 81 #define CONFIG_EXTRA_ENV_SETTINGS \ 82 "netdev=eth0\0" \ 83 "loadaddr=40010000\0" \ 84 "u-boot=u-boot.bin\0" \ 85 "load=tftp ${loadaddr) ${u-boot}\0" \ 86 "upd=run load; run prog\0" \ 87 "prog=prot off 0 3ffff;" \ 88 "era 0 3ffff;" \ 89 "cp.b ${loadaddr} 0 ${filesize};" \ 90 "save\0" \ 91 "" 92 93 #define CONFIG_PRAM 512 /* 512 KB */ 94 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 95 96 #ifdef CONFIG_CMD_KGDB 97 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 98 #else 99 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 100 #endif 101 102 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 103 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 104 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 105 #define CONFIG_SYS_LOAD_ADDR 0x40010000 106 107 #define CONFIG_SYS_CLK 80000000 108 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 109 110 #define CONFIG_SYS_MBAR 0xFC000000 111 112 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 113 114 /* 115 * Low Level Configuration Settings 116 * (address mappings, register initial values, etc.) 117 * You should know what you are doing if you make changes here. 118 */ 119 /*----------------------------------------------------------------------- 120 * Definitions for initial stack pointer and data area (in DPRAM) 121 */ 122 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 123 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 124 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 125 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 126 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 127 128 /*----------------------------------------------------------------------- 129 * Start addresses for the final memory configuration 130 * (Set up by the startup code) 131 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 132 */ 133 #define CONFIG_SYS_SDRAM_BASE 0x40000000 134 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 135 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 136 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 137 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 138 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 139 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 140 141 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 142 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 143 144 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 145 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 146 147 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 148 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 149 150 /* 151 * For booting Linux, the board info and command line data 152 * have to be in the first 8 MB of memory, since this is 153 * the maximum mapped by the Linux kernel during initialization ?? 154 */ 155 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 156 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 157 158 /*----------------------------------------------------------------------- 159 * FLASH organization 160 */ 161 #define CONFIG_SYS_FLASH_CFI 162 #ifdef CONFIG_SYS_FLASH_CFI 163 # define CONFIG_FLASH_CFI_DRIVER 1 164 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 165 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 166 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 167 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 168 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 169 #endif 170 171 #ifdef CONFIG_NANDFLASH_SIZE 172 # define CONFIG_SYS_MAX_NAND_DEVICE 1 173 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 174 # define CONFIG_SYS_NAND_SIZE 1 175 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 176 # define NAND_ALLOW_ERASE_ALL 1 177 # define CONFIG_JFFS2_NAND 1 178 # define CONFIG_JFFS2_DEV "nand0" 179 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 180 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 181 #endif 182 183 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 184 185 /* Configuration for environment 186 * Environment is embedded in u-boot in the second sector of the flash 187 */ 188 #define CONFIG_ENV_OFFSET 0x4000 189 #define CONFIG_ENV_SECT_SIZE 0x2000 190 #define CONFIG_ENV_IS_IN_FLASH 1 191 192 #define LDS_BOARD_TEXT \ 193 . = DEFINED(env_offset) ? env_offset : .; \ 194 common/env_embedded.o (.text*); 195 196 /*----------------------------------------------------------------------- 197 * Cache Configuration 198 */ 199 #define CONFIG_SYS_CACHELINE_SIZE 16 200 201 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 202 CONFIG_SYS_INIT_RAM_SIZE - 8) 203 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 204 CONFIG_SYS_INIT_RAM_SIZE - 4) 205 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 206 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 207 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 208 CF_ACR_EN | CF_ACR_SM_ALL) 209 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 210 CF_CACR_DCM_P) 211 212 /*----------------------------------------------------------------------- 213 * Chipselect bank definitions 214 */ 215 /* 216 * CS0 - NOR Flash 1, 2, 4, or 8MB 217 * CS1 - CompactFlash and registers 218 * CS2 - NAND Flash 16, 32, or 64MB 219 * CS3 - Available 220 * CS4 - Available 221 * CS5 - Available 222 */ 223 #define CONFIG_SYS_CS0_BASE 0 224 #define CONFIG_SYS_CS0_MASK 0x007f0001 225 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 226 227 #define CONFIG_SYS_CS1_BASE 0x10000000 228 #define CONFIG_SYS_CS1_MASK 0x001f0001 229 #define CONFIG_SYS_CS1_CTRL 0x002A3780 230 231 #ifdef CONFIG_NANDFLASH_SIZE 232 #define CONFIG_SYS_CS2_BASE 0x20000000 233 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 234 #define CONFIG_SYS_CS2_CTRL 0x00001f60 235 #endif 236 237 #endif /* _M5329EVB_H */ 238