1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * (C) Copyright 2010 5 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 /* 10 * ve8313 board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 20 #define CONFIG_MPC831x 1 21 #define CONFIG_MPC8313 1 22 #define CONFIG_VE8313 1 23 24 #ifndef CONFIG_SYS_TEXT_BASE 25 #define CONFIG_SYS_TEXT_BASE 0xfe000000 26 #endif 27 28 #define CONFIG_PCI_INDIRECT_BRIDGE 1 29 #define CONFIG_FSL_ELBC 1 30 31 /* 32 * On-board devices 33 * 34 */ 35 #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ 36 37 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 38 39 #define CONFIG_SYS_IMMR 0xE0000000 40 41 #define CONFIG_SYS_MEMTEST_START 0x00001000 42 #define CONFIG_SYS_MEMTEST_END 0x07000000 43 44 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ 45 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ 46 47 /* 48 * Device configurations 49 */ 50 51 /* 52 * DDR Setup 53 */ 54 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 56 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 57 58 /* 59 * Manually set up DDR parameters, as this board does not 60 * have the SPD connected to I2C. 61 */ 62 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 63 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 64 | CSCONFIG_AP \ 65 | CSCONFIG_ODT_RD_NEVER \ 66 | CSCONFIG_ODT_WR_ALL \ 67 | CSCONFIG_ROW_BIT_13 \ 68 | CSCONFIG_COL_BIT_10) 69 /* 0x80840102 */ 70 71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 73 | (0 << TIMING_CFG0_WRT_SHIFT) \ 74 | (3 << TIMING_CFG0_RRT_SHIFT) \ 75 | (2 << TIMING_CFG0_WWT_SHIFT) \ 76 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 77 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 78 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 79 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 80 /* 0x0e720802 */ 81 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 82 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 83 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 84 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 85 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 86 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 87 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 88 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 89 /* 0x26256222 */ 90 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 91 | (5 << TIMING_CFG2_CPO_SHIFT) \ 92 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 93 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 94 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 95 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 96 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 97 /* 0x029028c7 */ 98 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ 99 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 100 /* 0x03202000 */ 101 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 102 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 103 | SDRAM_CFG_DBW_32) 104 /* 0x43080000 */ 105 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 106 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 107 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 108 /* 0x44400232 */ 109 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 110 111 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 112 /*0x02000000*/ 113 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 114 | DDRCDR_PZ_NOMZ \ 115 | DDRCDR_NZ_NOMZ \ 116 | DDRCDR_M_ODR) 117 /* 0x73000002 */ 118 119 /* 120 * FLASH on the Local Bus 121 */ 122 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 123 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 124 #define CONFIG_SYS_FLASH_BASE 0xFE000000 125 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 126 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 128 129 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 130 | BR_PS_16 /* 16 bit */ \ 131 | BR_MS_GPCM /* MSEL = GPCM */ \ 132 | BR_V) /* valid */ 133 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 134 | OR_GPCM_CSNT \ 135 | OR_GPCM_ACS_DIV4 \ 136 | OR_GPCM_SCY_5 \ 137 | OR_GPCM_TRLX_SET \ 138 | OR_GPCM_EAD) 139 /* 0xfe000c55 */ 140 141 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 142 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 143 144 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 145 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 146 147 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 148 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 149 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 151 152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 153 #define CONFIG_SYS_RAMBOOT 154 #endif 155 156 #define CONFIG_SYS_INIT_RAM_LOCK 1 157 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 158 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 159 160 #define CONFIG_SYS_GBL_DATA_OFFSET \ 161 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 162 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 163 164 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 165 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 166 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 167 168 /* 169 * Local Bus LCRR and LBCR regs 170 */ 171 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 172 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 173 174 #define CONFIG_SYS_LBC_LBCR 0x00040000 175 176 #define CONFIG_SYS_LBC_MRTPR 0x20000000 177 178 /* 179 * NAND settings 180 */ 181 #define CONFIG_SYS_NAND_BASE 0x61000000 182 #define CONFIG_SYS_MAX_NAND_DEVICE 1 183 #define CONFIG_CMD_NAND 1 184 #define CONFIG_NAND_FSL_ELBC 1 185 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 186 187 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 188 | BR_PS_8 \ 189 | BR_DECC_CHK_GEN \ 190 | BR_MS_FCM \ 191 | BR_V) /* valid */ 192 /* 0x61000c21 */ 193 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 194 | OR_FCM_BCTLD \ 195 | OR_FCM_CHT \ 196 | OR_FCM_SCY_2 \ 197 | OR_FCM_RST \ 198 | OR_FCM_TRLX) 199 /* 0xffff90ac */ 200 201 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 202 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 203 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 204 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 205 206 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 207 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 208 209 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 210 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 211 212 /* CS2 NvRAM */ 213 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ 214 | BR_PS_8 \ 215 | BR_V) 216 /* 0x60000801 */ 217 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 218 | OR_GPCM_CSNT \ 219 | OR_GPCM_XACS \ 220 | OR_GPCM_SCY_3 \ 221 | OR_GPCM_TRLX_SET \ 222 | OR_GPCM_EHTR_SET \ 223 | OR_GPCM_EAD) 224 /* 0xfffe0937 */ 225 /* local bus read write buffer mapping SRAM@0x64000000 */ 226 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ 227 | BR_PS_16 \ 228 | BR_V) 229 /* 0x62001001 */ 230 231 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ 232 | OR_GPCM_CSNT \ 233 | OR_GPCM_XACS \ 234 | OR_GPCM_SCY_15 \ 235 | OR_GPCM_TRLX_SET \ 236 | OR_GPCM_EHTR_SET \ 237 | OR_GPCM_EAD) 238 /* 0xfe0009f7 */ 239 240 /* 241 * Serial Port 242 */ 243 #define CONFIG_CONS_INDEX 1 244 #define CONFIG_SYS_NS16550_SERIAL 245 #define CONFIG_SYS_NS16550_REG_SIZE 1 246 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 247 248 #define CONFIG_SYS_BAUDRATE_TABLE \ 249 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 250 251 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 252 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 253 254 #if defined(CONFIG_PCI) 255 /* 256 * General PCI 257 * Addresses are mapped 1-1. 258 */ 259 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 260 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 261 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 262 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 263 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 264 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 265 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 266 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 267 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 268 269 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 270 #endif 271 272 /* 273 * TSEC 274 */ 275 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 276 277 #define CONFIG_TSEC1 278 #ifdef CONFIG_TSEC1 279 #define CONFIG_HAS_ETH0 280 #define CONFIG_TSEC1_NAME "TSEC1" 281 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 282 #define TSEC1_PHY_ADDR 0x01 283 #define TSEC1_FLAGS 0 284 #define TSEC1_PHYIDX 0 285 #endif 286 287 /* Options are: TSEC[0-1] */ 288 #define CONFIG_ETHPRIME "TSEC1" 289 290 /* 291 * Environment 292 */ 293 #define CONFIG_ENV_ADDR \ 294 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 295 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 296 #define CONFIG_ENV_SIZE 0x4000 297 /* Address and size of Redundant Environment Sector */ 298 #define CONFIG_ENV_OFFSET_REDUND \ 299 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 300 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 301 302 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 303 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 304 305 /* 306 * BOOTP options 307 */ 308 #define CONFIG_BOOTP_BOOTFILESIZE 309 #define CONFIG_BOOTP_BOOTPATH 310 #define CONFIG_BOOTP_GATEWAY 311 #define CONFIG_BOOTP_HOSTNAME 312 313 /* 314 * Command line configuration. 315 */ 316 #define CONFIG_CMD_PCI 317 318 #define CONFIG_CMDLINE_EDITING 1 319 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 320 321 /* 322 * Miscellaneous configurable options 323 */ 324 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 325 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 326 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 327 328 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 329 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 330 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 331 332 /* 333 * For booting Linux, the board info and command line data 334 * have to be in the first 256 MB of memory, since this is 335 * the maximum mapped by the Linux kernel during initialization. 336 */ 337 /* Initial Memory map for Linux*/ 338 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 339 340 /* 0x64050000 */ 341 #define CONFIG_SYS_HRCW_LOW (\ 342 0x20000000 /* reserved, must be set */ |\ 343 HRCWL_DDRCM |\ 344 HRCWL_CSB_TO_CLKIN_4X1 | \ 345 HRCWL_CORE_TO_CSB_2_5X1) 346 347 /* 0xa0600004 */ 348 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ 349 HRCWH_PCI_ARBITER_ENABLE | \ 350 HRCWH_CORE_ENABLE | \ 351 HRCWH_FROM_0X00000100 | \ 352 HRCWH_BOOTSEQ_DISABLE |\ 353 HRCWH_SW_WATCHDOG_DISABLE |\ 354 HRCWH_ROM_LOC_LOCAL_16BIT | \ 355 HRCWH_TSEC1M_IN_MII | \ 356 HRCWH_BIG_ENDIAN | \ 357 HRCWH_LALE_EARLY) 358 359 /* System IO Config */ 360 #define CONFIG_SYS_SICRH (0x01000000 | \ 361 SICRH_ETSEC2_B | \ 362 SICRH_ETSEC2_C | \ 363 SICRH_ETSEC2_D | \ 364 SICRH_ETSEC2_E | \ 365 SICRH_ETSEC2_F | \ 366 SICRH_ETSEC2_G | \ 367 SICRH_TSOBI1 | \ 368 SICRH_TSOBI2) 369 /* 0x010fff03 */ 370 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 371 SICRL_SPI_A | \ 372 SICRL_SPI_B | \ 373 SICRL_SPI_C | \ 374 SICRL_SPI_D | \ 375 SICRL_ETSEC2_A) 376 /* 0x33fc0003) */ 377 378 #define CONFIG_SYS_HID0_INIT 0x000000000 379 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 380 HID0_ENABLE_INSTRUCTION_CACHE) 381 382 #define CONFIG_SYS_HID2 HID2_HBE 383 384 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 385 386 /* DDR @ 0x00000000 */ 387 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 388 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 389 | BATU_BL_256M \ 390 | BATU_VS \ 391 | BATU_VP) 392 393 #if defined(CONFIG_PCI) 394 /* PCI @ 0x80000000 */ 395 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 396 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 397 | BATU_BL_256M \ 398 | BATU_VS \ 399 | BATU_VP) 400 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 401 | BATL_PP_RW \ 402 | BATL_CACHEINHIBIT \ 403 | BATL_GUARDEDSTORAGE) 404 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 405 | BATU_BL_256M \ 406 | BATU_VS \ 407 | BATU_VP) 408 #else 409 #define CONFIG_SYS_IBAT1L (0) 410 #define CONFIG_SYS_IBAT1U (0) 411 #define CONFIG_SYS_IBAT2L (0) 412 #define CONFIG_SYS_IBAT2U (0) 413 #endif 414 415 /* PCI2 not supported on 8313 */ 416 #define CONFIG_SYS_IBAT3L (0) 417 #define CONFIG_SYS_IBAT3U (0) 418 #define CONFIG_SYS_IBAT4L (0) 419 #define CONFIG_SYS_IBAT4U (0) 420 421 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 422 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 423 | BATL_PP_RW \ 424 | BATL_CACHEINHIBIT \ 425 | BATL_GUARDEDSTORAGE) 426 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 427 | BATU_BL_256M \ 428 | BATU_VS \ 429 | BATU_VP) 430 431 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 432 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 433 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 434 435 /* FPGA, SRAM, NAND @ 0x60000000 */ 436 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 437 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) 438 439 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 440 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 441 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 442 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 443 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 444 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 445 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 446 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 447 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 448 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 449 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 450 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 451 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 452 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 453 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 454 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 455 456 #define CONFIG_NETDEV eth0 457 458 #define CONFIG_HOSTNAME ve8313 459 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 460 461 #define CONFIG_EXTRA_ENV_SETTINGS \ 462 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 463 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ 464 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 465 "u-boot_addr_r=100000\0" \ 466 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 467 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 468 " +${filesize};" \ 469 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 470 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ 471 " ${filesize};" \ 472 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 473 474 #endif /* __CONFIG_H */ 475