arm64: tegra: Use symbolic clock identifiers

Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-

arm64: tegra: Use symbolic clock identifiers

Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Use symbolic HSP identifiers

Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by

arm64: tegra: Use symbolic HSP identifiers

Now that the corresponding device tree binding include has been merged,
convert the DTS files to use symbolic names instead of numeric ones.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add GPIO controllers on Tegra186

Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an

arm64: tegra: Add GPIO controllers on Tegra186

Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add SDHCI controllers on Tegra186

Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOS

arm64: tegra: Add SDHCI controllers on Tegra186

Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add I2C controllers on Tegra186

Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads wi

arm64: tegra: Add I2C controllers on Tegra186

Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add serial ports on Tegra186

The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for U

arm64: tegra: Add serial ports on Tegra186

The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CPU nodes for Tegra186

Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.

Signed-off-by: Thierry Reding <tredi

arm64: tegra: Add CPU nodes for Tegra186

Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add Tegra186 support

This adds the initial support of Tegra186 SoC. It provides enough to
enable the serial console and boot from an initial ramdisk.

Signed-off-by: Joseph Lo <josephl

arm64: tegra: Add Tegra186 support

This adds the initial support of Tegra186 SoC. It provides enough to
enable the serial console and boot from an initial ramdisk.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
[treding@nvidia.com: remove leading 0 from unit-addresses]
[treding@nvidia.com: remove unused nvidia,bpmp property]
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Devicetree updates from Olof Johansson:
"As usual, most of the changes are to devicetrees.

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Devicetree updates from Olof Johansson:
"As usual, most of the changes are to devicetrees.

Besides smaller fixes, some refactorings and cleanups, some of the new
platforms and chips (or significant features) supported are below:

Broadcom boards:
- Cisco Meraki MR32 (BCM53016-based)
- BCM2711 (RPi4) display pipeline support

Actions Semi boards:
- Caninos Loucos Labrador SBC (S500-based)
- RoseapplePi SBC (S500-based)

Allwinner SoCs/boards:
- A100 SoC with Perf1 board
- Mali, DMA, Cetrus and IR support for R40 SoC

Amlogic boards:
- Libretch S905x CC V2 board
- Hardkernel ODROID-N2+ board

Aspeed boards/platforms:
- Wistron Mowgli (AST2500-based, Power9 OpenPower server)
- Facebook Wedge400 (AST2500-based, ToR switch)

Hisilicon SoC:
- SD5203 SoC

Nvidia boards:
- Tegra234 VDK, for pre-silicon Orin SoC

NXP i.MX boards:
- Librem 5 phone
- i.MX8MM DDR4 EVK
- Variscite VAR-SOM-MX8MN SoM
- Symphony board
- Tolino Shine 2 HD
- TQMa6 SoM
- Y Soft IOTA Orion

Rockchip boards:
- NanoPi R2S board
- A95X-Z2 board
- more Rock-Pi4 variants

STM32 boards:
- Odyssey SOM board (STM32MP157CAC-based)
- DH DRC02 board

Toshiba SoCs/boards:
- Visconti SoC and TPMV7708 board"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits)
ARM: dts: nspire: Fix SP804 users
arm64: dts: lg: Fix SP804 users
arm64: dts: lg: Fix SP805 clocks
ARM: mstar: Fix up the fallout from moving the dts/dtsi files
ARM: mstar: Add mstar prefix to all of the dtsi/dts files
ARM: mstar: Add interrupt to pm_uart
ARM: mstar: Add interrupt controller to base dtsi
ARM: dts: meson8: remove two invalid interrupt lines from the GPU node
arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
arm64: dts: ti: k3-j7200-main: Add USB controller
arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
ARM: dts: hisilicon: add SD5203 dts
ARM: dts: hisilicon: fix the system controller compatible nodes
arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
arm64: dts: zynqmp: Remove undocumented u-boot properties
arm64: dts: zynqmp: Remove additional compatible string for i2c IPs
arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml
...

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arm64: tegra: Add DT binding for AHUB components

This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a ch

arm64: tegra: Add DT binding for AHUB components

This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194.
Bindings for following modules are added.
* AHUB added as a child node under ACONNECT
* AHUB includes many HW accelerators and below components are added
as its children.
* ADMAIF
* I2S
* DMIC
* DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does
not have this module)

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes

commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")

Tegra186 uses separate SDMMC_LEGACY_TM clock for data time

arm64: tegra: Add missing timeout clock to Tegra186 SDMMC nodes

commit 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")

Tegra186 uses separate SDMMC_LEGACY_TM clock for data timeout and
this clock is not enabled currently which is not recommended.

Tegra186 SDMMC advertises 12Mhz as timeout clock frequency in host
capability register and uses it by default.

So, this clock should be kept enabled by the SDMMC driver.

Fixes: 39cb62cb8973 ("arm64: tegra: Add Tegra186 support")
Cc: stable <stable@vger.kernel.org> # 5.4
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Link: https://lore.kernel.org/r/1598548861-32373-6-git-send-email-skomatineni@nvidia.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

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arm64: tegra: Use standard names for SRAM nodes

SRAM nodes should be named sram@<unit-address> to match the bindings.

While at it, also remove the unneeded, custom compatible string

arm64: tegra: Use standard names for SRAM nodes

SRAM nodes should be named sram@<unit-address> to match the bindings.

While at it, also remove the unneeded, custom compatible string for
SRAM partition nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Do not mark display hub as simple bus

The display hub on Tegra186 and Tegra194 is not a simple bus, so drop
the corresponding compatible string.

Signed-off-by: Thi

arm64: tegra: Do not mark display hub as simple bus

The display hub on Tegra186 and Tegra194 is not a simple bus, so drop
the corresponding compatible string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix {clock,reset}-names ordering

It's very difficult to describe string lists that can be in arbitrary
order using the json-schema based validation tooling. Since the OS is

arm64: tegra: Fix {clock,reset}-names ordering

It's very difficult to describe string lists that can be in arbitrary
order using the json-schema based validation tooling. Since the OS is
not going to care either way, take the easy way out and reorder these
entries to match the order defined in the bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Remove XUSB pad controller interrupt from XUSB node

The XUSB controller doesn't need the XUSB pad controller's interrupt, so
remove it.

Signed-off-by: Thierry Redi

arm64: tegra: Remove XUSB pad controller interrupt from XUSB node

The XUSB controller doesn't need the XUSB pad controller's interrupt, so
remove it.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Do not mark host1x as simple bus

The host1x is not a simple bus, so drop the corresponding compatible
string.

Signed-off-by: Thierry Reding <treding@nvidia.com>

arm64: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
va

arm64: tegra: Use proper tuple notation

Tuple boundaries should be marked by < and > to make it clear which
cells are part of the same tuple. This also helps the json-schema based
validation tooling to properly parse this data.

While at it, also remove the "immovable" bit from PCI addresses. All of
these addresses are in fact "movable".

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Rename sdhci nodes to mmc

The new json-schema based validation tools require SD/MMC controller
nodes to be named mmc. Rename all references to them.

Signed-off-by:

arm64: tegra: Rename sdhci nodes to mmc

The new json-schema based validation tools require SD/MMC controller
nodes to be named mmc. Rename all references to them.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add interrupt-names for host1x

Interrupt names are used to distinguish between the syncpoint and
general host1x interrupts. Make sure they are available in the DT so
th

arm64: tegra: Add interrupt-names for host1x

Interrupt names are used to distinguish between the syncpoint and
general host1x interrupts. Make sure they are available in the DT so
that drivers can use them if necessary.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Describe interconnect paths on Tegra186

The interface used by clients of the memory controller can be configured
in a number of different ways. Describe this path using the

arm64: tegra: Describe interconnect paths on Tegra186

The interface used by clients of the memory controller can be configured
in a number of different ways. Describe this path using the interconnect
bindings to enable the configuration of these parameters.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Use standard notation for interrupts

It is customary to use angle brackets around each tuple in the
interrupts property.

Signed-off-by: Thierry Reding <treding@nvi

arm64: tegra: Use standard notation for interrupts

It is customary to use angle brackets around each tuple in the
interrupts property.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186

The standard mmio-sram bindings require the #address- and #size-cells
properties to be 1.

Signed-off-by: Thierr

arm64: tegra: Fix #address-cells/#size-cells for SRAM on Tegra186

The standard mmio-sram bindings require the #address- and #size-cells
properties to be 1.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add XUDC node for Tegra186

Tegra186 has one XUSB device mode controller, which can be operated in
HS and SS modes. Add DT entry for XUSB device mode controller.

Si

arm64: tegra: Add XUDC node for Tegra186

Tegra186 has one XUSB device mode controller, which can be operated in
HS and SS modes. Add DT entry for XUSB device mode controller.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Make XUSB node consistent with the rest

The ordering of properties in the XUSB node is inconsistent with the
ordering of the properties in other nodes. Resort them to make

arm64: tegra: Make XUSB node consistent with the rest

The ordering of properties in the XUSB node is inconsistent with the
ordering of the properties in other nodes. Resort them to make the node
more consistent. Also get rid of some unnecessary whitespace.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add external memory controller on Tegra186

Add the external memory controller as a child device of the memory
controller on Tegra186. The memory controller really represent

arm64: tegra: Add external memory controller on Tegra186

Add the external memory controller as a child device of the memory
controller on Tegra186. The memory controller really represents the
memory subsystem that encompasses both the memory and external memory
controllers. The external memory controller uses the BPMP to obtain the
list of supported EMC frequencies and set the EMC frequency.

Also set up the dma-ranges property to describe that all memory clients
can address up to 40 bits using the memory controller client interface
(MCCIF), unless otherwise limited by the DMA engines of the hardware.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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