1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 aconnect { 77 compatible = "nvidia,tegra186-aconnect", 78 "nvidia,tegra210-aconnect"; 79 clocks = <&bpmp TEGRA186_CLK_APE>, 80 <&bpmp TEGRA186_CLK_APB2APE>; 81 clock-names = "ape", "apb2ape"; 82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x02900000 0x0 0x02900000 0x200000>; 86 status = "disabled"; 87 88 adma: dma-controller@2930000 { 89 compatible = "nvidia,tegra186-adma"; 90 reg = <0x02930000 0x20000>; 91 interrupt-parent = <&agic>; 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 124 #dma-cells = <1>; 125 clocks = <&bpmp TEGRA186_CLK_AHUB>; 126 clock-names = "d_audio"; 127 status = "disabled"; 128 }; 129 130 agic: interrupt-controller@2a40000 { 131 compatible = "nvidia,tegra186-agic", 132 "nvidia,tegra210-agic"; 133 #interrupt-cells = <3>; 134 interrupt-controller; 135 reg = <0x02a41000 0x1000>, 136 <0x02a42000 0x2000>; 137 interrupts = <GIC_SPI 145 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA186_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 144 tegra_ahub: ahub@2900800 { 145 compatible = "nvidia,tegra186-ahub"; 146 reg = <0x02900800 0x800>; 147 clocks = <&bpmp TEGRA186_CLK_AHUB>; 148 clock-names = "ahub"; 149 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; 150 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 ranges = <0x02900800 0x02900800 0x11800>; 154 status = "disabled"; 155 156 tegra_admaif: admaif@290f000 { 157 compatible = "nvidia,tegra186-admaif"; 158 reg = <0x0290f000 0x1000>; 159 dmas = <&adma 1>, <&adma 1>, 160 <&adma 2>, <&adma 2>, 161 <&adma 3>, <&adma 3>, 162 <&adma 4>, <&adma 4>, 163 <&adma 5>, <&adma 5>, 164 <&adma 6>, <&adma 6>, 165 <&adma 7>, <&adma 7>, 166 <&adma 8>, <&adma 8>, 167 <&adma 9>, <&adma 9>, 168 <&adma 10>, <&adma 10>, 169 <&adma 11>, <&adma 11>, 170 <&adma 12>, <&adma 12>, 171 <&adma 13>, <&adma 13>, 172 <&adma 14>, <&adma 14>, 173 <&adma 15>, <&adma 15>, 174 <&adma 16>, <&adma 16>, 175 <&adma 17>, <&adma 17>, 176 <&adma 18>, <&adma 18>, 177 <&adma 19>, <&adma 19>, 178 <&adma 20>, <&adma 20>; 179 dma-names = "rx1", "tx1", 180 "rx2", "tx2", 181 "rx3", "tx3", 182 "rx4", "tx4", 183 "rx5", "tx5", 184 "rx6", "tx6", 185 "rx7", "tx7", 186 "rx8", "tx8", 187 "rx9", "tx9", 188 "rx10", "tx10", 189 "rx11", "tx11", 190 "rx12", "tx12", 191 "rx13", "tx13", 192 "rx14", "tx14", 193 "rx15", "tx15", 194 "rx16", "tx16", 195 "rx17", "tx17", 196 "rx18", "tx18", 197 "rx19", "tx19", 198 "rx20", "tx20"; 199 status = "disabled"; 200 }; 201 202 tegra_i2s1: i2s@2901000 { 203 compatible = "nvidia,tegra186-i2s", 204 "nvidia,tegra210-i2s"; 205 reg = <0x2901000 0x100>; 206 clocks = <&bpmp TEGRA186_CLK_I2S1>, 207 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; 208 clock-names = "i2s", "sync_input"; 209 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; 210 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 211 assigned-clock-rates = <1536000>; 212 sound-name-prefix = "I2S1"; 213 status = "disabled"; 214 }; 215 216 tegra_i2s2: i2s@2901100 { 217 compatible = "nvidia,tegra186-i2s", 218 "nvidia,tegra210-i2s"; 219 reg = <0x2901100 0x100>; 220 clocks = <&bpmp TEGRA186_CLK_I2S2>, 221 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; 222 clock-names = "i2s", "sync_input"; 223 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; 224 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 225 assigned-clock-rates = <1536000>; 226 sound-name-prefix = "I2S2"; 227 status = "disabled"; 228 }; 229 230 tegra_i2s3: i2s@2901200 { 231 compatible = "nvidia,tegra186-i2s", 232 "nvidia,tegra210-i2s"; 233 reg = <0x2901200 0x100>; 234 clocks = <&bpmp TEGRA186_CLK_I2S3>, 235 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; 236 clock-names = "i2s", "sync_input"; 237 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; 238 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 239 assigned-clock-rates = <1536000>; 240 sound-name-prefix = "I2S3"; 241 status = "disabled"; 242 }; 243 244 tegra_i2s4: i2s@2901300 { 245 compatible = "nvidia,tegra186-i2s", 246 "nvidia,tegra210-i2s"; 247 reg = <0x2901300 0x100>; 248 clocks = <&bpmp TEGRA186_CLK_I2S4>, 249 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; 250 clock-names = "i2s", "sync_input"; 251 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; 252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 253 assigned-clock-rates = <1536000>; 254 sound-name-prefix = "I2S4"; 255 status = "disabled"; 256 }; 257 258 tegra_i2s5: i2s@2901400 { 259 compatible = "nvidia,tegra186-i2s", 260 "nvidia,tegra210-i2s"; 261 reg = <0x2901400 0x100>; 262 clocks = <&bpmp TEGRA186_CLK_I2S5>, 263 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; 264 clock-names = "i2s", "sync_input"; 265 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; 266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 267 assigned-clock-rates = <1536000>; 268 sound-name-prefix = "I2S5"; 269 status = "disabled"; 270 }; 271 272 tegra_i2s6: i2s@2901500 { 273 compatible = "nvidia,tegra186-i2s", 274 "nvidia,tegra210-i2s"; 275 reg = <0x2901500 0x100>; 276 clocks = <&bpmp TEGRA186_CLK_I2S6>, 277 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; 278 clock-names = "i2s", "sync_input"; 279 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; 280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 281 assigned-clock-rates = <1536000>; 282 sound-name-prefix = "I2S6"; 283 status = "disabled"; 284 }; 285 286 tegra_dmic1: dmic@2904000 { 287 compatible = "nvidia,tegra210-dmic"; 288 reg = <0x2904000 0x100>; 289 clocks = <&bpmp TEGRA186_CLK_DMIC1>; 290 clock-names = "dmic"; 291 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; 292 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 293 assigned-clock-rates = <3072000>; 294 sound-name-prefix = "DMIC1"; 295 status = "disabled"; 296 }; 297 298 tegra_dmic2: dmic@2904100 { 299 compatible = "nvidia,tegra210-dmic"; 300 reg = <0x2904100 0x100>; 301 clocks = <&bpmp TEGRA186_CLK_DMIC2>; 302 clock-names = "dmic"; 303 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; 304 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 305 assigned-clock-rates = <3072000>; 306 sound-name-prefix = "DMIC2"; 307 status = "disabled"; 308 }; 309 310 tegra_dmic3: dmic@2904200 { 311 compatible = "nvidia,tegra210-dmic"; 312 reg = <0x2904200 0x100>; 313 clocks = <&bpmp TEGRA186_CLK_DMIC3>; 314 clock-names = "dmic"; 315 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; 316 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 317 assigned-clock-rates = <3072000>; 318 sound-name-prefix = "DMIC3"; 319 status = "disabled"; 320 }; 321 322 tegra_dmic4: dmic@2904300 { 323 compatible = "nvidia,tegra210-dmic"; 324 reg = <0x2904300 0x100>; 325 clocks = <&bpmp TEGRA186_CLK_DMIC4>; 326 clock-names = "dmic"; 327 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; 328 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 329 assigned-clock-rates = <3072000>; 330 sound-name-prefix = "DMIC4"; 331 status = "disabled"; 332 }; 333 334 tegra_dspk1: dspk@2905000 { 335 compatible = "nvidia,tegra186-dspk"; 336 reg = <0x2905000 0x100>; 337 clocks = <&bpmp TEGRA186_CLK_DSPK1>; 338 clock-names = "dspk"; 339 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; 340 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 341 assigned-clock-rates = <12288000>; 342 sound-name-prefix = "DSPK1"; 343 status = "disabled"; 344 }; 345 346 tegra_dspk2: dspk@2905100 { 347 compatible = "nvidia,tegra186-dspk"; 348 reg = <0x2905100 0x100>; 349 clocks = <&bpmp TEGRA186_CLK_DSPK2>; 350 clock-names = "dspk"; 351 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; 352 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; 353 assigned-clock-rates = <12288000>; 354 sound-name-prefix = "DSPK2"; 355 status = "disabled"; 356 }; 357 }; 358 }; 359 360 mc: memory-controller@2c00000 { 361 compatible = "nvidia,tegra186-mc"; 362 reg = <0x0 0x02c00000 0x0 0xb0000>; 363 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 364 status = "disabled"; 365 366 #interconnect-cells = <1>; 367 #address-cells = <2>; 368 #size-cells = <2>; 369 370 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 371 372 /* 373 * Memory clients have access to all 40 bits that the memory 374 * controller can address. 375 */ 376 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 377 378 emc: external-memory-controller@2c60000 { 379 compatible = "nvidia,tegra186-emc"; 380 reg = <0x0 0x02c60000 0x0 0x50000>; 381 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&bpmp TEGRA186_CLK_EMC>; 383 clock-names = "emc"; 384 385 #interconnect-cells = <0>; 386 387 nvidia,bpmp = <&bpmp>; 388 }; 389 }; 390 391 uarta: serial@3100000 { 392 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 393 reg = <0x0 0x03100000 0x0 0x40>; 394 reg-shift = <2>; 395 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&bpmp TEGRA186_CLK_UARTA>; 397 clock-names = "serial"; 398 resets = <&bpmp TEGRA186_RESET_UARTA>; 399 reset-names = "serial"; 400 status = "disabled"; 401 }; 402 403 uartb: serial@3110000 { 404 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 405 reg = <0x0 0x03110000 0x0 0x40>; 406 reg-shift = <2>; 407 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&bpmp TEGRA186_CLK_UARTB>; 409 clock-names = "serial"; 410 resets = <&bpmp TEGRA186_RESET_UARTB>; 411 reset-names = "serial"; 412 status = "disabled"; 413 }; 414 415 uartd: serial@3130000 { 416 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 417 reg = <0x0 0x03130000 0x0 0x40>; 418 reg-shift = <2>; 419 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&bpmp TEGRA186_CLK_UARTD>; 421 clock-names = "serial"; 422 resets = <&bpmp TEGRA186_RESET_UARTD>; 423 reset-names = "serial"; 424 status = "disabled"; 425 }; 426 427 uarte: serial@3140000 { 428 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 429 reg = <0x0 0x03140000 0x0 0x40>; 430 reg-shift = <2>; 431 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&bpmp TEGRA186_CLK_UARTE>; 433 clock-names = "serial"; 434 resets = <&bpmp TEGRA186_RESET_UARTE>; 435 reset-names = "serial"; 436 status = "disabled"; 437 }; 438 439 uartf: serial@3150000 { 440 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 441 reg = <0x0 0x03150000 0x0 0x40>; 442 reg-shift = <2>; 443 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&bpmp TEGRA186_CLK_UARTF>; 445 clock-names = "serial"; 446 resets = <&bpmp TEGRA186_RESET_UARTF>; 447 reset-names = "serial"; 448 status = "disabled"; 449 }; 450 451 gen1_i2c: i2c@3160000 { 452 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 453 reg = <0x0 0x03160000 0x0 0x10000>; 454 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clocks = <&bpmp TEGRA186_CLK_I2C1>; 458 clock-names = "div-clk"; 459 resets = <&bpmp TEGRA186_RESET_I2C1>; 460 reset-names = "i2c"; 461 status = "disabled"; 462 }; 463 464 cam_i2c: i2c@3180000 { 465 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 466 reg = <0x0 0x03180000 0x0 0x10000>; 467 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&bpmp TEGRA186_CLK_I2C3>; 471 clock-names = "div-clk"; 472 resets = <&bpmp TEGRA186_RESET_I2C3>; 473 reset-names = "i2c"; 474 status = "disabled"; 475 }; 476 477 /* shares pads with dpaux1 */ 478 dp_aux_ch1_i2c: i2c@3190000 { 479 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 480 reg = <0x0 0x03190000 0x0 0x10000>; 481 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 clocks = <&bpmp TEGRA186_CLK_I2C4>; 485 clock-names = "div-clk"; 486 resets = <&bpmp TEGRA186_RESET_I2C4>; 487 reset-names = "i2c"; 488 pinctrl-names = "default", "idle"; 489 pinctrl-0 = <&state_dpaux1_i2c>; 490 pinctrl-1 = <&state_dpaux1_off>; 491 status = "disabled"; 492 }; 493 494 /* controlled by BPMP, should not be enabled */ 495 pwr_i2c: i2c@31a0000 { 496 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 497 reg = <0x0 0x031a0000 0x0 0x10000>; 498 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&bpmp TEGRA186_CLK_I2C5>; 502 clock-names = "div-clk"; 503 resets = <&bpmp TEGRA186_RESET_I2C5>; 504 reset-names = "i2c"; 505 status = "disabled"; 506 }; 507 508 /* shares pads with dpaux0 */ 509 dp_aux_ch0_i2c: i2c@31b0000 { 510 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 511 reg = <0x0 0x031b0000 0x0 0x10000>; 512 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&bpmp TEGRA186_CLK_I2C6>; 516 clock-names = "div-clk"; 517 resets = <&bpmp TEGRA186_RESET_I2C6>; 518 reset-names = "i2c"; 519 pinctrl-names = "default", "idle"; 520 pinctrl-0 = <&state_dpaux_i2c>; 521 pinctrl-1 = <&state_dpaux_off>; 522 status = "disabled"; 523 }; 524 525 gen7_i2c: i2c@31c0000 { 526 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 527 reg = <0x0 0x031c0000 0x0 0x10000>; 528 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&bpmp TEGRA186_CLK_I2C7>; 532 clock-names = "div-clk"; 533 resets = <&bpmp TEGRA186_RESET_I2C7>; 534 reset-names = "i2c"; 535 status = "disabled"; 536 }; 537 538 gen9_i2c: i2c@31e0000 { 539 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 540 reg = <0x0 0x031e0000 0x0 0x10000>; 541 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 clocks = <&bpmp TEGRA186_CLK_I2C9>; 545 clock-names = "div-clk"; 546 resets = <&bpmp TEGRA186_RESET_I2C9>; 547 reset-names = "i2c"; 548 status = "disabled"; 549 }; 550 551 sdmmc1: mmc@3400000 { 552 compatible = "nvidia,tegra186-sdhci"; 553 reg = <0x0 0x03400000 0x0 0x10000>; 554 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 556 clock-names = "sdhci"; 557 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 558 reset-names = "sdhci"; 559 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 560 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 561 interconnect-names = "dma-mem", "write"; 562 iommus = <&smmu TEGRA186_SID_SDMMC1>; 563 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 564 pinctrl-0 = <&sdmmc1_3v3>; 565 pinctrl-1 = <&sdmmc1_1v8>; 566 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 567 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 568 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 569 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 570 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 571 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 572 nvidia,default-tap = <0x5>; 573 nvidia,default-trim = <0xb>; 574 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 575 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 576 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 577 status = "disabled"; 578 }; 579 580 sdmmc2: mmc@3420000 { 581 compatible = "nvidia,tegra186-sdhci"; 582 reg = <0x0 0x03420000 0x0 0x10000>; 583 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 585 clock-names = "sdhci"; 586 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 587 reset-names = "sdhci"; 588 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 589 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 590 interconnect-names = "dma-mem", "write"; 591 iommus = <&smmu TEGRA186_SID_SDMMC2>; 592 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 593 pinctrl-0 = <&sdmmc2_3v3>; 594 pinctrl-1 = <&sdmmc2_1v8>; 595 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 596 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 597 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 598 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 599 nvidia,default-tap = <0x5>; 600 nvidia,default-trim = <0xb>; 601 status = "disabled"; 602 }; 603 604 sdmmc3: mmc@3440000 { 605 compatible = "nvidia,tegra186-sdhci"; 606 reg = <0x0 0x03440000 0x0 0x10000>; 607 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 609 clock-names = "sdhci"; 610 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 611 reset-names = "sdhci"; 612 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 613 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 614 interconnect-names = "dma-mem", "write"; 615 iommus = <&smmu TEGRA186_SID_SDMMC3>; 616 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 617 pinctrl-0 = <&sdmmc3_3v3>; 618 pinctrl-1 = <&sdmmc3_1v8>; 619 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 620 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 621 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 622 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 623 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 624 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 625 nvidia,default-tap = <0x5>; 626 nvidia,default-trim = <0xb>; 627 status = "disabled"; 628 }; 629 630 sdmmc4: mmc@3460000 { 631 compatible = "nvidia,tegra186-sdhci"; 632 reg = <0x0 0x03460000 0x0 0x10000>; 633 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 635 clock-names = "sdhci"; 636 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 637 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 638 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 639 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 640 reset-names = "sdhci"; 641 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 642 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 643 interconnect-names = "dma-mem", "write"; 644 iommus = <&smmu TEGRA186_SID_SDMMC4>; 645 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 646 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 647 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 648 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 649 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 650 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 651 nvidia,default-tap = <0x9>; 652 nvidia,default-trim = <0x5>; 653 nvidia,dqs-trim = <63>; 654 mmc-hs400-1_8v; 655 supports-cqe; 656 status = "disabled"; 657 }; 658 659 hda@3510000 { 660 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 661 reg = <0x0 0x03510000 0x0 0x10000>; 662 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&bpmp TEGRA186_CLK_HDA>, 664 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 665 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 666 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 667 resets = <&bpmp TEGRA186_RESET_HDA>, 668 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 669 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 670 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 671 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 672 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 673 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 674 interconnect-names = "dma-mem", "write"; 675 iommus = <&smmu TEGRA186_SID_HDA>; 676 status = "disabled"; 677 }; 678 679 padctl: padctl@3520000 { 680 compatible = "nvidia,tegra186-xusb-padctl"; 681 reg = <0x0 0x03520000 0x0 0x1000>, 682 <0x0 0x03540000 0x0 0x1000>; 683 reg-names = "padctl", "ao"; 684 685 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 686 reset-names = "padctl"; 687 688 status = "disabled"; 689 690 pads { 691 usb2 { 692 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 693 clock-names = "trk"; 694 status = "disabled"; 695 696 lanes { 697 usb2-0 { 698 status = "disabled"; 699 #phy-cells = <0>; 700 }; 701 702 usb2-1 { 703 status = "disabled"; 704 #phy-cells = <0>; 705 }; 706 707 usb2-2 { 708 status = "disabled"; 709 #phy-cells = <0>; 710 }; 711 }; 712 }; 713 714 hsic { 715 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 716 clock-names = "trk"; 717 status = "disabled"; 718 719 lanes { 720 hsic-0 { 721 status = "disabled"; 722 #phy-cells = <0>; 723 }; 724 }; 725 }; 726 727 usb3 { 728 status = "disabled"; 729 730 lanes { 731 usb3-0 { 732 status = "disabled"; 733 #phy-cells = <0>; 734 }; 735 736 usb3-1 { 737 status = "disabled"; 738 #phy-cells = <0>; 739 }; 740 741 usb3-2 { 742 status = "disabled"; 743 #phy-cells = <0>; 744 }; 745 }; 746 }; 747 }; 748 749 ports { 750 usb2-0 { 751 status = "disabled"; 752 }; 753 754 usb2-1 { 755 status = "disabled"; 756 }; 757 758 usb2-2 { 759 status = "disabled"; 760 }; 761 762 hsic-0 { 763 status = "disabled"; 764 }; 765 766 usb3-0 { 767 status = "disabled"; 768 }; 769 770 usb3-1 { 771 status = "disabled"; 772 }; 773 774 usb3-2 { 775 status = "disabled"; 776 }; 777 }; 778 }; 779 780 usb@3530000 { 781 compatible = "nvidia,tegra186-xusb"; 782 reg = <0x0 0x03530000 0x0 0x8000>, 783 <0x0 0x03538000 0x0 0x1000>; 784 reg-names = "hcd", "fpci"; 785 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 788 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 789 <&bpmp TEGRA186_CLK_XUSB_SS>, 790 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 791 <&bpmp TEGRA186_CLK_CLK_M>, 792 <&bpmp TEGRA186_CLK_XUSB_FS>, 793 <&bpmp TEGRA186_CLK_PLLU>, 794 <&bpmp TEGRA186_CLK_CLK_M>, 795 <&bpmp TEGRA186_CLK_PLLE>; 796 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 797 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 798 "pll_u_480m", "clk_m", "pll_e"; 799 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 800 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 801 power-domain-names = "xusb_host", "xusb_ss"; 802 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 803 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 804 interconnect-names = "dma-mem", "write"; 805 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 810 nvidia,xusb-padctl = <&padctl>; 811 }; 812 813 usb@3550000 { 814 compatible = "nvidia,tegra186-xudc"; 815 reg = <0x0 0x03550000 0x0 0x8000>, 816 <0x0 0x03558000 0x0 0x1000>; 817 reg-names = "base", "fpci"; 818 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 820 <&bpmp TEGRA186_CLK_XUSB_SS>, 821 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 822 <&bpmp TEGRA186_CLK_XUSB_FS>; 823 clock-names = "dev", "ss", "ss_src", "fs_src"; 824 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 825 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 826 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 827 power-domain-names = "dev", "ss"; 828 nvidia,xusb-padctl = <&padctl>; 829 status = "disabled"; 830 }; 831 832 fuse@3820000 { 833 compatible = "nvidia,tegra186-efuse"; 834 reg = <0x0 0x03820000 0x0 0x10000>; 835 clocks = <&bpmp TEGRA186_CLK_FUSE>; 836 clock-names = "fuse"; 837 }; 838 839 gic: interrupt-controller@3881000 { 840 compatible = "arm,gic-400"; 841 #interrupt-cells = <3>; 842 interrupt-controller; 843 reg = <0x0 0x03881000 0x0 0x1000>, 844 <0x0 0x03882000 0x0 0x2000>; 845 interrupts = <GIC_PPI 9 846 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 847 interrupt-parent = <&gic>; 848 }; 849 850 cec@3960000 { 851 compatible = "nvidia,tegra186-cec"; 852 reg = <0x0 0x03960000 0x0 0x10000>; 853 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&bpmp TEGRA186_CLK_CEC>; 855 clock-names = "cec"; 856 status = "disabled"; 857 }; 858 859 hsp_top0: hsp@3c00000 { 860 compatible = "nvidia,tegra186-hsp"; 861 reg = <0x0 0x03c00000 0x0 0xa0000>; 862 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "doorbell"; 864 #mbox-cells = <2>; 865 status = "disabled"; 866 }; 867 868 gen2_i2c: i2c@c240000 { 869 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 870 reg = <0x0 0x0c240000 0x0 0x10000>; 871 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 clocks = <&bpmp TEGRA186_CLK_I2C2>; 875 clock-names = "div-clk"; 876 resets = <&bpmp TEGRA186_RESET_I2C2>; 877 reset-names = "i2c"; 878 status = "disabled"; 879 }; 880 881 gen8_i2c: i2c@c250000 { 882 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 883 reg = <0x0 0x0c250000 0x0 0x10000>; 884 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 clocks = <&bpmp TEGRA186_CLK_I2C8>; 888 clock-names = "div-clk"; 889 resets = <&bpmp TEGRA186_RESET_I2C8>; 890 reset-names = "i2c"; 891 status = "disabled"; 892 }; 893 894 uartc: serial@c280000 { 895 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 896 reg = <0x0 0x0c280000 0x0 0x40>; 897 reg-shift = <2>; 898 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&bpmp TEGRA186_CLK_UARTC>; 900 clock-names = "serial"; 901 resets = <&bpmp TEGRA186_RESET_UARTC>; 902 reset-names = "serial"; 903 status = "disabled"; 904 }; 905 906 uartg: serial@c290000 { 907 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 908 reg = <0x0 0x0c290000 0x0 0x40>; 909 reg-shift = <2>; 910 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&bpmp TEGRA186_CLK_UARTG>; 912 clock-names = "serial"; 913 resets = <&bpmp TEGRA186_RESET_UARTG>; 914 reset-names = "serial"; 915 status = "disabled"; 916 }; 917 918 rtc: rtc@c2a0000 { 919 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 920 reg = <0 0x0c2a0000 0 0x10000>; 921 interrupt-parent = <&pmc>; 922 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 924 clock-names = "rtc"; 925 status = "disabled"; 926 }; 927 928 gpio_aon: gpio@c2f0000 { 929 compatible = "nvidia,tegra186-gpio-aon"; 930 reg-names = "security", "gpio"; 931 reg = <0x0 0xc2f0000 0x0 0x1000>, 932 <0x0 0xc2f1000 0x0 0x1000>; 933 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 934 gpio-controller; 935 #gpio-cells = <2>; 936 interrupt-controller; 937 #interrupt-cells = <2>; 938 }; 939 940 pmc: pmc@c360000 { 941 compatible = "nvidia,tegra186-pmc"; 942 reg = <0 0x0c360000 0 0x10000>, 943 <0 0x0c370000 0 0x10000>, 944 <0 0x0c380000 0 0x10000>, 945 <0 0x0c390000 0 0x10000>; 946 reg-names = "pmc", "wake", "aotag", "scratch"; 947 948 #interrupt-cells = <2>; 949 interrupt-controller; 950 951 sdmmc1_3v3: sdmmc1-3v3 { 952 pins = "sdmmc1-hv"; 953 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 954 }; 955 956 sdmmc1_1v8: sdmmc1-1v8 { 957 pins = "sdmmc1-hv"; 958 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 959 }; 960 961 sdmmc2_3v3: sdmmc2-3v3 { 962 pins = "sdmmc2-hv"; 963 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 964 }; 965 966 sdmmc2_1v8: sdmmc2-1v8 { 967 pins = "sdmmc2-hv"; 968 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 969 }; 970 971 sdmmc3_3v3: sdmmc3-3v3 { 972 pins = "sdmmc3-hv"; 973 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 974 }; 975 976 sdmmc3_1v8: sdmmc3-1v8 { 977 pins = "sdmmc3-hv"; 978 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 979 }; 980 }; 981 982 ccplex@e000000 { 983 compatible = "nvidia,tegra186-ccplex-cluster"; 984 reg = <0x0 0x0e000000 0x0 0x3fffff>; 985 986 nvidia,bpmp = <&bpmp>; 987 }; 988 989 pcie@10003000 { 990 compatible = "nvidia,tegra186-pcie"; 991 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 992 device_type = "pci"; 993 reg = <0x0 0x10003000 0x0 0x00000800>, /* PADS registers */ 994 <0x0 0x10003800 0x0 0x00000800>, /* AFI registers */ 995 <0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 996 reg-names = "pads", "afi", "cs"; 997 998 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 999 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1000 interrupt-names = "intr", "msi"; 1001 1002 #interrupt-cells = <1>; 1003 interrupt-map-mask = <0 0 0 0>; 1004 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1005 1006 bus-range = <0x00 0xff>; 1007 #address-cells = <3>; 1008 #size-cells = <2>; 1009 1010 ranges = <0x02000000 0 0x10000000 0x0 0x10000000 0 0x00001000>, /* port 0 configuration space */ 1011 <0x02000000 0 0x10001000 0x0 0x10001000 0 0x00001000>,/* port 1 configuration space */ 1012 <0x02000000 0 0x10004000 0x0 0x10004000 0 0x00001000>, /* port 2 configuration space */ 1013 <0x01000000 0 0x0 0x0 0x50000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 1014 <0x02000000 0 0x50100000 0x0 0x50100000 0 0x07f00000>, /* non-prefetchable memory (127 MiB) */ 1015 <0x42000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 1016 1017 clocks = <&bpmp TEGRA186_CLK_PCIE>, 1018 <&bpmp TEGRA186_CLK_AFI>, 1019 <&bpmp TEGRA186_CLK_PLLE>; 1020 clock-names = "pex", "afi", "pll_e"; 1021 1022 resets = <&bpmp TEGRA186_RESET_PCIE>, 1023 <&bpmp TEGRA186_RESET_AFI>, 1024 <&bpmp TEGRA186_RESET_PCIEXCLK>; 1025 reset-names = "pex", "afi", "pcie_x"; 1026 1027 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 1028 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 1029 interconnect-names = "dma-mem", "write"; 1030 1031 iommus = <&smmu TEGRA186_SID_AFI>; 1032 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 1033 iommu-map-mask = <0x0>; 1034 1035 status = "disabled"; 1036 1037 pci@1,0 { 1038 device_type = "pci"; 1039 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 1040 reg = <0x000800 0 0 0 0>; 1041 status = "disabled"; 1042 1043 #address-cells = <3>; 1044 #size-cells = <2>; 1045 ranges; 1046 1047 nvidia,num-lanes = <2>; 1048 }; 1049 1050 pci@2,0 { 1051 device_type = "pci"; 1052 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 1053 reg = <0x001000 0 0 0 0>; 1054 status = "disabled"; 1055 1056 #address-cells = <3>; 1057 #size-cells = <2>; 1058 ranges; 1059 1060 nvidia,num-lanes = <1>; 1061 }; 1062 1063 pci@3,0 { 1064 device_type = "pci"; 1065 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 1066 reg = <0x001800 0 0 0 0>; 1067 status = "disabled"; 1068 1069 #address-cells = <3>; 1070 #size-cells = <2>; 1071 ranges; 1072 1073 nvidia,num-lanes = <1>; 1074 }; 1075 }; 1076 1077 smmu: iommu@12000000 { 1078 compatible = "arm,mmu-500"; 1079 reg = <0 0x12000000 0 0x800000>; 1080 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1143 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1145 stream-match-mask = <0x7f80>; 1146 #global-interrupts = <1>; 1147 #iommu-cells = <1>; 1148 }; 1149 1150 host1x@13e00000 { 1151 compatible = "nvidia,tegra186-host1x"; 1152 reg = <0x0 0x13e00000 0x0 0x10000>, 1153 <0x0 0x13e10000 0x0 0x10000>; 1154 reg-names = "hypervisor", "vm"; 1155 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1157 interrupt-names = "syncpt", "host1x"; 1158 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 1159 clock-names = "host1x"; 1160 resets = <&bpmp TEGRA186_RESET_HOST1X>; 1161 reset-names = "host1x"; 1162 1163 #address-cells = <1>; 1164 #size-cells = <1>; 1165 1166 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 1167 1168 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 1169 interconnect-names = "dma-mem"; 1170 1171 iommus = <&smmu TEGRA186_SID_HOST1X>; 1172 1173 dpaux1: dpaux@15040000 { 1174 compatible = "nvidia,tegra186-dpaux"; 1175 reg = <0x15040000 0x10000>; 1176 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 1178 <&bpmp TEGRA186_CLK_PLLDP>; 1179 clock-names = "dpaux", "parent"; 1180 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 1181 reset-names = "dpaux"; 1182 status = "disabled"; 1183 1184 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1185 1186 state_dpaux1_aux: pinmux-aux { 1187 groups = "dpaux-io"; 1188 function = "aux"; 1189 }; 1190 1191 state_dpaux1_i2c: pinmux-i2c { 1192 groups = "dpaux-io"; 1193 function = "i2c"; 1194 }; 1195 1196 state_dpaux1_off: pinmux-off { 1197 groups = "dpaux-io"; 1198 function = "off"; 1199 }; 1200 1201 i2c-bus { 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 }; 1205 }; 1206 1207 display-hub@15200000 { 1208 compatible = "nvidia,tegra186-display"; 1209 reg = <0x15200000 0x00040000>; 1210 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 1211 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 1212 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 1213 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1214 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1215 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1216 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1217 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1218 "wgrp3", "wgrp4", "wgrp5"; 1219 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1220 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1221 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1222 clock-names = "disp", "dsc", "hub"; 1223 status = "disabled"; 1224 1225 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1226 1227 #address-cells = <1>; 1228 #size-cells = <1>; 1229 1230 ranges = <0x15200000 0x15200000 0x40000>; 1231 1232 display@15200000 { 1233 compatible = "nvidia,tegra186-dc"; 1234 reg = <0x15200000 0x10000>; 1235 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1237 clock-names = "dc"; 1238 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1239 reset-names = "dc"; 1240 1241 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1242 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1243 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1244 interconnect-names = "dma-mem", "read-1"; 1245 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1246 1247 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1248 nvidia,head = <0>; 1249 }; 1250 1251 display@15210000 { 1252 compatible = "nvidia,tegra186-dc"; 1253 reg = <0x15210000 0x10000>; 1254 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1256 clock-names = "dc"; 1257 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1258 reset-names = "dc"; 1259 1260 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1261 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1262 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1263 interconnect-names = "dma-mem", "read-1"; 1264 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1265 1266 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1267 nvidia,head = <1>; 1268 }; 1269 1270 display@15220000 { 1271 compatible = "nvidia,tegra186-dc"; 1272 reg = <0x15220000 0x10000>; 1273 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1275 clock-names = "dc"; 1276 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1277 reset-names = "dc"; 1278 1279 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1280 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1281 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1282 interconnect-names = "dma-mem", "read-1"; 1283 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1284 1285 nvidia,outputs = <&sor0 &sor1>; 1286 nvidia,head = <2>; 1287 }; 1288 }; 1289 1290 dsia: dsi@15300000 { 1291 compatible = "nvidia,tegra186-dsi"; 1292 reg = <0x15300000 0x10000>; 1293 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&bpmp TEGRA186_CLK_DSI>, 1295 <&bpmp TEGRA186_CLK_DSIA_LP>, 1296 <&bpmp TEGRA186_CLK_PLLD>; 1297 clock-names = "dsi", "lp", "parent"; 1298 resets = <&bpmp TEGRA186_RESET_DSI>; 1299 reset-names = "dsi"; 1300 status = "disabled"; 1301 1302 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1303 }; 1304 1305 vic@15340000 { 1306 compatible = "nvidia,tegra186-vic"; 1307 reg = <0x15340000 0x40000>; 1308 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1309 clocks = <&bpmp TEGRA186_CLK_VIC>; 1310 clock-names = "vic"; 1311 resets = <&bpmp TEGRA186_RESET_VIC>; 1312 reset-names = "vic"; 1313 1314 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1315 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1316 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1317 interconnect-names = "dma-mem", "write"; 1318 iommus = <&smmu TEGRA186_SID_VIC>; 1319 }; 1320 1321 dsib: dsi@15400000 { 1322 compatible = "nvidia,tegra186-dsi"; 1323 reg = <0x15400000 0x10000>; 1324 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1326 <&bpmp TEGRA186_CLK_DSIB_LP>, 1327 <&bpmp TEGRA186_CLK_PLLD>; 1328 clock-names = "dsi", "lp", "parent"; 1329 resets = <&bpmp TEGRA186_RESET_DSIB>; 1330 reset-names = "dsi"; 1331 status = "disabled"; 1332 1333 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1334 }; 1335 1336 sor0: sor@15540000 { 1337 compatible = "nvidia,tegra186-sor"; 1338 reg = <0x15540000 0x10000>; 1339 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1341 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1342 <&bpmp TEGRA186_CLK_PLLD2>, 1343 <&bpmp TEGRA186_CLK_PLLDP>, 1344 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1345 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1346 clock-names = "sor", "out", "parent", "dp", "safe", 1347 "pad"; 1348 resets = <&bpmp TEGRA186_RESET_SOR0>; 1349 reset-names = "sor"; 1350 pinctrl-0 = <&state_dpaux_aux>; 1351 pinctrl-1 = <&state_dpaux_i2c>; 1352 pinctrl-2 = <&state_dpaux_off>; 1353 pinctrl-names = "aux", "i2c", "off"; 1354 status = "disabled"; 1355 1356 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1357 nvidia,interface = <0>; 1358 }; 1359 1360 sor1: sor@15580000 { 1361 compatible = "nvidia,tegra186-sor"; 1362 reg = <0x15580000 0x10000>; 1363 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1365 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1366 <&bpmp TEGRA186_CLK_PLLD3>, 1367 <&bpmp TEGRA186_CLK_PLLDP>, 1368 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1369 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1370 clock-names = "sor", "out", "parent", "dp", "safe", 1371 "pad"; 1372 resets = <&bpmp TEGRA186_RESET_SOR1>; 1373 reset-names = "sor"; 1374 pinctrl-0 = <&state_dpaux1_aux>; 1375 pinctrl-1 = <&state_dpaux1_i2c>; 1376 pinctrl-2 = <&state_dpaux1_off>; 1377 pinctrl-names = "aux", "i2c", "off"; 1378 status = "disabled"; 1379 1380 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1381 nvidia,interface = <1>; 1382 }; 1383 1384 dpaux: dpaux@155c0000 { 1385 compatible = "nvidia,tegra186-dpaux"; 1386 reg = <0x155c0000 0x10000>; 1387 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1389 <&bpmp TEGRA186_CLK_PLLDP>; 1390 clock-names = "dpaux", "parent"; 1391 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1392 reset-names = "dpaux"; 1393 status = "disabled"; 1394 1395 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1396 1397 state_dpaux_aux: pinmux-aux { 1398 groups = "dpaux-io"; 1399 function = "aux"; 1400 }; 1401 1402 state_dpaux_i2c: pinmux-i2c { 1403 groups = "dpaux-io"; 1404 function = "i2c"; 1405 }; 1406 1407 state_dpaux_off: pinmux-off { 1408 groups = "dpaux-io"; 1409 function = "off"; 1410 }; 1411 1412 i2c-bus { 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 }; 1416 }; 1417 1418 padctl@15880000 { 1419 compatible = "nvidia,tegra186-dsi-padctl"; 1420 reg = <0x15880000 0x10000>; 1421 resets = <&bpmp TEGRA186_RESET_DSI>; 1422 reset-names = "dsi"; 1423 status = "disabled"; 1424 }; 1425 1426 dsic: dsi@15900000 { 1427 compatible = "nvidia,tegra186-dsi"; 1428 reg = <0x15900000 0x10000>; 1429 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1430 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1431 <&bpmp TEGRA186_CLK_DSIC_LP>, 1432 <&bpmp TEGRA186_CLK_PLLD>; 1433 clock-names = "dsi", "lp", "parent"; 1434 resets = <&bpmp TEGRA186_RESET_DSIC>; 1435 reset-names = "dsi"; 1436 status = "disabled"; 1437 1438 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1439 }; 1440 1441 dsid: dsi@15940000 { 1442 compatible = "nvidia,tegra186-dsi"; 1443 reg = <0x15940000 0x10000>; 1444 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&bpmp TEGRA186_CLK_DSID>, 1446 <&bpmp TEGRA186_CLK_DSID_LP>, 1447 <&bpmp TEGRA186_CLK_PLLD>; 1448 clock-names = "dsi", "lp", "parent"; 1449 resets = <&bpmp TEGRA186_RESET_DSID>; 1450 reset-names = "dsi"; 1451 status = "disabled"; 1452 1453 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1454 }; 1455 }; 1456 1457 gpu@17000000 { 1458 compatible = "nvidia,gp10b"; 1459 reg = <0x0 0x17000000 0x0 0x1000000>, 1460 <0x0 0x18000000 0x0 0x1000000>; 1461 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1463 interrupt-names = "stall", "nonstall"; 1464 1465 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1466 <&bpmp TEGRA186_CLK_GPU>; 1467 clock-names = "gpu", "pwr"; 1468 resets = <&bpmp TEGRA186_RESET_GPU>; 1469 reset-names = "gpu"; 1470 status = "disabled"; 1471 1472 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1473 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1474 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1475 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1476 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1477 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1478 }; 1479 1480 sram@30000000 { 1481 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1482 reg = <0x0 0x30000000 0x0 0x50000>; 1483 #address-cells = <1>; 1484 #size-cells = <1>; 1485 ranges = <0x0 0x0 0x30000000 0x50000>; 1486 1487 cpu_bpmp_tx: sram@4e000 { 1488 reg = <0x4e000 0x1000>; 1489 label = "cpu-bpmp-tx"; 1490 pool; 1491 }; 1492 1493 cpu_bpmp_rx: sram@4f000 { 1494 reg = <0x4f000 0x1000>; 1495 label = "cpu-bpmp-rx"; 1496 pool; 1497 }; 1498 }; 1499 1500 bpmp: bpmp { 1501 compatible = "nvidia,tegra186-bpmp"; 1502 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1503 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1504 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1505 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1506 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1507 iommus = <&smmu TEGRA186_SID_BPMP>; 1508 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1509 TEGRA_HSP_DB_MASTER_BPMP>; 1510 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1511 #clock-cells = <1>; 1512 #reset-cells = <1>; 1513 #power-domain-cells = <1>; 1514 1515 bpmp_i2c: i2c { 1516 compatible = "nvidia,tegra186-bpmp-i2c"; 1517 nvidia,bpmp-bus-id = <5>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 1523 bpmp_thermal: thermal { 1524 compatible = "nvidia,tegra186-bpmp-thermal"; 1525 #thermal-sensor-cells = <1>; 1526 }; 1527 }; 1528 1529 cpus { 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 1533 cpu@0 { 1534 compatible = "nvidia,tegra186-denver"; 1535 device_type = "cpu"; 1536 i-cache-size = <0x20000>; 1537 i-cache-line-size = <64>; 1538 i-cache-sets = <512>; 1539 d-cache-size = <0x10000>; 1540 d-cache-line-size = <64>; 1541 d-cache-sets = <256>; 1542 next-level-cache = <&L2_DENVER>; 1543 reg = <0x000>; 1544 }; 1545 1546 cpu@1 { 1547 compatible = "nvidia,tegra186-denver"; 1548 device_type = "cpu"; 1549 i-cache-size = <0x20000>; 1550 i-cache-line-size = <64>; 1551 i-cache-sets = <512>; 1552 d-cache-size = <0x10000>; 1553 d-cache-line-size = <64>; 1554 d-cache-sets = <256>; 1555 next-level-cache = <&L2_DENVER>; 1556 reg = <0x001>; 1557 }; 1558 1559 cpu@2 { 1560 compatible = "arm,cortex-a57"; 1561 device_type = "cpu"; 1562 i-cache-size = <0xC000>; 1563 i-cache-line-size = <64>; 1564 i-cache-sets = <256>; 1565 d-cache-size = <0x8000>; 1566 d-cache-line-size = <64>; 1567 d-cache-sets = <256>; 1568 next-level-cache = <&L2_A57>; 1569 reg = <0x100>; 1570 }; 1571 1572 cpu@3 { 1573 compatible = "arm,cortex-a57"; 1574 device_type = "cpu"; 1575 i-cache-size = <0xC000>; 1576 i-cache-line-size = <64>; 1577 i-cache-sets = <256>; 1578 d-cache-size = <0x8000>; 1579 d-cache-line-size = <64>; 1580 d-cache-sets = <256>; 1581 next-level-cache = <&L2_A57>; 1582 reg = <0x101>; 1583 }; 1584 1585 cpu@4 { 1586 compatible = "arm,cortex-a57"; 1587 device_type = "cpu"; 1588 i-cache-size = <0xC000>; 1589 i-cache-line-size = <64>; 1590 i-cache-sets = <256>; 1591 d-cache-size = <0x8000>; 1592 d-cache-line-size = <64>; 1593 d-cache-sets = <256>; 1594 next-level-cache = <&L2_A57>; 1595 reg = <0x102>; 1596 }; 1597 1598 cpu@5 { 1599 compatible = "arm,cortex-a57"; 1600 device_type = "cpu"; 1601 i-cache-size = <0xC000>; 1602 i-cache-line-size = <64>; 1603 i-cache-sets = <256>; 1604 d-cache-size = <0x8000>; 1605 d-cache-line-size = <64>; 1606 d-cache-sets = <256>; 1607 next-level-cache = <&L2_A57>; 1608 reg = <0x103>; 1609 }; 1610 1611 L2_DENVER: l2-cache0 { 1612 compatible = "cache"; 1613 cache-unified; 1614 cache-level = <2>; 1615 cache-size = <0x200000>; 1616 cache-line-size = <64>; 1617 cache-sets = <2048>; 1618 }; 1619 1620 L2_A57: l2-cache1 { 1621 compatible = "cache"; 1622 cache-unified; 1623 cache-level = <2>; 1624 cache-size = <0x200000>; 1625 cache-line-size = <64>; 1626 cache-sets = <2048>; 1627 }; 1628 }; 1629 1630 thermal-zones { 1631 a57 { 1632 polling-delay = <0>; 1633 polling-delay-passive = <1000>; 1634 1635 thermal-sensors = 1636 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1637 1638 trips { 1639 critical { 1640 temperature = <101000>; 1641 hysteresis = <0>; 1642 type = "critical"; 1643 }; 1644 }; 1645 1646 cooling-maps { 1647 }; 1648 }; 1649 1650 denver { 1651 polling-delay = <0>; 1652 polling-delay-passive = <1000>; 1653 1654 thermal-sensors = 1655 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1656 1657 trips { 1658 critical { 1659 temperature = <101000>; 1660 hysteresis = <0>; 1661 type = "critical"; 1662 }; 1663 }; 1664 1665 cooling-maps { 1666 }; 1667 }; 1668 1669 gpu { 1670 polling-delay = <0>; 1671 polling-delay-passive = <1000>; 1672 1673 thermal-sensors = 1674 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1675 1676 trips { 1677 critical { 1678 temperature = <101000>; 1679 hysteresis = <0>; 1680 type = "critical"; 1681 }; 1682 }; 1683 1684 cooling-maps { 1685 }; 1686 }; 1687 1688 pll { 1689 polling-delay = <0>; 1690 polling-delay-passive = <1000>; 1691 1692 thermal-sensors = 1693 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1694 1695 trips { 1696 critical { 1697 temperature = <101000>; 1698 hysteresis = <0>; 1699 type = "critical"; 1700 }; 1701 }; 1702 1703 cooling-maps { 1704 }; 1705 }; 1706 1707 always_on { 1708 polling-delay = <0>; 1709 polling-delay-passive = <1000>; 1710 1711 thermal-sensors = 1712 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1713 1714 trips { 1715 critical { 1716 temperature = <101000>; 1717 hysteresis = <0>; 1718 type = "critical"; 1719 }; 1720 }; 1721 1722 cooling-maps { 1723 }; 1724 }; 1725 }; 1726 1727 timer { 1728 compatible = "arm,armv8-timer"; 1729 interrupts = <GIC_PPI 13 1730 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1731 <GIC_PPI 14 1732 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1733 <GIC_PPI 11 1734 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1735 <GIC_PPI 10 1736 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1737 interrupt-parent = <&gic>; 1738 always-on; 1739 }; 1740}; 1741