1#include <dt-bindings/interrupt-controller/arm-gic.h> 2 3/ { 4 compatible = "nvidia,tegra186"; 5 interrupt-parent = <&gic>; 6 #address-cells = <2>; 7 #size-cells = <2>; 8 9 uarta: serial@3100000 { 10 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 11 reg = <0x0 0x03100000 0x0 0x40>; 12 reg-shift = <2>; 13 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14 status = "disabled"; 15 }; 16 17 gic: interrupt-controller@3881000 { 18 compatible = "arm,gic-400"; 19 #interrupt-cells = <3>; 20 interrupt-controller; 21 reg = <0x0 0x03881000 0x0 0x1000>, 22 <0x0 0x03882000 0x0 0x2000>; 23 interrupts = <GIC_PPI 9 24 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 25 interrupt-parent = <&gic>; 26 }; 27 28 hsp_top0: hsp@3c00000 { 29 compatible = "nvidia,tegra186-hsp"; 30 reg = <0x0 0x03c00000 0x0 0xa0000>; 31 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 32 interrupt-names = "doorbell"; 33 #mbox-cells = <2>; 34 status = "disabled"; 35 }; 36 37 sysram@30000000 { 38 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 39 reg = <0x0 0x30000000 0x0 0x50000>; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 43 44 cpu_bpmp_tx: shmem@4e000 { 45 compatible = "nvidia,tegra186-bpmp-shmem"; 46 reg = <0x0 0x4e000 0x0 0x1000>; 47 label = "cpu-bpmp-tx"; 48 pool; 49 }; 50 51 cpu_bpmp_rx: shmem@4f000 { 52 compatible = "nvidia,tegra186-bpmp-shmem"; 53 reg = <0x0 0x4f000 0x0 0x1000>; 54 label = "cpu-bpmp-rx"; 55 pool; 56 }; 57 }; 58 59 bpmp: bpmp { 60 compatible = "nvidia,tegra186-bpmp"; 61 mboxes = <&hsp_top0 0 19>; 62 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 63 #clock-cells = <1>; 64 #reset-cells = <1>; 65 66 bpmp_i2c: i2c { 67 compatible = "nvidia,tegra186-bpmp-i2c"; 68 nvidia,bpmp-bus-id = <5>; 69 #address-cells = <1>; 70 #size-cells = <0>; 71 status = "disabled"; 72 }; 73 }; 74 75 timer { 76 compatible = "arm,armv8-timer"; 77 interrupts = <GIC_PPI 13 78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 14 80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 11 82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 83 <GIC_PPI 10 84 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 85 interrupt-parent = <&gic>; 86 }; 87}; 88