1#include <dt-bindings/interrupt-controller/arm-gic.h> 2 3/ { 4 compatible = "nvidia,tegra186"; 5 interrupt-parent = <&gic>; 6 #address-cells = <2>; 7 #size-cells = <2>; 8 9 uarta: serial@3100000 { 10 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 11 reg = <0x0 0x03100000 0x0 0x40>; 12 reg-shift = <2>; 13 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14 clocks = <&bpmp 55>; 15 clock-names = "serial"; 16 resets = <&bpmp 47>; 17 reset-names = "serial"; 18 status = "disabled"; 19 }; 20 21 uartb: serial@3110000 { 22 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 23 reg = <0x0 0x03110000 0x0 0x40>; 24 reg-shift = <2>; 25 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 26 clocks = <&bpmp 56>; 27 clock-names = "serial"; 28 resets = <&bpmp 48>; 29 reset-names = "serial"; 30 status = "disabled"; 31 }; 32 33 uartd: serial@3130000 { 34 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 35 reg = <0x0 0x03130000 0x0 0x40>; 36 reg-shift = <2>; 37 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 38 clocks = <&bpmp 77>; 39 clock-names = "serial"; 40 resets = <&bpmp 50>; 41 reset-names = "serial"; 42 status = "disabled"; 43 }; 44 45 uarte: serial@3140000 { 46 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 47 reg = <0x0 0x03140000 0x0 0x40>; 48 reg-shift = <2>; 49 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 50 clocks = <&bpmp 194>; 51 clock-names = "serial"; 52 resets = <&bpmp 132>; 53 reset-names = "serial"; 54 status = "disabled"; 55 }; 56 57 uartf: serial@3150000 { 58 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 59 reg = <0x0 0x03150000 0x0 0x40>; 60 reg-shift = <2>; 61 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 62 clocks = <&bpmp 195>; 63 clock-names = "serial"; 64 resets = <&bpmp 111>; 65 reset-names = "serial"; 66 status = "disabled"; 67 }; 68 69 gen1_i2c: i2c@3160000 { 70 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 71 reg = <0x0 0x03160000 0x0 0x10000>; 72 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 clocks = <&bpmp 47>; 76 clock-names = "div-clk"; 77 resets = <&bpmp 19>; 78 reset-names = "i2c"; 79 status = "disabled"; 80 }; 81 82 cam_i2c: i2c@3180000 { 83 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 84 reg = <0x0 0x03180000 0x0 0x10000>; 85 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 86 #address-cells = <1>; 87 #size-cells = <0>; 88 clocks = <&bpmp 75>; 89 clock-names = "div-clk"; 90 resets = <&bpmp 21>; 91 reset-names = "i2c"; 92 status = "disabled"; 93 }; 94 95 /* shares pads with dpaux1 */ 96 dp_aux_ch1_i2c: i2c@3190000 { 97 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 98 reg = <0x0 0x03190000 0x0 0x10000>; 99 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 clocks = <&bpmp 86>; 103 clock-names = "div-clk"; 104 resets = <&bpmp 22>; 105 reset-names = "i2c"; 106 status = "disabled"; 107 }; 108 109 /* controlled by BPMP, should not be enabled */ 110 pwr_i2c: i2c@31a0000 { 111 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 112 reg = <0x0 0x031a0000 0x0 0x10000>; 113 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 114 #address-cells = <1>; 115 #size-cells = <0>; 116 clocks = <&bpmp 48>; 117 clock-names = "div-clk"; 118 resets = <&bpmp 23>; 119 reset-names = "i2c"; 120 status = "disabled"; 121 }; 122 123 /* shares pads with dpaux0 */ 124 dp_aux_ch0_i2c: i2c@31b0000 { 125 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 126 reg = <0x0 0x031b0000 0x0 0x10000>; 127 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 clocks = <&bpmp 125>; 131 clock-names = "div-clk"; 132 resets = <&bpmp 24>; 133 reset-names = "i2c"; 134 status = "disabled"; 135 }; 136 137 gen7_i2c: i2c@31c0000 { 138 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 139 reg = <0x0 0x031c0000 0x0 0x10000>; 140 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 clocks = <&bpmp 182>; 144 clock-names = "div-clk"; 145 resets = <&bpmp 81>; 146 reset-names = "i2c"; 147 status = "disabled"; 148 }; 149 150 gen9_i2c: i2c@31e0000 { 151 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 152 reg = <0x0 0x031e0000 0x0 0x10000>; 153 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 clocks = <&bpmp 183>; 157 clock-names = "div-clk"; 158 resets = <&bpmp 83>; 159 reset-names = "i2c"; 160 status = "disabled"; 161 }; 162 163 sdmmc1: sdhci@3400000 { 164 compatible = "nvidia,tegra186-sdhci"; 165 reg = <0x0 0x03400000 0x0 0x10000>; 166 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&bpmp 52>; 168 clock-names = "sdhci"; 169 resets = <&bpmp 33>; 170 reset-names = "sdhci"; 171 status = "disabled"; 172 }; 173 174 sdmmc2: sdhci@3420000 { 175 compatible = "nvidia,tegra186-sdhci"; 176 reg = <0x0 0x03420000 0x0 0x10000>; 177 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&bpmp 53>; 179 clock-names = "sdhci"; 180 resets = <&bpmp 34>; 181 reset-names = "sdhci"; 182 status = "disabled"; 183 }; 184 185 sdmmc3: sdhci@3440000 { 186 compatible = "nvidia,tegra186-sdhci"; 187 reg = <0x0 0x03440000 0x0 0x10000>; 188 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&bpmp 76>; 190 clock-names = "sdhci"; 191 resets = <&bpmp 35>; 192 reset-names = "sdhci"; 193 status = "disabled"; 194 }; 195 196 sdmmc4: sdhci@3460000 { 197 compatible = "nvidia,tegra186-sdhci"; 198 reg = <0x0 0x03460000 0x0 0x10000>; 199 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&bpmp 54>; 201 clock-names = "sdhci"; 202 resets = <&bpmp 36>; 203 reset-names = "sdhci"; 204 status = "disabled"; 205 }; 206 207 gic: interrupt-controller@3881000 { 208 compatible = "arm,gic-400"; 209 #interrupt-cells = <3>; 210 interrupt-controller; 211 reg = <0x0 0x03881000 0x0 0x1000>, 212 <0x0 0x03882000 0x0 0x2000>; 213 interrupts = <GIC_PPI 9 214 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 215 interrupt-parent = <&gic>; 216 }; 217 218 hsp_top0: hsp@3c00000 { 219 compatible = "nvidia,tegra186-hsp"; 220 reg = <0x0 0x03c00000 0x0 0xa0000>; 221 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 222 interrupt-names = "doorbell"; 223 #mbox-cells = <2>; 224 status = "disabled"; 225 }; 226 227 gen2_i2c: i2c@c240000 { 228 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 229 reg = <0x0 0x0c240000 0x0 0x10000>; 230 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 clocks = <&bpmp 218>; 234 clock-names = "div-clk"; 235 resets = <&bpmp 20>; 236 reset-names = "i2c"; 237 status = "disabled"; 238 }; 239 240 gen8_i2c: i2c@c250000 { 241 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 242 reg = <0x0 0x0c250000 0x0 0x10000>; 243 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 clocks = <&bpmp 219>; 247 clock-names = "div-clk"; 248 resets = <&bpmp 82>; 249 reset-names = "i2c"; 250 status = "disabled"; 251 }; 252 253 uartc: serial@c280000 { 254 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 255 reg = <0x0 0x0c280000 0x0 0x40>; 256 reg-shift = <2>; 257 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&bpmp 215>; 259 clock-names = "serial"; 260 resets = <&bpmp 49>; 261 reset-names = "serial"; 262 status = "disabled"; 263 }; 264 265 uartg: serial@c290000 { 266 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 267 reg = <0x0 0x0c290000 0x0 0x40>; 268 reg-shift = <2>; 269 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&bpmp 216>; 271 clock-names = "serial"; 272 resets = <&bpmp 112>; 273 reset-names = "serial"; 274 status = "disabled"; 275 }; 276 277 sysram@30000000 { 278 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 279 reg = <0x0 0x30000000 0x0 0x50000>; 280 #address-cells = <2>; 281 #size-cells = <2>; 282 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 283 284 cpu_bpmp_tx: shmem@4e000 { 285 compatible = "nvidia,tegra186-bpmp-shmem"; 286 reg = <0x0 0x4e000 0x0 0x1000>; 287 label = "cpu-bpmp-tx"; 288 pool; 289 }; 290 291 cpu_bpmp_rx: shmem@4f000 { 292 compatible = "nvidia,tegra186-bpmp-shmem"; 293 reg = <0x0 0x4f000 0x0 0x1000>; 294 label = "cpu-bpmp-rx"; 295 pool; 296 }; 297 }; 298 299 cpus { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 cpu@0 { 304 compatible = "nvidia,tegra186-denver", "arm,armv8"; 305 device_type = "cpu"; 306 reg = <0x000>; 307 }; 308 309 cpu@1 { 310 compatible = "nvidia,tegra186-denver", "arm,armv8"; 311 device_type = "cpu"; 312 reg = <0x001>; 313 }; 314 315 cpu@2 { 316 compatible = "arm,cortex-a57", "arm,armv8"; 317 device_type = "cpu"; 318 reg = <0x100>; 319 }; 320 321 cpu@3 { 322 compatible = "arm,cortex-a57", "arm,armv8"; 323 device_type = "cpu"; 324 reg = <0x101>; 325 }; 326 327 cpu@4 { 328 compatible = "arm,cortex-a57", "arm,armv8"; 329 device_type = "cpu"; 330 reg = <0x102>; 331 }; 332 333 cpu@5 { 334 compatible = "arm,cortex-a57", "arm,armv8"; 335 device_type = "cpu"; 336 reg = <0x103>; 337 }; 338 }; 339 340 bpmp: bpmp { 341 compatible = "nvidia,tegra186-bpmp"; 342 mboxes = <&hsp_top0 0 19>; 343 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 344 #clock-cells = <1>; 345 #reset-cells = <1>; 346 347 bpmp_i2c: i2c { 348 compatible = "nvidia,tegra186-bpmp-i2c"; 349 nvidia,bpmp-bus-id = <5>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 status = "disabled"; 353 }; 354 }; 355 356 timer { 357 compatible = "arm,armv8-timer"; 358 interrupts = <GIC_PPI 13 359 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 360 <GIC_PPI 14 361 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 362 <GIC_PPI 11 363 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 364 <GIC_PPI 10 365 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 366 interrupt-parent = <&gic>; 367 }; 368}; 369