1#include <dt-bindings/clock/tegra186-clock.h> 2#include <dt-bindings/gpio/tegra186-gpio.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/mailbox/tegra186-hsp.h> 5 6/ { 7 compatible = "nvidia,tegra186"; 8 interrupt-parent = <&gic>; 9 #address-cells = <2>; 10 #size-cells = <2>; 11 12 gpio: gpio@2200000 { 13 compatible = "nvidia,tegra186-gpio"; 14 reg-names = "security", "gpio"; 15 reg = <0x0 0x2200000 0x0 0x10000>, 16 <0x0 0x2210000 0x0 0x10000>; 17 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 18 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 19 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 20 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 23 #interrupt-cells = <2>; 24 interrupt-controller; 25 #gpio-cells = <2>; 26 gpio-controller; 27 }; 28 29 uarta: serial@3100000 { 30 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 31 reg = <0x0 0x03100000 0x0 0x40>; 32 reg-shift = <2>; 33 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 34 clocks = <&bpmp TEGRA186_CLK_UARTA>; 35 clock-names = "serial"; 36 resets = <&bpmp 47>; 37 reset-names = "serial"; 38 status = "disabled"; 39 }; 40 41 uartb: serial@3110000 { 42 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 43 reg = <0x0 0x03110000 0x0 0x40>; 44 reg-shift = <2>; 45 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 46 clocks = <&bpmp TEGRA186_CLK_UARTB>; 47 clock-names = "serial"; 48 resets = <&bpmp 48>; 49 reset-names = "serial"; 50 status = "disabled"; 51 }; 52 53 uartd: serial@3130000 { 54 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 55 reg = <0x0 0x03130000 0x0 0x40>; 56 reg-shift = <2>; 57 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 58 clocks = <&bpmp TEGRA186_CLK_UARTD>; 59 clock-names = "serial"; 60 resets = <&bpmp 50>; 61 reset-names = "serial"; 62 status = "disabled"; 63 }; 64 65 uarte: serial@3140000 { 66 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 67 reg = <0x0 0x03140000 0x0 0x40>; 68 reg-shift = <2>; 69 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 70 clocks = <&bpmp TEGRA186_CLK_UARTE>; 71 clock-names = "serial"; 72 resets = <&bpmp 132>; 73 reset-names = "serial"; 74 status = "disabled"; 75 }; 76 77 uartf: serial@3150000 { 78 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 79 reg = <0x0 0x03150000 0x0 0x40>; 80 reg-shift = <2>; 81 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 82 clocks = <&bpmp TEGRA186_CLK_UARTF>; 83 clock-names = "serial"; 84 resets = <&bpmp 111>; 85 reset-names = "serial"; 86 status = "disabled"; 87 }; 88 89 gen1_i2c: i2c@3160000 { 90 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 91 reg = <0x0 0x03160000 0x0 0x10000>; 92 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 clocks = <&bpmp TEGRA186_CLK_I2C1>; 96 clock-names = "div-clk"; 97 resets = <&bpmp 19>; 98 reset-names = "i2c"; 99 status = "disabled"; 100 }; 101 102 cam_i2c: i2c@3180000 { 103 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 104 reg = <0x0 0x03180000 0x0 0x10000>; 105 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 clocks = <&bpmp TEGRA186_CLK_I2C3>; 109 clock-names = "div-clk"; 110 resets = <&bpmp 21>; 111 reset-names = "i2c"; 112 status = "disabled"; 113 }; 114 115 /* shares pads with dpaux1 */ 116 dp_aux_ch1_i2c: i2c@3190000 { 117 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 118 reg = <0x0 0x03190000 0x0 0x10000>; 119 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 clocks = <&bpmp TEGRA186_CLK_I2C4>; 123 clock-names = "div-clk"; 124 resets = <&bpmp 22>; 125 reset-names = "i2c"; 126 status = "disabled"; 127 }; 128 129 /* controlled by BPMP, should not be enabled */ 130 pwr_i2c: i2c@31a0000 { 131 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 132 reg = <0x0 0x031a0000 0x0 0x10000>; 133 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 clocks = <&bpmp TEGRA186_CLK_I2C5>; 137 clock-names = "div-clk"; 138 resets = <&bpmp 23>; 139 reset-names = "i2c"; 140 status = "disabled"; 141 }; 142 143 /* shares pads with dpaux0 */ 144 dp_aux_ch0_i2c: i2c@31b0000 { 145 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 146 reg = <0x0 0x031b0000 0x0 0x10000>; 147 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 clocks = <&bpmp TEGRA186_CLK_I2C6>; 151 clock-names = "div-clk"; 152 resets = <&bpmp 24>; 153 reset-names = "i2c"; 154 status = "disabled"; 155 }; 156 157 gen7_i2c: i2c@31c0000 { 158 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 159 reg = <0x0 0x031c0000 0x0 0x10000>; 160 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 clocks = <&bpmp TEGRA186_CLK_I2C7>; 164 clock-names = "div-clk"; 165 resets = <&bpmp 81>; 166 reset-names = "i2c"; 167 status = "disabled"; 168 }; 169 170 gen9_i2c: i2c@31e0000 { 171 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 172 reg = <0x0 0x031e0000 0x0 0x10000>; 173 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 clocks = <&bpmp TEGRA186_CLK_I2C9>; 177 clock-names = "div-clk"; 178 resets = <&bpmp 83>; 179 reset-names = "i2c"; 180 status = "disabled"; 181 }; 182 183 sdmmc1: sdhci@3400000 { 184 compatible = "nvidia,tegra186-sdhci"; 185 reg = <0x0 0x03400000 0x0 0x10000>; 186 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 188 clock-names = "sdhci"; 189 resets = <&bpmp 33>; 190 reset-names = "sdhci"; 191 status = "disabled"; 192 }; 193 194 sdmmc2: sdhci@3420000 { 195 compatible = "nvidia,tegra186-sdhci"; 196 reg = <0x0 0x03420000 0x0 0x10000>; 197 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 199 clock-names = "sdhci"; 200 resets = <&bpmp 34>; 201 reset-names = "sdhci"; 202 status = "disabled"; 203 }; 204 205 sdmmc3: sdhci@3440000 { 206 compatible = "nvidia,tegra186-sdhci"; 207 reg = <0x0 0x03440000 0x0 0x10000>; 208 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 210 clock-names = "sdhci"; 211 resets = <&bpmp 35>; 212 reset-names = "sdhci"; 213 status = "disabled"; 214 }; 215 216 sdmmc4: sdhci@3460000 { 217 compatible = "nvidia,tegra186-sdhci"; 218 reg = <0x0 0x03460000 0x0 0x10000>; 219 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 221 clock-names = "sdhci"; 222 resets = <&bpmp 36>; 223 reset-names = "sdhci"; 224 status = "disabled"; 225 }; 226 227 gic: interrupt-controller@3881000 { 228 compatible = "arm,gic-400"; 229 #interrupt-cells = <3>; 230 interrupt-controller; 231 reg = <0x0 0x03881000 0x0 0x1000>, 232 <0x0 0x03882000 0x0 0x2000>; 233 interrupts = <GIC_PPI 9 234 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 235 interrupt-parent = <&gic>; 236 }; 237 238 hsp_top0: hsp@3c00000 { 239 compatible = "nvidia,tegra186-hsp"; 240 reg = <0x0 0x03c00000 0x0 0xa0000>; 241 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 242 interrupt-names = "doorbell"; 243 #mbox-cells = <2>; 244 status = "disabled"; 245 }; 246 247 gen2_i2c: i2c@c240000 { 248 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 249 reg = <0x0 0x0c240000 0x0 0x10000>; 250 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 clocks = <&bpmp TEGRA186_CLK_I2C2>; 254 clock-names = "div-clk"; 255 resets = <&bpmp 20>; 256 reset-names = "i2c"; 257 status = "disabled"; 258 }; 259 260 gen8_i2c: i2c@c250000 { 261 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 262 reg = <0x0 0x0c250000 0x0 0x10000>; 263 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 clocks = <&bpmp TEGRA186_CLK_I2C8>; 267 clock-names = "div-clk"; 268 resets = <&bpmp 82>; 269 reset-names = "i2c"; 270 status = "disabled"; 271 }; 272 273 uartc: serial@c280000 { 274 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 275 reg = <0x0 0x0c280000 0x0 0x40>; 276 reg-shift = <2>; 277 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&bpmp TEGRA186_CLK_UARTC>; 279 clock-names = "serial"; 280 resets = <&bpmp 49>; 281 reset-names = "serial"; 282 status = "disabled"; 283 }; 284 285 uartg: serial@c290000 { 286 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 287 reg = <0x0 0x0c290000 0x0 0x40>; 288 reg-shift = <2>; 289 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&bpmp TEGRA186_CLK_UARTG>; 291 clock-names = "serial"; 292 resets = <&bpmp 112>; 293 reset-names = "serial"; 294 status = "disabled"; 295 }; 296 297 gpio_aon: gpio@c2f0000 { 298 compatible = "nvidia,tegra186-gpio-aon"; 299 reg-names = "security", "gpio"; 300 reg = <0x0 0xc2f0000 0x0 0x1000>, 301 <0x0 0xc2f1000 0x0 0x1000>; 302 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 303 gpio-controller; 304 #gpio-cells = <2>; 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 }; 308 309 sysram@30000000 { 310 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 311 reg = <0x0 0x30000000 0x0 0x50000>; 312 #address-cells = <2>; 313 #size-cells = <2>; 314 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 315 316 cpu_bpmp_tx: shmem@4e000 { 317 compatible = "nvidia,tegra186-bpmp-shmem"; 318 reg = <0x0 0x4e000 0x0 0x1000>; 319 label = "cpu-bpmp-tx"; 320 pool; 321 }; 322 323 cpu_bpmp_rx: shmem@4f000 { 324 compatible = "nvidia,tegra186-bpmp-shmem"; 325 reg = <0x0 0x4f000 0x0 0x1000>; 326 label = "cpu-bpmp-rx"; 327 pool; 328 }; 329 }; 330 331 cpus { 332 #address-cells = <1>; 333 #size-cells = <0>; 334 335 cpu@0 { 336 compatible = "nvidia,tegra186-denver", "arm,armv8"; 337 device_type = "cpu"; 338 reg = <0x000>; 339 }; 340 341 cpu@1 { 342 compatible = "nvidia,tegra186-denver", "arm,armv8"; 343 device_type = "cpu"; 344 reg = <0x001>; 345 }; 346 347 cpu@2 { 348 compatible = "arm,cortex-a57", "arm,armv8"; 349 device_type = "cpu"; 350 reg = <0x100>; 351 }; 352 353 cpu@3 { 354 compatible = "arm,cortex-a57", "arm,armv8"; 355 device_type = "cpu"; 356 reg = <0x101>; 357 }; 358 359 cpu@4 { 360 compatible = "arm,cortex-a57", "arm,armv8"; 361 device_type = "cpu"; 362 reg = <0x102>; 363 }; 364 365 cpu@5 { 366 compatible = "arm,cortex-a57", "arm,armv8"; 367 device_type = "cpu"; 368 reg = <0x103>; 369 }; 370 }; 371 372 bpmp: bpmp { 373 compatible = "nvidia,tegra186-bpmp"; 374 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 375 TEGRA_HSP_DB_MASTER_BPMP>; 376 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 377 #clock-cells = <1>; 378 #reset-cells = <1>; 379 380 bpmp_i2c: i2c { 381 compatible = "nvidia,tegra186-bpmp-i2c"; 382 nvidia,bpmp-bus-id = <5>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 status = "disabled"; 386 }; 387 }; 388 389 timer { 390 compatible = "arm,armv8-timer"; 391 interrupts = <GIC_PPI 13 392 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 393 <GIC_PPI 14 394 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 395 <GIC_PPI 11 396 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 397 <GIC_PPI 10 398 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 399 interrupt-parent = <&gic>; 400 }; 401}; 402