1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 interconnects = <&mc TEGRA186_MEMORY_CLIENT_EQOSR &emc>, 64 <&mc TEGRA186_MEMORY_CLIENT_EQOSW &emc>; 65 interconnect-names = "dma-mem", "write"; 66 iommus = <&smmu TEGRA186_SID_EQOS>; 67 status = "disabled"; 68 69 snps,write-requests = <1>; 70 snps,read-requests = <3>; 71 snps,burst-map = <0x7>; 72 snps,txpbl = <32>; 73 snps,rxpbl = <8>; 74 }; 75 76 aconnect { 77 compatible = "nvidia,tegra186-aconnect", 78 "nvidia,tegra210-aconnect"; 79 clocks = <&bpmp TEGRA186_CLK_APE>, 80 <&bpmp TEGRA186_CLK_APB2APE>; 81 clock-names = "ape", "apb2ape"; 82 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0x02900000 0x0 0x02900000 0x200000>; 86 status = "disabled"; 87 88 dma-controller@2930000 { 89 compatible = "nvidia,tegra186-adma"; 90 reg = <0x02930000 0x20000>; 91 interrupt-parent = <&agic>; 92 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 124 #dma-cells = <1>; 125 clocks = <&bpmp TEGRA186_CLK_AHUB>; 126 clock-names = "d_audio"; 127 status = "disabled"; 128 }; 129 130 agic: interrupt-controller@2a40000 { 131 compatible = "nvidia,tegra186-agic", 132 "nvidia,tegra210-agic"; 133 #interrupt-cells = <3>; 134 interrupt-controller; 135 reg = <0x02a41000 0x1000>, 136 <0x02a42000 0x2000>; 137 interrupts = <GIC_SPI 145 138 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 139 clocks = <&bpmp TEGRA186_CLK_APE>; 140 clock-names = "clk"; 141 status = "disabled"; 142 }; 143 }; 144 145 mc: memory-controller@2c00000 { 146 compatible = "nvidia,tegra186-mc"; 147 reg = <0x0 0x02c00000 0x0 0xb0000>; 148 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 149 status = "disabled"; 150 151 #interconnect-cells = <1>; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 155 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 156 157 /* 158 * Memory clients have access to all 40 bits that the memory 159 * controller can address. 160 */ 161 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 162 163 emc: external-memory-controller@2c60000 { 164 compatible = "nvidia,tegra186-emc"; 165 reg = <0x0 0x02c60000 0x0 0x50000>; 166 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&bpmp TEGRA186_CLK_EMC>; 168 clock-names = "emc"; 169 170 #interconnect-cells = <0>; 171 172 nvidia,bpmp = <&bpmp>; 173 }; 174 }; 175 176 uarta: serial@3100000 { 177 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 178 reg = <0x0 0x03100000 0x0 0x40>; 179 reg-shift = <2>; 180 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&bpmp TEGRA186_CLK_UARTA>; 182 clock-names = "serial"; 183 resets = <&bpmp TEGRA186_RESET_UARTA>; 184 reset-names = "serial"; 185 status = "disabled"; 186 }; 187 188 uartb: serial@3110000 { 189 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 190 reg = <0x0 0x03110000 0x0 0x40>; 191 reg-shift = <2>; 192 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&bpmp TEGRA186_CLK_UARTB>; 194 clock-names = "serial"; 195 resets = <&bpmp TEGRA186_RESET_UARTB>; 196 reset-names = "serial"; 197 status = "disabled"; 198 }; 199 200 uartd: serial@3130000 { 201 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 202 reg = <0x0 0x03130000 0x0 0x40>; 203 reg-shift = <2>; 204 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&bpmp TEGRA186_CLK_UARTD>; 206 clock-names = "serial"; 207 resets = <&bpmp TEGRA186_RESET_UARTD>; 208 reset-names = "serial"; 209 status = "disabled"; 210 }; 211 212 uarte: serial@3140000 { 213 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 214 reg = <0x0 0x03140000 0x0 0x40>; 215 reg-shift = <2>; 216 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&bpmp TEGRA186_CLK_UARTE>; 218 clock-names = "serial"; 219 resets = <&bpmp TEGRA186_RESET_UARTE>; 220 reset-names = "serial"; 221 status = "disabled"; 222 }; 223 224 uartf: serial@3150000 { 225 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 226 reg = <0x0 0x03150000 0x0 0x40>; 227 reg-shift = <2>; 228 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&bpmp TEGRA186_CLK_UARTF>; 230 clock-names = "serial"; 231 resets = <&bpmp TEGRA186_RESET_UARTF>; 232 reset-names = "serial"; 233 status = "disabled"; 234 }; 235 236 gen1_i2c: i2c@3160000 { 237 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 238 reg = <0x0 0x03160000 0x0 0x10000>; 239 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 clocks = <&bpmp TEGRA186_CLK_I2C1>; 243 clock-names = "div-clk"; 244 resets = <&bpmp TEGRA186_RESET_I2C1>; 245 reset-names = "i2c"; 246 status = "disabled"; 247 }; 248 249 cam_i2c: i2c@3180000 { 250 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 251 reg = <0x0 0x03180000 0x0 0x10000>; 252 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 clocks = <&bpmp TEGRA186_CLK_I2C3>; 256 clock-names = "div-clk"; 257 resets = <&bpmp TEGRA186_RESET_I2C3>; 258 reset-names = "i2c"; 259 status = "disabled"; 260 }; 261 262 /* shares pads with dpaux1 */ 263 dp_aux_ch1_i2c: i2c@3190000 { 264 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 265 reg = <0x0 0x03190000 0x0 0x10000>; 266 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 clocks = <&bpmp TEGRA186_CLK_I2C4>; 270 clock-names = "div-clk"; 271 resets = <&bpmp TEGRA186_RESET_I2C4>; 272 reset-names = "i2c"; 273 pinctrl-names = "default", "idle"; 274 pinctrl-0 = <&state_dpaux1_i2c>; 275 pinctrl-1 = <&state_dpaux1_off>; 276 status = "disabled"; 277 }; 278 279 /* controlled by BPMP, should not be enabled */ 280 pwr_i2c: i2c@31a0000 { 281 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 282 reg = <0x0 0x031a0000 0x0 0x10000>; 283 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 clocks = <&bpmp TEGRA186_CLK_I2C5>; 287 clock-names = "div-clk"; 288 resets = <&bpmp TEGRA186_RESET_I2C5>; 289 reset-names = "i2c"; 290 status = "disabled"; 291 }; 292 293 /* shares pads with dpaux0 */ 294 dp_aux_ch0_i2c: i2c@31b0000 { 295 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 296 reg = <0x0 0x031b0000 0x0 0x10000>; 297 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 clocks = <&bpmp TEGRA186_CLK_I2C6>; 301 clock-names = "div-clk"; 302 resets = <&bpmp TEGRA186_RESET_I2C6>; 303 reset-names = "i2c"; 304 pinctrl-names = "default", "idle"; 305 pinctrl-0 = <&state_dpaux_i2c>; 306 pinctrl-1 = <&state_dpaux_off>; 307 status = "disabled"; 308 }; 309 310 gen7_i2c: i2c@31c0000 { 311 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 312 reg = <0x0 0x031c0000 0x0 0x10000>; 313 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 clocks = <&bpmp TEGRA186_CLK_I2C7>; 317 clock-names = "div-clk"; 318 resets = <&bpmp TEGRA186_RESET_I2C7>; 319 reset-names = "i2c"; 320 status = "disabled"; 321 }; 322 323 gen9_i2c: i2c@31e0000 { 324 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 325 reg = <0x0 0x031e0000 0x0 0x10000>; 326 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 clocks = <&bpmp TEGRA186_CLK_I2C9>; 330 clock-names = "div-clk"; 331 resets = <&bpmp TEGRA186_RESET_I2C9>; 332 reset-names = "i2c"; 333 status = "disabled"; 334 }; 335 336 sdmmc1: mmc@3400000 { 337 compatible = "nvidia,tegra186-sdhci"; 338 reg = <0x0 0x03400000 0x0 0x10000>; 339 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 341 clock-names = "sdhci"; 342 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 343 reset-names = "sdhci"; 344 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>, 345 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>; 346 interconnect-names = "dma-mem", "write"; 347 iommus = <&smmu TEGRA186_SID_SDMMC1>; 348 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 349 pinctrl-0 = <&sdmmc1_3v3>; 350 pinctrl-1 = <&sdmmc1_1v8>; 351 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 352 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 353 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 354 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 355 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 356 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 357 nvidia,default-tap = <0x5>; 358 nvidia,default-trim = <0xb>; 359 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 360 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 361 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 362 status = "disabled"; 363 }; 364 365 sdmmc2: mmc@3420000 { 366 compatible = "nvidia,tegra186-sdhci"; 367 reg = <0x0 0x03420000 0x0 0x10000>; 368 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 370 clock-names = "sdhci"; 371 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 372 reset-names = "sdhci"; 373 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAA &emc>, 374 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAA &emc>; 375 interconnect-names = "dma-mem", "write"; 376 iommus = <&smmu TEGRA186_SID_SDMMC2>; 377 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 378 pinctrl-0 = <&sdmmc2_3v3>; 379 pinctrl-1 = <&sdmmc2_1v8>; 380 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 381 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 382 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 383 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 384 nvidia,default-tap = <0x5>; 385 nvidia,default-trim = <0xb>; 386 status = "disabled"; 387 }; 388 389 sdmmc3: mmc@3440000 { 390 compatible = "nvidia,tegra186-sdhci"; 391 reg = <0x0 0x03440000 0x0 0x10000>; 392 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 394 clock-names = "sdhci"; 395 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 396 reset-names = "sdhci"; 397 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCR &emc>, 398 <&mc TEGRA186_MEMORY_CLIENT_SDMMCW &emc>; 399 interconnect-names = "dma-mem", "write"; 400 iommus = <&smmu TEGRA186_SID_SDMMC3>; 401 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 402 pinctrl-0 = <&sdmmc3_3v3>; 403 pinctrl-1 = <&sdmmc3_1v8>; 404 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 405 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 406 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 407 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 408 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 409 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 410 nvidia,default-tap = <0x5>; 411 nvidia,default-trim = <0xb>; 412 status = "disabled"; 413 }; 414 415 sdmmc4: mmc@3460000 { 416 compatible = "nvidia,tegra186-sdhci"; 417 reg = <0x0 0x03460000 0x0 0x10000>; 418 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 420 clock-names = "sdhci"; 421 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 422 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 423 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 424 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 425 reset-names = "sdhci"; 426 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRAB &emc>, 427 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWAB &emc>; 428 interconnect-names = "dma-mem", "write"; 429 iommus = <&smmu TEGRA186_SID_SDMMC4>; 430 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 431 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 432 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 433 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 434 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 435 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 436 nvidia,default-tap = <0x9>; 437 nvidia,default-trim = <0x5>; 438 nvidia,dqs-trim = <63>; 439 mmc-hs400-1_8v; 440 supports-cqe; 441 status = "disabled"; 442 }; 443 444 hda@3510000 { 445 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 446 reg = <0x0 0x03510000 0x0 0x10000>; 447 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&bpmp TEGRA186_CLK_HDA>, 449 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 450 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 451 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 452 resets = <&bpmp TEGRA186_RESET_HDA>, 453 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 454 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 455 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 456 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 457 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HDAR &emc>, 458 <&mc TEGRA186_MEMORY_CLIENT_HDAW &emc>; 459 interconnect-names = "dma-mem", "write"; 460 iommus = <&smmu TEGRA186_SID_HDA>; 461 status = "disabled"; 462 }; 463 464 padctl: padctl@3520000 { 465 compatible = "nvidia,tegra186-xusb-padctl"; 466 reg = <0x0 0x03520000 0x0 0x1000>, 467 <0x0 0x03540000 0x0 0x1000>; 468 reg-names = "padctl", "ao"; 469 470 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 471 reset-names = "padctl"; 472 473 status = "disabled"; 474 475 pads { 476 usb2 { 477 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 478 clock-names = "trk"; 479 status = "disabled"; 480 481 lanes { 482 usb2-0 { 483 status = "disabled"; 484 #phy-cells = <0>; 485 }; 486 487 usb2-1 { 488 status = "disabled"; 489 #phy-cells = <0>; 490 }; 491 492 usb2-2 { 493 status = "disabled"; 494 #phy-cells = <0>; 495 }; 496 }; 497 }; 498 499 hsic { 500 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 501 clock-names = "trk"; 502 status = "disabled"; 503 504 lanes { 505 hsic-0 { 506 status = "disabled"; 507 #phy-cells = <0>; 508 }; 509 }; 510 }; 511 512 usb3 { 513 status = "disabled"; 514 515 lanes { 516 usb3-0 { 517 status = "disabled"; 518 #phy-cells = <0>; 519 }; 520 521 usb3-1 { 522 status = "disabled"; 523 #phy-cells = <0>; 524 }; 525 526 usb3-2 { 527 status = "disabled"; 528 #phy-cells = <0>; 529 }; 530 }; 531 }; 532 }; 533 534 ports { 535 usb2-0 { 536 status = "disabled"; 537 }; 538 539 usb2-1 { 540 status = "disabled"; 541 }; 542 543 usb2-2 { 544 status = "disabled"; 545 }; 546 547 hsic-0 { 548 status = "disabled"; 549 }; 550 551 usb3-0 { 552 status = "disabled"; 553 }; 554 555 usb3-1 { 556 status = "disabled"; 557 }; 558 559 usb3-2 { 560 status = "disabled"; 561 }; 562 }; 563 }; 564 565 usb@3530000 { 566 compatible = "nvidia,tegra186-xusb"; 567 reg = <0x0 0x03530000 0x0 0x8000>, 568 <0x0 0x03538000 0x0 0x1000>; 569 reg-names = "hcd", "fpci"; 570 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 574 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 575 <&bpmp TEGRA186_CLK_XUSB_SS>, 576 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 577 <&bpmp TEGRA186_CLK_CLK_M>, 578 <&bpmp TEGRA186_CLK_XUSB_FS>, 579 <&bpmp TEGRA186_CLK_PLLU>, 580 <&bpmp TEGRA186_CLK_CLK_M>, 581 <&bpmp TEGRA186_CLK_PLLE>; 582 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 583 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 584 "pll_u_480m", "clk_m", "pll_e"; 585 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 586 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 587 power-domain-names = "xusb_host", "xusb_ss"; 588 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>, 589 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>; 590 interconnect-names = "dma-mem", "write"; 591 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 status = "disabled"; 595 596 nvidia,xusb-padctl = <&padctl>; 597 }; 598 599 usb@3550000 { 600 compatible = "nvidia,tegra186-xudc"; 601 reg = <0x0 0x03550000 0x0 0x8000>, 602 <0x0 0x03558000 0x0 0x1000>; 603 reg-names = "base", "fpci"; 604 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, 606 <&bpmp TEGRA186_CLK_XUSB_SS>, 607 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 608 <&bpmp TEGRA186_CLK_XUSB_FS>; 609 clock-names = "dev", "ss", "ss_src", "fs_src"; 610 iommus = <&smmu TEGRA186_SID_XUSB_DEV>; 611 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, 612 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 613 power-domain-names = "dev", "ss"; 614 nvidia,xusb-padctl = <&padctl>; 615 status = "disabled"; 616 }; 617 618 fuse@3820000 { 619 compatible = "nvidia,tegra186-efuse"; 620 reg = <0x0 0x03820000 0x0 0x10000>; 621 clocks = <&bpmp TEGRA186_CLK_FUSE>; 622 clock-names = "fuse"; 623 }; 624 625 gic: interrupt-controller@3881000 { 626 compatible = "arm,gic-400"; 627 #interrupt-cells = <3>; 628 interrupt-controller; 629 reg = <0x0 0x03881000 0x0 0x1000>, 630 <0x0 0x03882000 0x0 0x2000>; 631 interrupts = <GIC_PPI 9 632 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 633 interrupt-parent = <&gic>; 634 }; 635 636 cec@3960000 { 637 compatible = "nvidia,tegra186-cec"; 638 reg = <0x0 0x03960000 0x0 0x10000>; 639 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&bpmp TEGRA186_CLK_CEC>; 641 clock-names = "cec"; 642 status = "disabled"; 643 }; 644 645 hsp_top0: hsp@3c00000 { 646 compatible = "nvidia,tegra186-hsp"; 647 reg = <0x0 0x03c00000 0x0 0xa0000>; 648 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 649 interrupt-names = "doorbell"; 650 #mbox-cells = <2>; 651 status = "disabled"; 652 }; 653 654 gen2_i2c: i2c@c240000 { 655 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 656 reg = <0x0 0x0c240000 0x0 0x10000>; 657 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 clocks = <&bpmp TEGRA186_CLK_I2C2>; 661 clock-names = "div-clk"; 662 resets = <&bpmp TEGRA186_RESET_I2C2>; 663 reset-names = "i2c"; 664 status = "disabled"; 665 }; 666 667 gen8_i2c: i2c@c250000 { 668 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 669 reg = <0x0 0x0c250000 0x0 0x10000>; 670 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 clocks = <&bpmp TEGRA186_CLK_I2C8>; 674 clock-names = "div-clk"; 675 resets = <&bpmp TEGRA186_RESET_I2C8>; 676 reset-names = "i2c"; 677 status = "disabled"; 678 }; 679 680 uartc: serial@c280000 { 681 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 682 reg = <0x0 0x0c280000 0x0 0x40>; 683 reg-shift = <2>; 684 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&bpmp TEGRA186_CLK_UARTC>; 686 clock-names = "serial"; 687 resets = <&bpmp TEGRA186_RESET_UARTC>; 688 reset-names = "serial"; 689 status = "disabled"; 690 }; 691 692 uartg: serial@c290000 { 693 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 694 reg = <0x0 0x0c290000 0x0 0x40>; 695 reg-shift = <2>; 696 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&bpmp TEGRA186_CLK_UARTG>; 698 clock-names = "serial"; 699 resets = <&bpmp TEGRA186_RESET_UARTG>; 700 reset-names = "serial"; 701 status = "disabled"; 702 }; 703 704 rtc: rtc@c2a0000 { 705 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 706 reg = <0 0x0c2a0000 0 0x10000>; 707 interrupt-parent = <&pmc>; 708 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 710 clock-names = "rtc"; 711 status = "disabled"; 712 }; 713 714 gpio_aon: gpio@c2f0000 { 715 compatible = "nvidia,tegra186-gpio-aon"; 716 reg-names = "security", "gpio"; 717 reg = <0x0 0xc2f0000 0x0 0x1000>, 718 <0x0 0xc2f1000 0x0 0x1000>; 719 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 720 gpio-controller; 721 #gpio-cells = <2>; 722 interrupt-controller; 723 #interrupt-cells = <2>; 724 }; 725 726 pmc: pmc@c360000 { 727 compatible = "nvidia,tegra186-pmc"; 728 reg = <0 0x0c360000 0 0x10000>, 729 <0 0x0c370000 0 0x10000>, 730 <0 0x0c380000 0 0x10000>, 731 <0 0x0c390000 0 0x10000>; 732 reg-names = "pmc", "wake", "aotag", "scratch"; 733 734 #interrupt-cells = <2>; 735 interrupt-controller; 736 737 sdmmc1_3v3: sdmmc1-3v3 { 738 pins = "sdmmc1-hv"; 739 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 740 }; 741 742 sdmmc1_1v8: sdmmc1-1v8 { 743 pins = "sdmmc1-hv"; 744 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 745 }; 746 747 sdmmc2_3v3: sdmmc2-3v3 { 748 pins = "sdmmc2-hv"; 749 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 750 }; 751 752 sdmmc2_1v8: sdmmc2-1v8 { 753 pins = "sdmmc2-hv"; 754 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 755 }; 756 757 sdmmc3_3v3: sdmmc3-3v3 { 758 pins = "sdmmc3-hv"; 759 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 760 }; 761 762 sdmmc3_1v8: sdmmc3-1v8 { 763 pins = "sdmmc3-hv"; 764 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 765 }; 766 }; 767 768 ccplex@e000000 { 769 compatible = "nvidia,tegra186-ccplex-cluster"; 770 reg = <0x0 0x0e000000 0x0 0x3fffff>; 771 772 nvidia,bpmp = <&bpmp>; 773 }; 774 775 pcie@10003000 { 776 compatible = "nvidia,tegra186-pcie"; 777 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 778 device_type = "pci"; 779 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 780 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 781 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 782 reg-names = "pads", "afi", "cs"; 783 784 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 785 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 786 interrupt-names = "intr", "msi"; 787 788 #interrupt-cells = <1>; 789 interrupt-map-mask = <0 0 0 0>; 790 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 791 792 bus-range = <0x00 0xff>; 793 #address-cells = <3>; 794 #size-cells = <2>; 795 796 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 797 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 798 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 799 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 800 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 801 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 802 803 clocks = <&bpmp TEGRA186_CLK_AFI>, 804 <&bpmp TEGRA186_CLK_PCIE>, 805 <&bpmp TEGRA186_CLK_PLLE>; 806 clock-names = "afi", "pex", "pll_e"; 807 808 resets = <&bpmp TEGRA186_RESET_AFI>, 809 <&bpmp TEGRA186_RESET_PCIE>, 810 <&bpmp TEGRA186_RESET_PCIEXCLK>; 811 reset-names = "afi", "pex", "pcie_x"; 812 813 interconnects = <&mc TEGRA186_MEMORY_CLIENT_AFIR &emc>, 814 <&mc TEGRA186_MEMORY_CLIENT_AFIW &emc>; 815 interconnect-names = "dma-mem", "write"; 816 817 iommus = <&smmu TEGRA186_SID_AFI>; 818 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 819 iommu-map-mask = <0x0>; 820 821 status = "disabled"; 822 823 pci@1,0 { 824 device_type = "pci"; 825 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 826 reg = <0x000800 0 0 0 0>; 827 status = "disabled"; 828 829 #address-cells = <3>; 830 #size-cells = <2>; 831 ranges; 832 833 nvidia,num-lanes = <2>; 834 }; 835 836 pci@2,0 { 837 device_type = "pci"; 838 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 839 reg = <0x001000 0 0 0 0>; 840 status = "disabled"; 841 842 #address-cells = <3>; 843 #size-cells = <2>; 844 ranges; 845 846 nvidia,num-lanes = <1>; 847 }; 848 849 pci@3,0 { 850 device_type = "pci"; 851 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 852 reg = <0x001800 0 0 0 0>; 853 status = "disabled"; 854 855 #address-cells = <3>; 856 #size-cells = <2>; 857 ranges; 858 859 nvidia,num-lanes = <1>; 860 }; 861 }; 862 863 smmu: iommu@12000000 { 864 compatible = "arm,mmu-500"; 865 reg = <0 0x12000000 0 0x800000>; 866 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 931 stream-match-mask = <0x7f80>; 932 #global-interrupts = <1>; 933 #iommu-cells = <1>; 934 }; 935 936 host1x@13e00000 { 937 compatible = "nvidia,tegra186-host1x", "simple-bus"; 938 reg = <0x0 0x13e00000 0x0 0x10000>, 939 <0x0 0x13e10000 0x0 0x10000>; 940 reg-names = "hypervisor", "vm"; 941 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "syncpt", "host1x"; 944 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 945 clock-names = "host1x"; 946 resets = <&bpmp TEGRA186_RESET_HOST1X>; 947 reset-names = "host1x"; 948 949 #address-cells = <1>; 950 #size-cells = <1>; 951 952 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 953 954 interconnects = <&mc TEGRA186_MEMORY_CLIENT_HOST1XDMAR &emc>; 955 interconnect-names = "dma-mem"; 956 957 iommus = <&smmu TEGRA186_SID_HOST1X>; 958 959 dpaux1: dpaux@15040000 { 960 compatible = "nvidia,tegra186-dpaux"; 961 reg = <0x15040000 0x10000>; 962 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 964 <&bpmp TEGRA186_CLK_PLLDP>; 965 clock-names = "dpaux", "parent"; 966 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 967 reset-names = "dpaux"; 968 status = "disabled"; 969 970 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 971 972 state_dpaux1_aux: pinmux-aux { 973 groups = "dpaux-io"; 974 function = "aux"; 975 }; 976 977 state_dpaux1_i2c: pinmux-i2c { 978 groups = "dpaux-io"; 979 function = "i2c"; 980 }; 981 982 state_dpaux1_off: pinmux-off { 983 groups = "dpaux-io"; 984 function = "off"; 985 }; 986 987 i2c-bus { 988 #address-cells = <1>; 989 #size-cells = <0>; 990 }; 991 }; 992 993 display-hub@15200000 { 994 compatible = "nvidia,tegra186-display", "simple-bus"; 995 reg = <0x15200000 0x00040000>; 996 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 997 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 998 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 999 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 1000 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 1001 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 1002 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 1003 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1004 "wgrp3", "wgrp4", "wgrp5"; 1005 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 1006 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 1007 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 1008 clock-names = "disp", "dsc", "hub"; 1009 status = "disabled"; 1010 1011 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1012 1013 #address-cells = <1>; 1014 #size-cells = <1>; 1015 1016 ranges = <0x15200000 0x15200000 0x40000>; 1017 1018 display@15200000 { 1019 compatible = "nvidia,tegra186-dc"; 1020 reg = <0x15200000 0x10000>; 1021 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 1023 clock-names = "dc"; 1024 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 1025 reset-names = "dc"; 1026 1027 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1028 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1029 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1030 interconnect-names = "dma-mem", "read-1"; 1031 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1032 1033 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1034 nvidia,head = <0>; 1035 }; 1036 1037 display@15210000 { 1038 compatible = "nvidia,tegra186-dc"; 1039 reg = <0x15210000 0x10000>; 1040 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 1042 clock-names = "dc"; 1043 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 1044 reset-names = "dc"; 1045 1046 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 1047 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1048 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1049 interconnect-names = "dma-mem", "read-1"; 1050 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1051 1052 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 1053 nvidia,head = <1>; 1054 }; 1055 1056 display@15220000 { 1057 compatible = "nvidia,tegra186-dc"; 1058 reg = <0x15220000 0x10000>; 1059 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1061 clock-names = "dc"; 1062 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1063 reset-names = "dc"; 1064 1065 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1066 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>, 1067 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1068 interconnect-names = "dma-mem", "read-1"; 1069 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1070 1071 nvidia,outputs = <&sor0 &sor1>; 1072 nvidia,head = <2>; 1073 }; 1074 }; 1075 1076 dsia: dsi@15300000 { 1077 compatible = "nvidia,tegra186-dsi"; 1078 reg = <0x15300000 0x10000>; 1079 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&bpmp TEGRA186_CLK_DSI>, 1081 <&bpmp TEGRA186_CLK_DSIA_LP>, 1082 <&bpmp TEGRA186_CLK_PLLD>; 1083 clock-names = "dsi", "lp", "parent"; 1084 resets = <&bpmp TEGRA186_RESET_DSI>; 1085 reset-names = "dsi"; 1086 status = "disabled"; 1087 1088 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1089 }; 1090 1091 vic@15340000 { 1092 compatible = "nvidia,tegra186-vic"; 1093 reg = <0x15340000 0x40000>; 1094 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&bpmp TEGRA186_CLK_VIC>; 1096 clock-names = "vic"; 1097 resets = <&bpmp TEGRA186_RESET_VIC>; 1098 reset-names = "vic"; 1099 1100 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1101 interconnects = <&mc TEGRA186_MEMORY_CLIENT_VICSRD &emc>, 1102 <&mc TEGRA186_MEMORY_CLIENT_VICSWR &emc>; 1103 interconnect-names = "dma-mem", "write"; 1104 iommus = <&smmu TEGRA186_SID_VIC>; 1105 }; 1106 1107 dsib: dsi@15400000 { 1108 compatible = "nvidia,tegra186-dsi"; 1109 reg = <0x15400000 0x10000>; 1110 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1112 <&bpmp TEGRA186_CLK_DSIB_LP>, 1113 <&bpmp TEGRA186_CLK_PLLD>; 1114 clock-names = "dsi", "lp", "parent"; 1115 resets = <&bpmp TEGRA186_RESET_DSIB>; 1116 reset-names = "dsi"; 1117 status = "disabled"; 1118 1119 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1120 }; 1121 1122 sor0: sor@15540000 { 1123 compatible = "nvidia,tegra186-sor"; 1124 reg = <0x15540000 0x10000>; 1125 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1127 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1128 <&bpmp TEGRA186_CLK_PLLD2>, 1129 <&bpmp TEGRA186_CLK_PLLDP>, 1130 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1131 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1132 clock-names = "sor", "out", "parent", "dp", "safe", 1133 "pad"; 1134 resets = <&bpmp TEGRA186_RESET_SOR0>; 1135 reset-names = "sor"; 1136 pinctrl-0 = <&state_dpaux_aux>; 1137 pinctrl-1 = <&state_dpaux_i2c>; 1138 pinctrl-2 = <&state_dpaux_off>; 1139 pinctrl-names = "aux", "i2c", "off"; 1140 status = "disabled"; 1141 1142 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1143 nvidia,interface = <0>; 1144 }; 1145 1146 sor1: sor@15580000 { 1147 compatible = "nvidia,tegra186-sor"; 1148 reg = <0x15580000 0x10000>; 1149 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1150 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1151 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1152 <&bpmp TEGRA186_CLK_PLLD3>, 1153 <&bpmp TEGRA186_CLK_PLLDP>, 1154 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1155 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1156 clock-names = "sor", "out", "parent", "dp", "safe", 1157 "pad"; 1158 resets = <&bpmp TEGRA186_RESET_SOR1>; 1159 reset-names = "sor"; 1160 pinctrl-0 = <&state_dpaux1_aux>; 1161 pinctrl-1 = <&state_dpaux1_i2c>; 1162 pinctrl-2 = <&state_dpaux1_off>; 1163 pinctrl-names = "aux", "i2c", "off"; 1164 status = "disabled"; 1165 1166 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1167 nvidia,interface = <1>; 1168 }; 1169 1170 dpaux: dpaux@155c0000 { 1171 compatible = "nvidia,tegra186-dpaux"; 1172 reg = <0x155c0000 0x10000>; 1173 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1175 <&bpmp TEGRA186_CLK_PLLDP>; 1176 clock-names = "dpaux", "parent"; 1177 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1178 reset-names = "dpaux"; 1179 status = "disabled"; 1180 1181 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1182 1183 state_dpaux_aux: pinmux-aux { 1184 groups = "dpaux-io"; 1185 function = "aux"; 1186 }; 1187 1188 state_dpaux_i2c: pinmux-i2c { 1189 groups = "dpaux-io"; 1190 function = "i2c"; 1191 }; 1192 1193 state_dpaux_off: pinmux-off { 1194 groups = "dpaux-io"; 1195 function = "off"; 1196 }; 1197 1198 i2c-bus { 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 }; 1202 }; 1203 1204 padctl@15880000 { 1205 compatible = "nvidia,tegra186-dsi-padctl"; 1206 reg = <0x15880000 0x10000>; 1207 resets = <&bpmp TEGRA186_RESET_DSI>; 1208 reset-names = "dsi"; 1209 status = "disabled"; 1210 }; 1211 1212 dsic: dsi@15900000 { 1213 compatible = "nvidia,tegra186-dsi"; 1214 reg = <0x15900000 0x10000>; 1215 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1217 <&bpmp TEGRA186_CLK_DSIC_LP>, 1218 <&bpmp TEGRA186_CLK_PLLD>; 1219 clock-names = "dsi", "lp", "parent"; 1220 resets = <&bpmp TEGRA186_RESET_DSIC>; 1221 reset-names = "dsi"; 1222 status = "disabled"; 1223 1224 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1225 }; 1226 1227 dsid: dsi@15940000 { 1228 compatible = "nvidia,tegra186-dsi"; 1229 reg = <0x15940000 0x10000>; 1230 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&bpmp TEGRA186_CLK_DSID>, 1232 <&bpmp TEGRA186_CLK_DSID_LP>, 1233 <&bpmp TEGRA186_CLK_PLLD>; 1234 clock-names = "dsi", "lp", "parent"; 1235 resets = <&bpmp TEGRA186_RESET_DSID>; 1236 reset-names = "dsi"; 1237 status = "disabled"; 1238 1239 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1240 }; 1241 }; 1242 1243 gpu@17000000 { 1244 compatible = "nvidia,gp10b"; 1245 reg = <0x0 0x17000000 0x0 0x1000000>, 1246 <0x0 0x18000000 0x0 0x1000000>; 1247 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1249 interrupt-names = "stall", "nonstall"; 1250 1251 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1252 <&bpmp TEGRA186_CLK_GPU>; 1253 clock-names = "gpu", "pwr"; 1254 resets = <&bpmp TEGRA186_RESET_GPU>; 1255 reset-names = "gpu"; 1256 status = "disabled"; 1257 1258 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1259 interconnects = <&mc TEGRA186_MEMORY_CLIENT_GPUSRD &emc>, 1260 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR &emc>, 1261 <&mc TEGRA186_MEMORY_CLIENT_GPUSRD2 &emc>, 1262 <&mc TEGRA186_MEMORY_CLIENT_GPUSWR2 &emc>; 1263 interconnect-names = "dma-mem", "write-0", "read-1", "write-1"; 1264 }; 1265 1266 sysram@30000000 { 1267 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1268 reg = <0x0 0x30000000 0x0 0x50000>; 1269 #address-cells = <1>; 1270 #size-cells = <1>; 1271 ranges = <0x0 0x0 0x30000000 0x50000>; 1272 1273 cpu_bpmp_tx: shmem@4e000 { 1274 compatible = "nvidia,tegra186-bpmp-shmem"; 1275 reg = <0x4e000 0x1000>; 1276 label = "cpu-bpmp-tx"; 1277 pool; 1278 }; 1279 1280 cpu_bpmp_rx: shmem@4f000 { 1281 compatible = "nvidia,tegra186-bpmp-shmem"; 1282 reg = <0x4f000 0x1000>; 1283 label = "cpu-bpmp-rx"; 1284 pool; 1285 }; 1286 }; 1287 1288 bpmp: bpmp { 1289 compatible = "nvidia,tegra186-bpmp"; 1290 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, 1291 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, 1292 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, 1293 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; 1294 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1295 iommus = <&smmu TEGRA186_SID_BPMP>; 1296 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1297 TEGRA_HSP_DB_MASTER_BPMP>; 1298 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1299 #clock-cells = <1>; 1300 #reset-cells = <1>; 1301 #power-domain-cells = <1>; 1302 1303 bpmp_i2c: i2c { 1304 compatible = "nvidia,tegra186-bpmp-i2c"; 1305 nvidia,bpmp-bus-id = <5>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 status = "disabled"; 1309 }; 1310 1311 bpmp_thermal: thermal { 1312 compatible = "nvidia,tegra186-bpmp-thermal"; 1313 #thermal-sensor-cells = <1>; 1314 }; 1315 }; 1316 1317 cpus { 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 1321 cpu@0 { 1322 compatible = "nvidia,tegra186-denver"; 1323 device_type = "cpu"; 1324 i-cache-size = <0x20000>; 1325 i-cache-line-size = <64>; 1326 i-cache-sets = <512>; 1327 d-cache-size = <0x10000>; 1328 d-cache-line-size = <64>; 1329 d-cache-sets = <256>; 1330 next-level-cache = <&L2_DENVER>; 1331 reg = <0x000>; 1332 }; 1333 1334 cpu@1 { 1335 compatible = "nvidia,tegra186-denver"; 1336 device_type = "cpu"; 1337 i-cache-size = <0x20000>; 1338 i-cache-line-size = <64>; 1339 i-cache-sets = <512>; 1340 d-cache-size = <0x10000>; 1341 d-cache-line-size = <64>; 1342 d-cache-sets = <256>; 1343 next-level-cache = <&L2_DENVER>; 1344 reg = <0x001>; 1345 }; 1346 1347 cpu@2 { 1348 compatible = "arm,cortex-a57"; 1349 device_type = "cpu"; 1350 i-cache-size = <0xC000>; 1351 i-cache-line-size = <64>; 1352 i-cache-sets = <256>; 1353 d-cache-size = <0x8000>; 1354 d-cache-line-size = <64>; 1355 d-cache-sets = <256>; 1356 next-level-cache = <&L2_A57>; 1357 reg = <0x100>; 1358 }; 1359 1360 cpu@3 { 1361 compatible = "arm,cortex-a57"; 1362 device_type = "cpu"; 1363 i-cache-size = <0xC000>; 1364 i-cache-line-size = <64>; 1365 i-cache-sets = <256>; 1366 d-cache-size = <0x8000>; 1367 d-cache-line-size = <64>; 1368 d-cache-sets = <256>; 1369 next-level-cache = <&L2_A57>; 1370 reg = <0x101>; 1371 }; 1372 1373 cpu@4 { 1374 compatible = "arm,cortex-a57"; 1375 device_type = "cpu"; 1376 i-cache-size = <0xC000>; 1377 i-cache-line-size = <64>; 1378 i-cache-sets = <256>; 1379 d-cache-size = <0x8000>; 1380 d-cache-line-size = <64>; 1381 d-cache-sets = <256>; 1382 next-level-cache = <&L2_A57>; 1383 reg = <0x102>; 1384 }; 1385 1386 cpu@5 { 1387 compatible = "arm,cortex-a57"; 1388 device_type = "cpu"; 1389 i-cache-size = <0xC000>; 1390 i-cache-line-size = <64>; 1391 i-cache-sets = <256>; 1392 d-cache-size = <0x8000>; 1393 d-cache-line-size = <64>; 1394 d-cache-sets = <256>; 1395 next-level-cache = <&L2_A57>; 1396 reg = <0x103>; 1397 }; 1398 1399 L2_DENVER: l2-cache0 { 1400 compatible = "cache"; 1401 cache-unified; 1402 cache-level = <2>; 1403 cache-size = <0x200000>; 1404 cache-line-size = <64>; 1405 cache-sets = <2048>; 1406 }; 1407 1408 L2_A57: l2-cache1 { 1409 compatible = "cache"; 1410 cache-unified; 1411 cache-level = <2>; 1412 cache-size = <0x200000>; 1413 cache-line-size = <64>; 1414 cache-sets = <2048>; 1415 }; 1416 }; 1417 1418 thermal-zones { 1419 a57 { 1420 polling-delay = <0>; 1421 polling-delay-passive = <1000>; 1422 1423 thermal-sensors = 1424 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1425 1426 trips { 1427 critical { 1428 temperature = <101000>; 1429 hysteresis = <0>; 1430 type = "critical"; 1431 }; 1432 }; 1433 1434 cooling-maps { 1435 }; 1436 }; 1437 1438 denver { 1439 polling-delay = <0>; 1440 polling-delay-passive = <1000>; 1441 1442 thermal-sensors = 1443 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1444 1445 trips { 1446 critical { 1447 temperature = <101000>; 1448 hysteresis = <0>; 1449 type = "critical"; 1450 }; 1451 }; 1452 1453 cooling-maps { 1454 }; 1455 }; 1456 1457 gpu { 1458 polling-delay = <0>; 1459 polling-delay-passive = <1000>; 1460 1461 thermal-sensors = 1462 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1463 1464 trips { 1465 critical { 1466 temperature = <101000>; 1467 hysteresis = <0>; 1468 type = "critical"; 1469 }; 1470 }; 1471 1472 cooling-maps { 1473 }; 1474 }; 1475 1476 pll { 1477 polling-delay = <0>; 1478 polling-delay-passive = <1000>; 1479 1480 thermal-sensors = 1481 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1482 1483 trips { 1484 critical { 1485 temperature = <101000>; 1486 hysteresis = <0>; 1487 type = "critical"; 1488 }; 1489 }; 1490 1491 cooling-maps { 1492 }; 1493 }; 1494 1495 always_on { 1496 polling-delay = <0>; 1497 polling-delay-passive = <1000>; 1498 1499 thermal-sensors = 1500 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1501 1502 trips { 1503 critical { 1504 temperature = <101000>; 1505 hysteresis = <0>; 1506 type = "critical"; 1507 }; 1508 }; 1509 1510 cooling-maps { 1511 }; 1512 }; 1513 }; 1514 1515 timer { 1516 compatible = "arm,armv8-timer"; 1517 interrupts = <GIC_PPI 13 1518 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1519 <GIC_PPI 14 1520 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1521 <GIC_PPI 11 1522 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1523 <GIC_PPI 10 1524 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1525 interrupt-parent = <&gic>; 1526 always-on; 1527 }; 1528}; 1529