1#include <dt-bindings/gpio/tegra186-gpio.h> 2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/mailbox/tegra186-hsp.h> 4 5/ { 6 compatible = "nvidia,tegra186"; 7 interrupt-parent = <&gic>; 8 #address-cells = <2>; 9 #size-cells = <2>; 10 11 gpio: gpio@2200000 { 12 compatible = "nvidia,tegra186-gpio"; 13 reg-names = "security", "gpio"; 14 reg = <0x0 0x2200000 0x0 0x10000>, 15 <0x0 0x2210000 0x0 0x10000>; 16 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 17 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 18 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 19 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 20 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 22 #interrupt-cells = <2>; 23 interrupt-controller; 24 #gpio-cells = <2>; 25 gpio-controller; 26 }; 27 28 uarta: serial@3100000 { 29 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 30 reg = <0x0 0x03100000 0x0 0x40>; 31 reg-shift = <2>; 32 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 33 clocks = <&bpmp 55>; 34 clock-names = "serial"; 35 resets = <&bpmp 47>; 36 reset-names = "serial"; 37 status = "disabled"; 38 }; 39 40 uartb: serial@3110000 { 41 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 42 reg = <0x0 0x03110000 0x0 0x40>; 43 reg-shift = <2>; 44 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&bpmp 56>; 46 clock-names = "serial"; 47 resets = <&bpmp 48>; 48 reset-names = "serial"; 49 status = "disabled"; 50 }; 51 52 uartd: serial@3130000 { 53 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 54 reg = <0x0 0x03130000 0x0 0x40>; 55 reg-shift = <2>; 56 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 57 clocks = <&bpmp 77>; 58 clock-names = "serial"; 59 resets = <&bpmp 50>; 60 reset-names = "serial"; 61 status = "disabled"; 62 }; 63 64 uarte: serial@3140000 { 65 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 66 reg = <0x0 0x03140000 0x0 0x40>; 67 reg-shift = <2>; 68 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&bpmp 194>; 70 clock-names = "serial"; 71 resets = <&bpmp 132>; 72 reset-names = "serial"; 73 status = "disabled"; 74 }; 75 76 uartf: serial@3150000 { 77 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 78 reg = <0x0 0x03150000 0x0 0x40>; 79 reg-shift = <2>; 80 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 81 clocks = <&bpmp 195>; 82 clock-names = "serial"; 83 resets = <&bpmp 111>; 84 reset-names = "serial"; 85 status = "disabled"; 86 }; 87 88 gen1_i2c: i2c@3160000 { 89 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 90 reg = <0x0 0x03160000 0x0 0x10000>; 91 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 clocks = <&bpmp 47>; 95 clock-names = "div-clk"; 96 resets = <&bpmp 19>; 97 reset-names = "i2c"; 98 status = "disabled"; 99 }; 100 101 cam_i2c: i2c@3180000 { 102 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 103 reg = <0x0 0x03180000 0x0 0x10000>; 104 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 105 #address-cells = <1>; 106 #size-cells = <0>; 107 clocks = <&bpmp 75>; 108 clock-names = "div-clk"; 109 resets = <&bpmp 21>; 110 reset-names = "i2c"; 111 status = "disabled"; 112 }; 113 114 /* shares pads with dpaux1 */ 115 dp_aux_ch1_i2c: i2c@3190000 { 116 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 117 reg = <0x0 0x03190000 0x0 0x10000>; 118 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 119 #address-cells = <1>; 120 #size-cells = <0>; 121 clocks = <&bpmp 86>; 122 clock-names = "div-clk"; 123 resets = <&bpmp 22>; 124 reset-names = "i2c"; 125 status = "disabled"; 126 }; 127 128 /* controlled by BPMP, should not be enabled */ 129 pwr_i2c: i2c@31a0000 { 130 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 131 reg = <0x0 0x031a0000 0x0 0x10000>; 132 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 clocks = <&bpmp 48>; 136 clock-names = "div-clk"; 137 resets = <&bpmp 23>; 138 reset-names = "i2c"; 139 status = "disabled"; 140 }; 141 142 /* shares pads with dpaux0 */ 143 dp_aux_ch0_i2c: i2c@31b0000 { 144 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 145 reg = <0x0 0x031b0000 0x0 0x10000>; 146 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 clocks = <&bpmp 125>; 150 clock-names = "div-clk"; 151 resets = <&bpmp 24>; 152 reset-names = "i2c"; 153 status = "disabled"; 154 }; 155 156 gen7_i2c: i2c@31c0000 { 157 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 158 reg = <0x0 0x031c0000 0x0 0x10000>; 159 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 clocks = <&bpmp 182>; 163 clock-names = "div-clk"; 164 resets = <&bpmp 81>; 165 reset-names = "i2c"; 166 status = "disabled"; 167 }; 168 169 gen9_i2c: i2c@31e0000 { 170 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 171 reg = <0x0 0x031e0000 0x0 0x10000>; 172 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 clocks = <&bpmp 183>; 176 clock-names = "div-clk"; 177 resets = <&bpmp 83>; 178 reset-names = "i2c"; 179 status = "disabled"; 180 }; 181 182 sdmmc1: sdhci@3400000 { 183 compatible = "nvidia,tegra186-sdhci"; 184 reg = <0x0 0x03400000 0x0 0x10000>; 185 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&bpmp 52>; 187 clock-names = "sdhci"; 188 resets = <&bpmp 33>; 189 reset-names = "sdhci"; 190 status = "disabled"; 191 }; 192 193 sdmmc2: sdhci@3420000 { 194 compatible = "nvidia,tegra186-sdhci"; 195 reg = <0x0 0x03420000 0x0 0x10000>; 196 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&bpmp 53>; 198 clock-names = "sdhci"; 199 resets = <&bpmp 34>; 200 reset-names = "sdhci"; 201 status = "disabled"; 202 }; 203 204 sdmmc3: sdhci@3440000 { 205 compatible = "nvidia,tegra186-sdhci"; 206 reg = <0x0 0x03440000 0x0 0x10000>; 207 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&bpmp 76>; 209 clock-names = "sdhci"; 210 resets = <&bpmp 35>; 211 reset-names = "sdhci"; 212 status = "disabled"; 213 }; 214 215 sdmmc4: sdhci@3460000 { 216 compatible = "nvidia,tegra186-sdhci"; 217 reg = <0x0 0x03460000 0x0 0x10000>; 218 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&bpmp 54>; 220 clock-names = "sdhci"; 221 resets = <&bpmp 36>; 222 reset-names = "sdhci"; 223 status = "disabled"; 224 }; 225 226 gic: interrupt-controller@3881000 { 227 compatible = "arm,gic-400"; 228 #interrupt-cells = <3>; 229 interrupt-controller; 230 reg = <0x0 0x03881000 0x0 0x1000>, 231 <0x0 0x03882000 0x0 0x2000>; 232 interrupts = <GIC_PPI 9 233 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 234 interrupt-parent = <&gic>; 235 }; 236 237 hsp_top0: hsp@3c00000 { 238 compatible = "nvidia,tegra186-hsp"; 239 reg = <0x0 0x03c00000 0x0 0xa0000>; 240 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 241 interrupt-names = "doorbell"; 242 #mbox-cells = <2>; 243 status = "disabled"; 244 }; 245 246 gen2_i2c: i2c@c240000 { 247 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 248 reg = <0x0 0x0c240000 0x0 0x10000>; 249 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 clocks = <&bpmp 218>; 253 clock-names = "div-clk"; 254 resets = <&bpmp 20>; 255 reset-names = "i2c"; 256 status = "disabled"; 257 }; 258 259 gen8_i2c: i2c@c250000 { 260 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 261 reg = <0x0 0x0c250000 0x0 0x10000>; 262 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 clocks = <&bpmp 219>; 266 clock-names = "div-clk"; 267 resets = <&bpmp 82>; 268 reset-names = "i2c"; 269 status = "disabled"; 270 }; 271 272 uartc: serial@c280000 { 273 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 274 reg = <0x0 0x0c280000 0x0 0x40>; 275 reg-shift = <2>; 276 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&bpmp 215>; 278 clock-names = "serial"; 279 resets = <&bpmp 49>; 280 reset-names = "serial"; 281 status = "disabled"; 282 }; 283 284 uartg: serial@c290000 { 285 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 286 reg = <0x0 0x0c290000 0x0 0x40>; 287 reg-shift = <2>; 288 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&bpmp 216>; 290 clock-names = "serial"; 291 resets = <&bpmp 112>; 292 reset-names = "serial"; 293 status = "disabled"; 294 }; 295 296 gpio_aon: gpio@c2f0000 { 297 compatible = "nvidia,tegra186-gpio-aon"; 298 reg-names = "security", "gpio"; 299 reg = <0x0 0xc2f0000 0x0 0x1000>, 300 <0x0 0xc2f1000 0x0 0x1000>; 301 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 302 gpio-controller; 303 #gpio-cells = <2>; 304 interrupt-controller; 305 #interrupt-cells = <2>; 306 }; 307 308 sysram@30000000 { 309 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 310 reg = <0x0 0x30000000 0x0 0x50000>; 311 #address-cells = <2>; 312 #size-cells = <2>; 313 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 314 315 cpu_bpmp_tx: shmem@4e000 { 316 compatible = "nvidia,tegra186-bpmp-shmem"; 317 reg = <0x0 0x4e000 0x0 0x1000>; 318 label = "cpu-bpmp-tx"; 319 pool; 320 }; 321 322 cpu_bpmp_rx: shmem@4f000 { 323 compatible = "nvidia,tegra186-bpmp-shmem"; 324 reg = <0x0 0x4f000 0x0 0x1000>; 325 label = "cpu-bpmp-rx"; 326 pool; 327 }; 328 }; 329 330 cpus { 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 cpu@0 { 335 compatible = "nvidia,tegra186-denver", "arm,armv8"; 336 device_type = "cpu"; 337 reg = <0x000>; 338 }; 339 340 cpu@1 { 341 compatible = "nvidia,tegra186-denver", "arm,armv8"; 342 device_type = "cpu"; 343 reg = <0x001>; 344 }; 345 346 cpu@2 { 347 compatible = "arm,cortex-a57", "arm,armv8"; 348 device_type = "cpu"; 349 reg = <0x100>; 350 }; 351 352 cpu@3 { 353 compatible = "arm,cortex-a57", "arm,armv8"; 354 device_type = "cpu"; 355 reg = <0x101>; 356 }; 357 358 cpu@4 { 359 compatible = "arm,cortex-a57", "arm,armv8"; 360 device_type = "cpu"; 361 reg = <0x102>; 362 }; 363 364 cpu@5 { 365 compatible = "arm,cortex-a57", "arm,armv8"; 366 device_type = "cpu"; 367 reg = <0x103>; 368 }; 369 }; 370 371 bpmp: bpmp { 372 compatible = "nvidia,tegra186-bpmp"; 373 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 374 TEGRA_HSP_DB_MASTER_BPMP>; 375 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 376 #clock-cells = <1>; 377 #reset-cells = <1>; 378 379 bpmp_i2c: i2c { 380 compatible = "nvidia,tegra186-bpmp-i2c"; 381 nvidia,bpmp-bus-id = <5>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 status = "disabled"; 385 }; 386 }; 387 388 timer { 389 compatible = "arm,armv8-timer"; 390 interrupts = <GIC_PPI 13 391 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 392 <GIC_PPI 14 393 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 394 <GIC_PPI 11 395 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 396 <GIC_PPI 10 397 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 398 interrupt-parent = <&gic>; 399 }; 400}; 401