1#include <dt-bindings/interrupt-controller/arm-gic.h> 2 3/ { 4 compatible = "nvidia,tegra186"; 5 interrupt-parent = <&gic>; 6 #address-cells = <2>; 7 #size-cells = <2>; 8 9 uarta: serial@3100000 { 10 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 11 reg = <0x0 0x03100000 0x0 0x40>; 12 reg-shift = <2>; 13 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14 clocks = <&bpmp 55>; 15 clock-names = "serial"; 16 resets = <&bpmp 47>; 17 reset-names = "serial"; 18 status = "disabled"; 19 }; 20 21 uartb: serial@3110000 { 22 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 23 reg = <0x0 0x03110000 0x0 0x40>; 24 reg-shift = <2>; 25 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 26 clocks = <&bpmp 56>; 27 clock-names = "serial"; 28 resets = <&bpmp 48>; 29 reset-names = "serial"; 30 status = "disabled"; 31 }; 32 33 uartd: serial@3130000 { 34 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 35 reg = <0x0 0x03130000 0x0 0x40>; 36 reg-shift = <2>; 37 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 38 clocks = <&bpmp 77>; 39 clock-names = "serial"; 40 resets = <&bpmp 50>; 41 reset-names = "serial"; 42 status = "disabled"; 43 }; 44 45 uarte: serial@3140000 { 46 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 47 reg = <0x0 0x03140000 0x0 0x40>; 48 reg-shift = <2>; 49 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 50 clocks = <&bpmp 194>; 51 clock-names = "serial"; 52 resets = <&bpmp 132>; 53 reset-names = "serial"; 54 status = "disabled"; 55 }; 56 57 uartf: serial@3150000 { 58 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 59 reg = <0x0 0x03150000 0x0 0x40>; 60 reg-shift = <2>; 61 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 62 clocks = <&bpmp 195>; 63 clock-names = "serial"; 64 resets = <&bpmp 111>; 65 reset-names = "serial"; 66 status = "disabled"; 67 }; 68 69 gic: interrupt-controller@3881000 { 70 compatible = "arm,gic-400"; 71 #interrupt-cells = <3>; 72 interrupt-controller; 73 reg = <0x0 0x03881000 0x0 0x1000>, 74 <0x0 0x03882000 0x0 0x2000>; 75 interrupts = <GIC_PPI 9 76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 77 interrupt-parent = <&gic>; 78 }; 79 80 hsp_top0: hsp@3c00000 { 81 compatible = "nvidia,tegra186-hsp"; 82 reg = <0x0 0x03c00000 0x0 0xa0000>; 83 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-names = "doorbell"; 85 #mbox-cells = <2>; 86 status = "disabled"; 87 }; 88 89 uartc: serial@c280000 { 90 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 91 reg = <0x0 0x0c280000 0x0 0x40>; 92 reg-shift = <2>; 93 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&bpmp 215>; 95 clock-names = "serial"; 96 resets = <&bpmp 49>; 97 reset-names = "serial"; 98 status = "disabled"; 99 }; 100 101 uartg: serial@c290000 { 102 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 103 reg = <0x0 0x0c290000 0x0 0x40>; 104 reg-shift = <2>; 105 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 106 clocks = <&bpmp 216>; 107 clock-names = "serial"; 108 resets = <&bpmp 112>; 109 reset-names = "serial"; 110 status = "disabled"; 111 }; 112 113 sysram@30000000 { 114 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 115 reg = <0x0 0x30000000 0x0 0x50000>; 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 119 120 cpu_bpmp_tx: shmem@4e000 { 121 compatible = "nvidia,tegra186-bpmp-shmem"; 122 reg = <0x0 0x4e000 0x0 0x1000>; 123 label = "cpu-bpmp-tx"; 124 pool; 125 }; 126 127 cpu_bpmp_rx: shmem@4f000 { 128 compatible = "nvidia,tegra186-bpmp-shmem"; 129 reg = <0x0 0x4f000 0x0 0x1000>; 130 label = "cpu-bpmp-rx"; 131 pool; 132 }; 133 }; 134 135 cpus { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 cpu@0 { 140 compatible = "nvidia,tegra186-denver", "arm,armv8"; 141 device_type = "cpu"; 142 reg = <0x000>; 143 }; 144 145 cpu@1 { 146 compatible = "nvidia,tegra186-denver", "arm,armv8"; 147 device_type = "cpu"; 148 reg = <0x001>; 149 }; 150 151 cpu@2 { 152 compatible = "arm,cortex-a57", "arm,armv8"; 153 device_type = "cpu"; 154 reg = <0x100>; 155 }; 156 157 cpu@3 { 158 compatible = "arm,cortex-a57", "arm,armv8"; 159 device_type = "cpu"; 160 reg = <0x101>; 161 }; 162 163 cpu@4 { 164 compatible = "arm,cortex-a57", "arm,armv8"; 165 device_type = "cpu"; 166 reg = <0x102>; 167 }; 168 169 cpu@5 { 170 compatible = "arm,cortex-a57", "arm,armv8"; 171 device_type = "cpu"; 172 reg = <0x103>; 173 }; 174 }; 175 176 bpmp: bpmp { 177 compatible = "nvidia,tegra186-bpmp"; 178 mboxes = <&hsp_top0 0 19>; 179 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 180 #clock-cells = <1>; 181 #reset-cells = <1>; 182 183 bpmp_i2c: i2c { 184 compatible = "nvidia,tegra186-bpmp-i2c"; 185 nvidia,bpmp-bus-id = <5>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 status = "disabled"; 189 }; 190 }; 191 192 timer { 193 compatible = "arm,armv8-timer"; 194 interrupts = <GIC_PPI 13 195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 196 <GIC_PPI 14 197 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 198 <GIC_PPI 11 199 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 10 201 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 202 interrupt-parent = <&gic>; 203 }; 204}; 205