1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra186-clock.h> 3#include <dt-bindings/gpio/tegra186-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/memory/tegra186-mc.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 8#include <dt-bindings/power/tegra186-powergate.h> 9#include <dt-bindings/reset/tegra186-reset.h> 10#include <dt-bindings/thermal/tegra186-bpmp-thermal.h> 11 12/ { 13 compatible = "nvidia,tegra186"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 misc@100000 { 19 compatible = "nvidia,tegra186-misc"; 20 reg = <0x0 0x00100000 0x0 0xf000>, 21 <0x0 0x0010f000 0x0 0x1000>; 22 }; 23 24 gpio: gpio@2200000 { 25 compatible = "nvidia,tegra186-gpio"; 26 reg-names = "security", "gpio"; 27 reg = <0x0 0x2200000 0x0 0x10000>, 28 <0x0 0x2210000 0x0 0x10000>; 29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 35 #interrupt-cells = <2>; 36 interrupt-controller; 37 #gpio-cells = <2>; 38 gpio-controller; 39 }; 40 41 ethernet@2490000 { 42 compatible = "nvidia,tegra186-eqos", 43 "snps,dwc-qos-ethernet-4.10"; 44 reg = <0x0 0x02490000 0x0 0x10000>; 45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ 46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ 47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ 48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ 49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ 50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ 51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ 52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ 53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ 54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ 55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 56 <&bpmp TEGRA186_CLK_EQOS_AXI>, 57 <&bpmp TEGRA186_CLK_EQOS_RX>, 58 <&bpmp TEGRA186_CLK_EQOS_TX>, 59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; 60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 61 resets = <&bpmp TEGRA186_RESET_EQOS>; 62 reset-names = "eqos"; 63 iommus = <&smmu TEGRA186_SID_EQOS>; 64 status = "disabled"; 65 66 snps,write-requests = <1>; 67 snps,read-requests = <3>; 68 snps,burst-map = <0x7>; 69 snps,txpbl = <32>; 70 snps,rxpbl = <8>; 71 }; 72 73 aconnect { 74 compatible = "nvidia,tegra186-aconnect", 75 "nvidia,tegra210-aconnect"; 76 clocks = <&bpmp TEGRA186_CLK_APE>, 77 <&bpmp TEGRA186_CLK_APB2APE>; 78 clock-names = "ape", "apb2ape"; 79 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 ranges = <0x02900000 0x0 0x02900000 0x200000>; 83 status = "disabled"; 84 85 dma-controller@2930000 { 86 compatible = "nvidia,tegra186-adma"; 87 reg = <0x02930000 0x20000>; 88 interrupt-parent = <&agic>; 89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 121 #dma-cells = <1>; 122 clocks = <&bpmp TEGRA186_CLK_AHUB>; 123 clock-names = "d_audio"; 124 status = "disabled"; 125 }; 126 127 agic: interrupt-controller@2a40000 { 128 compatible = "nvidia,tegra186-agic", 129 "nvidia,tegra210-agic"; 130 #interrupt-cells = <3>; 131 interrupt-controller; 132 reg = <0x02a41000 0x1000>, 133 <0x02a42000 0x2000>; 134 interrupts = <GIC_SPI 145 135 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 136 clocks = <&bpmp TEGRA186_CLK_APE>; 137 clock-names = "clk"; 138 status = "disabled"; 139 }; 140 }; 141 142 memory-controller@2c00000 { 143 compatible = "nvidia,tegra186-mc"; 144 reg = <0x0 0x02c00000 0x0 0xb0000>; 145 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 146 status = "disabled"; 147 148 #address-cells = <2>; 149 #size-cells = <2>; 150 151 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; 152 153 /* 154 * Memory clients have access to all 40 bits that the memory 155 * controller can address. 156 */ 157 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 158 159 emc: external-memory-controller@2c60000 { 160 compatible = "nvidia,tegra186-emc"; 161 reg = <0x0 0x02c60000 0x0 0x50000>; 162 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&bpmp TEGRA186_CLK_EMC>; 164 clock-names = "emc"; 165 166 nvidia,bpmp = <&bpmp>; 167 }; 168 }; 169 170 uarta: serial@3100000 { 171 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 172 reg = <0x0 0x03100000 0x0 0x40>; 173 reg-shift = <2>; 174 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&bpmp TEGRA186_CLK_UARTA>; 176 clock-names = "serial"; 177 resets = <&bpmp TEGRA186_RESET_UARTA>; 178 reset-names = "serial"; 179 status = "disabled"; 180 }; 181 182 uartb: serial@3110000 { 183 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 184 reg = <0x0 0x03110000 0x0 0x40>; 185 reg-shift = <2>; 186 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&bpmp TEGRA186_CLK_UARTB>; 188 clock-names = "serial"; 189 resets = <&bpmp TEGRA186_RESET_UARTB>; 190 reset-names = "serial"; 191 status = "disabled"; 192 }; 193 194 uartd: serial@3130000 { 195 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 196 reg = <0x0 0x03130000 0x0 0x40>; 197 reg-shift = <2>; 198 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&bpmp TEGRA186_CLK_UARTD>; 200 clock-names = "serial"; 201 resets = <&bpmp TEGRA186_RESET_UARTD>; 202 reset-names = "serial"; 203 status = "disabled"; 204 }; 205 206 uarte: serial@3140000 { 207 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 208 reg = <0x0 0x03140000 0x0 0x40>; 209 reg-shift = <2>; 210 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&bpmp TEGRA186_CLK_UARTE>; 212 clock-names = "serial"; 213 resets = <&bpmp TEGRA186_RESET_UARTE>; 214 reset-names = "serial"; 215 status = "disabled"; 216 }; 217 218 uartf: serial@3150000 { 219 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 220 reg = <0x0 0x03150000 0x0 0x40>; 221 reg-shift = <2>; 222 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&bpmp TEGRA186_CLK_UARTF>; 224 clock-names = "serial"; 225 resets = <&bpmp TEGRA186_RESET_UARTF>; 226 reset-names = "serial"; 227 status = "disabled"; 228 }; 229 230 gen1_i2c: i2c@3160000 { 231 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 232 reg = <0x0 0x03160000 0x0 0x10000>; 233 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 clocks = <&bpmp TEGRA186_CLK_I2C1>; 237 clock-names = "div-clk"; 238 resets = <&bpmp TEGRA186_RESET_I2C1>; 239 reset-names = "i2c"; 240 status = "disabled"; 241 }; 242 243 cam_i2c: i2c@3180000 { 244 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 245 reg = <0x0 0x03180000 0x0 0x10000>; 246 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 clocks = <&bpmp TEGRA186_CLK_I2C3>; 250 clock-names = "div-clk"; 251 resets = <&bpmp TEGRA186_RESET_I2C3>; 252 reset-names = "i2c"; 253 status = "disabled"; 254 }; 255 256 /* shares pads with dpaux1 */ 257 dp_aux_ch1_i2c: i2c@3190000 { 258 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 259 reg = <0x0 0x03190000 0x0 0x10000>; 260 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 clocks = <&bpmp TEGRA186_CLK_I2C4>; 264 clock-names = "div-clk"; 265 resets = <&bpmp TEGRA186_RESET_I2C4>; 266 reset-names = "i2c"; 267 pinctrl-names = "default", "idle"; 268 pinctrl-0 = <&state_dpaux1_i2c>; 269 pinctrl-1 = <&state_dpaux1_off>; 270 status = "disabled"; 271 }; 272 273 /* controlled by BPMP, should not be enabled */ 274 pwr_i2c: i2c@31a0000 { 275 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 276 reg = <0x0 0x031a0000 0x0 0x10000>; 277 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 clocks = <&bpmp TEGRA186_CLK_I2C5>; 281 clock-names = "div-clk"; 282 resets = <&bpmp TEGRA186_RESET_I2C5>; 283 reset-names = "i2c"; 284 status = "disabled"; 285 }; 286 287 /* shares pads with dpaux0 */ 288 dp_aux_ch0_i2c: i2c@31b0000 { 289 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 290 reg = <0x0 0x031b0000 0x0 0x10000>; 291 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 clocks = <&bpmp TEGRA186_CLK_I2C6>; 295 clock-names = "div-clk"; 296 resets = <&bpmp TEGRA186_RESET_I2C6>; 297 reset-names = "i2c"; 298 pinctrl-names = "default", "idle"; 299 pinctrl-0 = <&state_dpaux_i2c>; 300 pinctrl-1 = <&state_dpaux_off>; 301 status = "disabled"; 302 }; 303 304 gen7_i2c: i2c@31c0000 { 305 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 306 reg = <0x0 0x031c0000 0x0 0x10000>; 307 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 clocks = <&bpmp TEGRA186_CLK_I2C7>; 311 clock-names = "div-clk"; 312 resets = <&bpmp TEGRA186_RESET_I2C7>; 313 reset-names = "i2c"; 314 status = "disabled"; 315 }; 316 317 gen9_i2c: i2c@31e0000 { 318 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 319 reg = <0x0 0x031e0000 0x0 0x10000>; 320 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 clocks = <&bpmp TEGRA186_CLK_I2C9>; 324 clock-names = "div-clk"; 325 resets = <&bpmp TEGRA186_RESET_I2C9>; 326 reset-names = "i2c"; 327 status = "disabled"; 328 }; 329 330 sdmmc1: sdhci@3400000 { 331 compatible = "nvidia,tegra186-sdhci"; 332 reg = <0x0 0x03400000 0x0 0x10000>; 333 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 335 clock-names = "sdhci"; 336 resets = <&bpmp TEGRA186_RESET_SDMMC1>; 337 reset-names = "sdhci"; 338 iommus = <&smmu TEGRA186_SID_SDMMC1>; 339 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 340 pinctrl-0 = <&sdmmc1_3v3>; 341 pinctrl-1 = <&sdmmc1_1v8>; 342 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 343 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 344 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 345 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 346 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>; 347 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>; 348 nvidia,default-tap = <0x5>; 349 nvidia,default-trim = <0xb>; 350 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>, 351 <&bpmp TEGRA186_CLK_PLLP_OUT0>; 352 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; 353 status = "disabled"; 354 }; 355 356 sdmmc2: sdhci@3420000 { 357 compatible = "nvidia,tegra186-sdhci"; 358 reg = <0x0 0x03420000 0x0 0x10000>; 359 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&bpmp TEGRA186_CLK_SDMMC2>; 361 clock-names = "sdhci"; 362 resets = <&bpmp TEGRA186_RESET_SDMMC2>; 363 reset-names = "sdhci"; 364 iommus = <&smmu TEGRA186_SID_SDMMC2>; 365 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 366 pinctrl-0 = <&sdmmc2_3v3>; 367 pinctrl-1 = <&sdmmc2_1v8>; 368 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 369 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 370 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 371 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 372 nvidia,default-tap = <0x5>; 373 nvidia,default-trim = <0xb>; 374 status = "disabled"; 375 }; 376 377 sdmmc3: sdhci@3440000 { 378 compatible = "nvidia,tegra186-sdhci"; 379 reg = <0x0 0x03440000 0x0 0x10000>; 380 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&bpmp TEGRA186_CLK_SDMMC3>; 382 clock-names = "sdhci"; 383 resets = <&bpmp TEGRA186_RESET_SDMMC3>; 384 reset-names = "sdhci"; 385 iommus = <&smmu TEGRA186_SID_SDMMC3>; 386 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 387 pinctrl-0 = <&sdmmc3_3v3>; 388 pinctrl-1 = <&sdmmc3_1v8>; 389 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 390 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 391 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 392 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>; 393 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>; 394 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 395 nvidia,default-tap = <0x5>; 396 nvidia,default-trim = <0xb>; 397 status = "disabled"; 398 }; 399 400 sdmmc4: sdhci@3460000 { 401 compatible = "nvidia,tegra186-sdhci"; 402 reg = <0x0 0x03460000 0x0 0x10000>; 403 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 405 clock-names = "sdhci"; 406 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>, 407 <&bpmp TEGRA186_CLK_PLLC4_VCO>; 408 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>; 409 resets = <&bpmp TEGRA186_RESET_SDMMC4>; 410 reset-names = "sdhci"; 411 iommus = <&smmu TEGRA186_SID_SDMMC4>; 412 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>; 413 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>; 414 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 415 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 416 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 417 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 418 nvidia,default-tap = <0x9>; 419 nvidia,default-trim = <0x5>; 420 nvidia,dqs-trim = <63>; 421 mmc-hs400-1_8v; 422 supports-cqe; 423 status = "disabled"; 424 }; 425 426 hda@3510000 { 427 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda"; 428 reg = <0x0 0x03510000 0x0 0x10000>; 429 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&bpmp TEGRA186_CLK_HDA>, 431 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>, 432 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>; 433 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 434 resets = <&bpmp TEGRA186_RESET_HDA>, 435 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>, 436 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>; 437 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 438 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 439 iommus = <&smmu TEGRA186_SID_HDA>; 440 status = "disabled"; 441 }; 442 443 padctl: padctl@3520000 { 444 compatible = "nvidia,tegra186-xusb-padctl"; 445 reg = <0x0 0x03520000 0x0 0x1000>, 446 <0x0 0x03540000 0x0 0x1000>; 447 reg-names = "padctl", "ao"; 448 449 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>; 450 reset-names = "padctl"; 451 452 status = "disabled"; 453 454 pads { 455 usb2 { 456 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>; 457 clock-names = "trk"; 458 status = "disabled"; 459 460 lanes { 461 usb2-0 { 462 status = "disabled"; 463 #phy-cells = <0>; 464 }; 465 466 usb2-1 { 467 status = "disabled"; 468 #phy-cells = <0>; 469 }; 470 471 usb2-2 { 472 status = "disabled"; 473 #phy-cells = <0>; 474 }; 475 }; 476 }; 477 478 hsic { 479 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>; 480 clock-names = "trk"; 481 status = "disabled"; 482 483 lanes { 484 hsic-0 { 485 status = "disabled"; 486 #phy-cells = <0>; 487 }; 488 }; 489 }; 490 491 usb3 { 492 status = "disabled"; 493 494 lanes { 495 usb3-0 { 496 status = "disabled"; 497 #phy-cells = <0>; 498 }; 499 500 usb3-1 { 501 status = "disabled"; 502 #phy-cells = <0>; 503 }; 504 505 usb3-2 { 506 status = "disabled"; 507 #phy-cells = <0>; 508 }; 509 }; 510 }; 511 }; 512 513 ports { 514 usb2-0 { 515 status = "disabled"; 516 }; 517 518 usb2-1 { 519 status = "disabled"; 520 }; 521 522 usb2-2 { 523 status = "disabled"; 524 }; 525 526 hsic-0 { 527 status = "disabled"; 528 }; 529 530 usb3-0 { 531 status = "disabled"; 532 }; 533 534 usb3-1 { 535 status = "disabled"; 536 }; 537 538 usb3-2 { 539 status = "disabled"; 540 }; 541 }; 542 }; 543 544 usb@3530000 { 545 compatible = "nvidia,tegra186-xusb"; 546 reg = <0x0 0x03530000 0x0 0x8000>, 547 <0x0 0x03538000 0x0 0x1000>; 548 reg-names = "hcd", "fpci"; 549 550 iommus = <&smmu TEGRA186_SID_XUSB_HOST>; 551 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 554 555 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, 556 <&bpmp TEGRA186_CLK_XUSB_FALCON>, 557 <&bpmp TEGRA186_CLK_XUSB_SS>, 558 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, 559 <&bpmp TEGRA186_CLK_CLK_M>, 560 <&bpmp TEGRA186_CLK_XUSB_FS>, 561 <&bpmp TEGRA186_CLK_PLLU>, 562 <&bpmp TEGRA186_CLK_CLK_M>, 563 <&bpmp TEGRA186_CLK_PLLE>; 564 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", 565 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", 566 "pll_u_480m", "clk_m", "pll_e"; 567 568 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, 569 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; 570 power-domain-names = "xusb_host", "xusb_ss"; 571 nvidia,xusb-padctl = <&padctl>; 572 573 status = "disabled"; 574 575 #address-cells = <1>; 576 #size-cells = <0>; 577 }; 578 579 fuse@3820000 { 580 compatible = "nvidia,tegra186-efuse"; 581 reg = <0x0 0x03820000 0x0 0x10000>; 582 clocks = <&bpmp TEGRA186_CLK_FUSE>; 583 clock-names = "fuse"; 584 }; 585 586 gic: interrupt-controller@3881000 { 587 compatible = "arm,gic-400"; 588 #interrupt-cells = <3>; 589 interrupt-controller; 590 reg = <0x0 0x03881000 0x0 0x1000>, 591 <0x0 0x03882000 0x0 0x2000>; 592 interrupts = <GIC_PPI 9 593 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 594 interrupt-parent = <&gic>; 595 }; 596 597 cec@3960000 { 598 compatible = "nvidia,tegra186-cec"; 599 reg = <0x0 0x03960000 0x0 0x10000>; 600 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&bpmp TEGRA186_CLK_CEC>; 602 clock-names = "cec"; 603 status = "disabled"; 604 }; 605 606 hsp_top0: hsp@3c00000 { 607 compatible = "nvidia,tegra186-hsp"; 608 reg = <0x0 0x03c00000 0x0 0xa0000>; 609 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 610 interrupt-names = "doorbell"; 611 #mbox-cells = <2>; 612 status = "disabled"; 613 }; 614 615 gen2_i2c: i2c@c240000 { 616 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 617 reg = <0x0 0x0c240000 0x0 0x10000>; 618 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 clocks = <&bpmp TEGRA186_CLK_I2C2>; 622 clock-names = "div-clk"; 623 resets = <&bpmp TEGRA186_RESET_I2C2>; 624 reset-names = "i2c"; 625 status = "disabled"; 626 }; 627 628 gen8_i2c: i2c@c250000 { 629 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c"; 630 reg = <0x0 0x0c250000 0x0 0x10000>; 631 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 clocks = <&bpmp TEGRA186_CLK_I2C8>; 635 clock-names = "div-clk"; 636 resets = <&bpmp TEGRA186_RESET_I2C8>; 637 reset-names = "i2c"; 638 status = "disabled"; 639 }; 640 641 uartc: serial@c280000 { 642 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 643 reg = <0x0 0x0c280000 0x0 0x40>; 644 reg-shift = <2>; 645 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&bpmp TEGRA186_CLK_UARTC>; 647 clock-names = "serial"; 648 resets = <&bpmp TEGRA186_RESET_UARTC>; 649 reset-names = "serial"; 650 status = "disabled"; 651 }; 652 653 uartg: serial@c290000 { 654 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 655 reg = <0x0 0x0c290000 0x0 0x40>; 656 reg-shift = <2>; 657 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&bpmp TEGRA186_CLK_UARTG>; 659 clock-names = "serial"; 660 resets = <&bpmp TEGRA186_RESET_UARTG>; 661 reset-names = "serial"; 662 status = "disabled"; 663 }; 664 665 rtc: rtc@c2a0000 { 666 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc"; 667 reg = <0 0x0c2a0000 0 0x10000>; 668 interrupt-parent = <&pmc>; 669 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&bpmp TEGRA186_CLK_CLK_32K>; 671 clock-names = "rtc"; 672 status = "disabled"; 673 }; 674 675 gpio_aon: gpio@c2f0000 { 676 compatible = "nvidia,tegra186-gpio-aon"; 677 reg-names = "security", "gpio"; 678 reg = <0x0 0xc2f0000 0x0 0x1000>, 679 <0x0 0xc2f1000 0x0 0x1000>; 680 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 681 gpio-controller; 682 #gpio-cells = <2>; 683 interrupt-controller; 684 #interrupt-cells = <2>; 685 }; 686 687 pmc: pmc@c360000 { 688 compatible = "nvidia,tegra186-pmc"; 689 reg = <0 0x0c360000 0 0x10000>, 690 <0 0x0c370000 0 0x10000>, 691 <0 0x0c380000 0 0x10000>, 692 <0 0x0c390000 0 0x10000>; 693 reg-names = "pmc", "wake", "aotag", "scratch"; 694 695 #interrupt-cells = <2>; 696 interrupt-controller; 697 698 sdmmc1_3v3: sdmmc1-3v3 { 699 pins = "sdmmc1-hv"; 700 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 701 }; 702 703 sdmmc1_1v8: sdmmc1-1v8 { 704 pins = "sdmmc1-hv"; 705 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 706 }; 707 708 sdmmc2_3v3: sdmmc2-3v3 { 709 pins = "sdmmc2-hv"; 710 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 711 }; 712 713 sdmmc2_1v8: sdmmc2-1v8 { 714 pins = "sdmmc2-hv"; 715 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 716 }; 717 718 sdmmc3_3v3: sdmmc3-3v3 { 719 pins = "sdmmc3-hv"; 720 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 721 }; 722 723 sdmmc3_1v8: sdmmc3-1v8 { 724 pins = "sdmmc3-hv"; 725 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 726 }; 727 }; 728 729 ccplex@e000000 { 730 compatible = "nvidia,tegra186-ccplex-cluster"; 731 reg = <0x0 0x0e000000 0x0 0x3fffff>; 732 733 nvidia,bpmp = <&bpmp>; 734 }; 735 736 pcie@10003000 { 737 compatible = "nvidia,tegra186-pcie"; 738 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 739 device_type = "pci"; 740 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 741 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 742 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 743 reg-names = "pads", "afi", "cs"; 744 745 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 746 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 747 interrupt-names = "intr", "msi"; 748 749 #interrupt-cells = <1>; 750 interrupt-map-mask = <0 0 0 0>; 751 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 752 753 bus-range = <0x00 0xff>; 754 #address-cells = <3>; 755 #size-cells = <2>; 756 757 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 758 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 759 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 760 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 761 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ 762 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 763 764 clocks = <&bpmp TEGRA186_CLK_AFI>, 765 <&bpmp TEGRA186_CLK_PCIE>, 766 <&bpmp TEGRA186_CLK_PLLE>; 767 clock-names = "afi", "pex", "pll_e"; 768 769 resets = <&bpmp TEGRA186_RESET_AFI>, 770 <&bpmp TEGRA186_RESET_PCIE>, 771 <&bpmp TEGRA186_RESET_PCIEXCLK>; 772 reset-names = "afi", "pex", "pcie_x"; 773 774 iommus = <&smmu TEGRA186_SID_AFI>; 775 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>; 776 iommu-map-mask = <0x0>; 777 778 status = "disabled"; 779 780 pci@1,0 { 781 device_type = "pci"; 782 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 783 reg = <0x000800 0 0 0 0>; 784 status = "disabled"; 785 786 #address-cells = <3>; 787 #size-cells = <2>; 788 ranges; 789 790 nvidia,num-lanes = <2>; 791 }; 792 793 pci@2,0 { 794 device_type = "pci"; 795 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 796 reg = <0x001000 0 0 0 0>; 797 status = "disabled"; 798 799 #address-cells = <3>; 800 #size-cells = <2>; 801 ranges; 802 803 nvidia,num-lanes = <1>; 804 }; 805 806 pci@3,0 { 807 device_type = "pci"; 808 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 809 reg = <0x001800 0 0 0 0>; 810 status = "disabled"; 811 812 #address-cells = <3>; 813 #size-cells = <2>; 814 ranges; 815 816 nvidia,num-lanes = <1>; 817 }; 818 }; 819 820 smmu: iommu@12000000 { 821 compatible = "arm,mmu-500"; 822 reg = <0 0x12000000 0 0x800000>; 823 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 888 stream-match-mask = <0x7f80>; 889 #global-interrupts = <1>; 890 #iommu-cells = <1>; 891 }; 892 893 host1x@13e00000 { 894 compatible = "nvidia,tegra186-host1x", "simple-bus"; 895 reg = <0x0 0x13e00000 0x0 0x10000>, 896 <0x0 0x13e10000 0x0 0x10000>; 897 reg-names = "hypervisor", "vm"; 898 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&bpmp TEGRA186_CLK_HOST1X>; 901 clock-names = "host1x"; 902 resets = <&bpmp TEGRA186_RESET_HOST1X>; 903 reset-names = "host1x"; 904 905 #address-cells = <1>; 906 #size-cells = <1>; 907 908 ranges = <0x15000000 0x0 0x15000000 0x01000000>; 909 iommus = <&smmu TEGRA186_SID_HOST1X>; 910 911 dpaux1: dpaux@15040000 { 912 compatible = "nvidia,tegra186-dpaux"; 913 reg = <0x15040000 0x10000>; 914 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&bpmp TEGRA186_CLK_DPAUX1>, 916 <&bpmp TEGRA186_CLK_PLLDP>; 917 clock-names = "dpaux", "parent"; 918 resets = <&bpmp TEGRA186_RESET_DPAUX1>; 919 reset-names = "dpaux"; 920 status = "disabled"; 921 922 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 923 924 state_dpaux1_aux: pinmux-aux { 925 groups = "dpaux-io"; 926 function = "aux"; 927 }; 928 929 state_dpaux1_i2c: pinmux-i2c { 930 groups = "dpaux-io"; 931 function = "i2c"; 932 }; 933 934 state_dpaux1_off: pinmux-off { 935 groups = "dpaux-io"; 936 function = "off"; 937 }; 938 939 i2c-bus { 940 #address-cells = <1>; 941 #size-cells = <0>; 942 }; 943 }; 944 945 display-hub@15200000 { 946 compatible = "nvidia,tegra186-display", "simple-bus"; 947 reg = <0x15200000 0x00040000>; 948 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, 949 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, 950 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, 951 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, 952 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, 953 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, 954 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; 955 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 956 "wgrp3", "wgrp4", "wgrp5"; 957 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, 958 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, 959 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; 960 clock-names = "disp", "dsc", "hub"; 961 status = "disabled"; 962 963 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 964 965 #address-cells = <1>; 966 #size-cells = <1>; 967 968 ranges = <0x15200000 0x15200000 0x40000>; 969 970 display@15200000 { 971 compatible = "nvidia,tegra186-dc"; 972 reg = <0x15200000 0x10000>; 973 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; 975 clock-names = "dc"; 976 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; 977 reset-names = "dc"; 978 979 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 980 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 981 982 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 983 nvidia,head = <0>; 984 }; 985 986 display@15210000 { 987 compatible = "nvidia,tegra186-dc"; 988 reg = <0x15210000 0x10000>; 989 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; 991 clock-names = "dc"; 992 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; 993 reset-names = "dc"; 994 995 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; 996 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 997 998 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 999 nvidia,head = <1>; 1000 }; 1001 1002 display@15220000 { 1003 compatible = "nvidia,tegra186-dc"; 1004 reg = <0x15220000 0x10000>; 1005 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; 1007 clock-names = "dc"; 1008 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; 1009 reset-names = "dc"; 1010 1011 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; 1012 iommus = <&smmu TEGRA186_SID_NVDISPLAY>; 1013 1014 nvidia,outputs = <&sor0 &sor1>; 1015 nvidia,head = <2>; 1016 }; 1017 }; 1018 1019 dsia: dsi@15300000 { 1020 compatible = "nvidia,tegra186-dsi"; 1021 reg = <0x15300000 0x10000>; 1022 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&bpmp TEGRA186_CLK_DSI>, 1024 <&bpmp TEGRA186_CLK_DSIA_LP>, 1025 <&bpmp TEGRA186_CLK_PLLD>; 1026 clock-names = "dsi", "lp", "parent"; 1027 resets = <&bpmp TEGRA186_RESET_DSI>; 1028 reset-names = "dsi"; 1029 status = "disabled"; 1030 1031 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1032 }; 1033 1034 vic@15340000 { 1035 compatible = "nvidia,tegra186-vic"; 1036 reg = <0x15340000 0x40000>; 1037 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&bpmp TEGRA186_CLK_VIC>; 1039 clock-names = "vic"; 1040 resets = <&bpmp TEGRA186_RESET_VIC>; 1041 reset-names = "vic"; 1042 1043 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; 1044 iommus = <&smmu TEGRA186_SID_VIC>; 1045 }; 1046 1047 dsib: dsi@15400000 { 1048 compatible = "nvidia,tegra186-dsi"; 1049 reg = <0x15400000 0x10000>; 1050 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&bpmp TEGRA186_CLK_DSIB>, 1052 <&bpmp TEGRA186_CLK_DSIB_LP>, 1053 <&bpmp TEGRA186_CLK_PLLD>; 1054 clock-names = "dsi", "lp", "parent"; 1055 resets = <&bpmp TEGRA186_RESET_DSIB>; 1056 reset-names = "dsi"; 1057 status = "disabled"; 1058 1059 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1060 }; 1061 1062 sor0: sor@15540000 { 1063 compatible = "nvidia,tegra186-sor"; 1064 reg = <0x15540000 0x10000>; 1065 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1066 clocks = <&bpmp TEGRA186_CLK_SOR0>, 1067 <&bpmp TEGRA186_CLK_SOR0_OUT>, 1068 <&bpmp TEGRA186_CLK_PLLD2>, 1069 <&bpmp TEGRA186_CLK_PLLDP>, 1070 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1071 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; 1072 clock-names = "sor", "out", "parent", "dp", "safe", 1073 "pad"; 1074 resets = <&bpmp TEGRA186_RESET_SOR0>; 1075 reset-names = "sor"; 1076 pinctrl-0 = <&state_dpaux_aux>; 1077 pinctrl-1 = <&state_dpaux_i2c>; 1078 pinctrl-2 = <&state_dpaux_off>; 1079 pinctrl-names = "aux", "i2c", "off"; 1080 status = "disabled"; 1081 1082 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1083 nvidia,interface = <0>; 1084 }; 1085 1086 sor1: sor@15580000 { 1087 compatible = "nvidia,tegra186-sor"; 1088 reg = <0x15580000 0x10000>; 1089 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&bpmp TEGRA186_CLK_SOR1>, 1091 <&bpmp TEGRA186_CLK_SOR1_OUT>, 1092 <&bpmp TEGRA186_CLK_PLLD3>, 1093 <&bpmp TEGRA186_CLK_PLLDP>, 1094 <&bpmp TEGRA186_CLK_SOR_SAFE>, 1095 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; 1096 clock-names = "sor", "out", "parent", "dp", "safe", 1097 "pad"; 1098 resets = <&bpmp TEGRA186_RESET_SOR1>; 1099 reset-names = "sor"; 1100 pinctrl-0 = <&state_dpaux1_aux>; 1101 pinctrl-1 = <&state_dpaux1_i2c>; 1102 pinctrl-2 = <&state_dpaux1_off>; 1103 pinctrl-names = "aux", "i2c", "off"; 1104 status = "disabled"; 1105 1106 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1107 nvidia,interface = <1>; 1108 }; 1109 1110 dpaux: dpaux@155c0000 { 1111 compatible = "nvidia,tegra186-dpaux"; 1112 reg = <0x155c0000 0x10000>; 1113 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&bpmp TEGRA186_CLK_DPAUX>, 1115 <&bpmp TEGRA186_CLK_PLLDP>; 1116 clock-names = "dpaux", "parent"; 1117 resets = <&bpmp TEGRA186_RESET_DPAUX>; 1118 reset-names = "dpaux"; 1119 status = "disabled"; 1120 1121 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1122 1123 state_dpaux_aux: pinmux-aux { 1124 groups = "dpaux-io"; 1125 function = "aux"; 1126 }; 1127 1128 state_dpaux_i2c: pinmux-i2c { 1129 groups = "dpaux-io"; 1130 function = "i2c"; 1131 }; 1132 1133 state_dpaux_off: pinmux-off { 1134 groups = "dpaux-io"; 1135 function = "off"; 1136 }; 1137 1138 i2c-bus { 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 }; 1142 }; 1143 1144 padctl@15880000 { 1145 compatible = "nvidia,tegra186-dsi-padctl"; 1146 reg = <0x15880000 0x10000>; 1147 resets = <&bpmp TEGRA186_RESET_DSI>; 1148 reset-names = "dsi"; 1149 status = "disabled"; 1150 }; 1151 1152 dsic: dsi@15900000 { 1153 compatible = "nvidia,tegra186-dsi"; 1154 reg = <0x15900000 0x10000>; 1155 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&bpmp TEGRA186_CLK_DSIC>, 1157 <&bpmp TEGRA186_CLK_DSIC_LP>, 1158 <&bpmp TEGRA186_CLK_PLLD>; 1159 clock-names = "dsi", "lp", "parent"; 1160 resets = <&bpmp TEGRA186_RESET_DSIC>; 1161 reset-names = "dsi"; 1162 status = "disabled"; 1163 1164 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1165 }; 1166 1167 dsid: dsi@15940000 { 1168 compatible = "nvidia,tegra186-dsi"; 1169 reg = <0x15940000 0x10000>; 1170 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&bpmp TEGRA186_CLK_DSID>, 1172 <&bpmp TEGRA186_CLK_DSID_LP>, 1173 <&bpmp TEGRA186_CLK_PLLD>; 1174 clock-names = "dsi", "lp", "parent"; 1175 resets = <&bpmp TEGRA186_RESET_DSID>; 1176 reset-names = "dsi"; 1177 status = "disabled"; 1178 1179 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; 1180 }; 1181 }; 1182 1183 gpu@17000000 { 1184 compatible = "nvidia,gp10b"; 1185 reg = <0x0 0x17000000 0x0 0x1000000>, 1186 <0x0 0x18000000 0x0 0x1000000>; 1187 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH 1188 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1189 interrupt-names = "stall", "nonstall"; 1190 1191 clocks = <&bpmp TEGRA186_CLK_GPCCLK>, 1192 <&bpmp TEGRA186_CLK_GPU>; 1193 clock-names = "gpu", "pwr"; 1194 resets = <&bpmp TEGRA186_RESET_GPU>; 1195 reset-names = "gpu"; 1196 status = "disabled"; 1197 1198 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; 1199 }; 1200 1201 sysram@30000000 { 1202 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 1203 reg = <0x0 0x30000000 0x0 0x50000>; 1204 #address-cells = <2>; 1205 #size-cells = <2>; 1206 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 1207 1208 cpu_bpmp_tx: shmem@4e000 { 1209 compatible = "nvidia,tegra186-bpmp-shmem"; 1210 reg = <0x0 0x4e000 0x0 0x1000>; 1211 label = "cpu-bpmp-tx"; 1212 pool; 1213 }; 1214 1215 cpu_bpmp_rx: shmem@4f000 { 1216 compatible = "nvidia,tegra186-bpmp-shmem"; 1217 reg = <0x0 0x4f000 0x0 0x1000>; 1218 label = "cpu-bpmp-rx"; 1219 pool; 1220 }; 1221 }; 1222 1223 bpmp: bpmp { 1224 compatible = "nvidia,tegra186-bpmp"; 1225 iommus = <&smmu TEGRA186_SID_BPMP>; 1226 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1227 TEGRA_HSP_DB_MASTER_BPMP>; 1228 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1229 #clock-cells = <1>; 1230 #reset-cells = <1>; 1231 #power-domain-cells = <1>; 1232 1233 bpmp_i2c: i2c { 1234 compatible = "nvidia,tegra186-bpmp-i2c"; 1235 nvidia,bpmp-bus-id = <5>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 bpmp_thermal: thermal { 1242 compatible = "nvidia,tegra186-bpmp-thermal"; 1243 #thermal-sensor-cells = <1>; 1244 }; 1245 }; 1246 1247 cpus { 1248 #address-cells = <1>; 1249 #size-cells = <0>; 1250 1251 cpu@0 { 1252 compatible = "nvidia,tegra186-denver"; 1253 device_type = "cpu"; 1254 i-cache-size = <0x20000>; 1255 i-cache-line-size = <64>; 1256 i-cache-sets = <512>; 1257 d-cache-size = <0x10000>; 1258 d-cache-line-size = <64>; 1259 d-cache-sets = <256>; 1260 next-level-cache = <&L2_DENVER>; 1261 reg = <0x000>; 1262 }; 1263 1264 cpu@1 { 1265 compatible = "nvidia,tegra186-denver"; 1266 device_type = "cpu"; 1267 i-cache-size = <0x20000>; 1268 i-cache-line-size = <64>; 1269 i-cache-sets = <512>; 1270 d-cache-size = <0x10000>; 1271 d-cache-line-size = <64>; 1272 d-cache-sets = <256>; 1273 next-level-cache = <&L2_DENVER>; 1274 reg = <0x001>; 1275 }; 1276 1277 cpu@2 { 1278 compatible = "arm,cortex-a57"; 1279 device_type = "cpu"; 1280 i-cache-size = <0xC000>; 1281 i-cache-line-size = <64>; 1282 i-cache-sets = <256>; 1283 d-cache-size = <0x8000>; 1284 d-cache-line-size = <64>; 1285 d-cache-sets = <256>; 1286 next-level-cache = <&L2_A57>; 1287 reg = <0x100>; 1288 }; 1289 1290 cpu@3 { 1291 compatible = "arm,cortex-a57"; 1292 device_type = "cpu"; 1293 i-cache-size = <0xC000>; 1294 i-cache-line-size = <64>; 1295 i-cache-sets = <256>; 1296 d-cache-size = <0x8000>; 1297 d-cache-line-size = <64>; 1298 d-cache-sets = <256>; 1299 next-level-cache = <&L2_A57>; 1300 reg = <0x101>; 1301 }; 1302 1303 cpu@4 { 1304 compatible = "arm,cortex-a57"; 1305 device_type = "cpu"; 1306 i-cache-size = <0xC000>; 1307 i-cache-line-size = <64>; 1308 i-cache-sets = <256>; 1309 d-cache-size = <0x8000>; 1310 d-cache-line-size = <64>; 1311 d-cache-sets = <256>; 1312 next-level-cache = <&L2_A57>; 1313 reg = <0x102>; 1314 }; 1315 1316 cpu@5 { 1317 compatible = "arm,cortex-a57"; 1318 device_type = "cpu"; 1319 i-cache-size = <0xC000>; 1320 i-cache-line-size = <64>; 1321 i-cache-sets = <256>; 1322 d-cache-size = <0x8000>; 1323 d-cache-line-size = <64>; 1324 d-cache-sets = <256>; 1325 next-level-cache = <&L2_A57>; 1326 reg = <0x103>; 1327 }; 1328 1329 L2_DENVER: l2-cache0 { 1330 compatible = "cache"; 1331 cache-unified; 1332 cache-level = <2>; 1333 cache-size = <0x200000>; 1334 cache-line-size = <64>; 1335 cache-sets = <2048>; 1336 }; 1337 1338 L2_A57: l2-cache1 { 1339 compatible = "cache"; 1340 cache-unified; 1341 cache-level = <2>; 1342 cache-size = <0x200000>; 1343 cache-line-size = <64>; 1344 cache-sets = <2048>; 1345 }; 1346 }; 1347 1348 thermal-zones { 1349 a57 { 1350 polling-delay = <0>; 1351 polling-delay-passive = <1000>; 1352 1353 thermal-sensors = 1354 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; 1355 1356 trips { 1357 critical { 1358 temperature = <101000>; 1359 hysteresis = <0>; 1360 type = "critical"; 1361 }; 1362 }; 1363 1364 cooling-maps { 1365 }; 1366 }; 1367 1368 denver { 1369 polling-delay = <0>; 1370 polling-delay-passive = <1000>; 1371 1372 thermal-sensors = 1373 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; 1374 1375 trips { 1376 critical { 1377 temperature = <101000>; 1378 hysteresis = <0>; 1379 type = "critical"; 1380 }; 1381 }; 1382 1383 cooling-maps { 1384 }; 1385 }; 1386 1387 gpu { 1388 polling-delay = <0>; 1389 polling-delay-passive = <1000>; 1390 1391 thermal-sensors = 1392 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; 1393 1394 trips { 1395 critical { 1396 temperature = <101000>; 1397 hysteresis = <0>; 1398 type = "critical"; 1399 }; 1400 }; 1401 1402 cooling-maps { 1403 }; 1404 }; 1405 1406 pll { 1407 polling-delay = <0>; 1408 polling-delay-passive = <1000>; 1409 1410 thermal-sensors = 1411 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; 1412 1413 trips { 1414 critical { 1415 temperature = <101000>; 1416 hysteresis = <0>; 1417 type = "critical"; 1418 }; 1419 }; 1420 1421 cooling-maps { 1422 }; 1423 }; 1424 1425 always_on { 1426 polling-delay = <0>; 1427 polling-delay-passive = <1000>; 1428 1429 thermal-sensors = 1430 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; 1431 1432 trips { 1433 critical { 1434 temperature = <101000>; 1435 hysteresis = <0>; 1436 type = "critical"; 1437 }; 1438 }; 1439 1440 cooling-maps { 1441 }; 1442 }; 1443 }; 1444 1445 timer { 1446 compatible = "arm,armv8-timer"; 1447 interrupts = <GIC_PPI 13 1448 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1449 <GIC_PPI 14 1450 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1451 <GIC_PPI 11 1452 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1453 <GIC_PPI 10 1454 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1455 interrupt-parent = <&gic>; 1456 always-on; 1457 }; 1458}; 1459