1#include <dt-bindings/interrupt-controller/arm-gic.h> 2 3/ { 4 compatible = "nvidia,tegra186"; 5 interrupt-parent = <&gic>; 6 #address-cells = <2>; 7 #size-cells = <2>; 8 9 uarta: serial@3100000 { 10 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 11 reg = <0x0 0x03100000 0x0 0x40>; 12 reg-shift = <2>; 13 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 14 clocks = <&bpmp 55>; 15 clock-names = "serial"; 16 resets = <&bpmp 47>; 17 reset-names = "serial"; 18 status = "disabled"; 19 }; 20 21 uartb: serial@3110000 { 22 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 23 reg = <0x0 0x03110000 0x0 0x40>; 24 reg-shift = <2>; 25 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 26 clocks = <&bpmp 56>; 27 clock-names = "serial"; 28 resets = <&bpmp 48>; 29 reset-names = "serial"; 30 status = "disabled"; 31 }; 32 33 uartd: serial@3130000 { 34 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 35 reg = <0x0 0x03130000 0x0 0x40>; 36 reg-shift = <2>; 37 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 38 clocks = <&bpmp 77>; 39 clock-names = "serial"; 40 resets = <&bpmp 50>; 41 reset-names = "serial"; 42 status = "disabled"; 43 }; 44 45 uarte: serial@3140000 { 46 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 47 reg = <0x0 0x03140000 0x0 0x40>; 48 reg-shift = <2>; 49 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 50 clocks = <&bpmp 194>; 51 clock-names = "serial"; 52 resets = <&bpmp 132>; 53 reset-names = "serial"; 54 status = "disabled"; 55 }; 56 57 uartf: serial@3150000 { 58 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 59 reg = <0x0 0x03150000 0x0 0x40>; 60 reg-shift = <2>; 61 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 62 clocks = <&bpmp 195>; 63 clock-names = "serial"; 64 resets = <&bpmp 111>; 65 reset-names = "serial"; 66 status = "disabled"; 67 }; 68 69 gen1_i2c: i2c@3160000 { 70 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 71 reg = <0x0 0x03160000 0x0 0x10000>; 72 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 clocks = <&bpmp 47>; 76 clock-names = "div-clk"; 77 resets = <&bpmp 19>; 78 reset-names = "i2c"; 79 status = "disabled"; 80 }; 81 82 cam_i2c: i2c@3180000 { 83 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 84 reg = <0x0 0x03180000 0x0 0x10000>; 85 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 86 #address-cells = <1>; 87 #size-cells = <0>; 88 clocks = <&bpmp 75>; 89 clock-names = "div-clk"; 90 resets = <&bpmp 21>; 91 reset-names = "i2c"; 92 status = "disabled"; 93 }; 94 95 /* shares pads with dpaux1 */ 96 dp_aux_ch1_i2c: i2c@3190000 { 97 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 98 reg = <0x0 0x03190000 0x0 0x10000>; 99 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 clocks = <&bpmp 86>; 103 clock-names = "div-clk"; 104 resets = <&bpmp 22>; 105 reset-names = "i2c"; 106 status = "disabled"; 107 }; 108 109 /* controlled by BPMP, should not be enabled */ 110 pwr_i2c: i2c@31a0000 { 111 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 112 reg = <0x0 0x031a0000 0x0 0x10000>; 113 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 114 #address-cells = <1>; 115 #size-cells = <0>; 116 clocks = <&bpmp 48>; 117 clock-names = "div-clk"; 118 resets = <&bpmp 23>; 119 reset-names = "i2c"; 120 status = "disabled"; 121 }; 122 123 /* shares pads with dpaux0 */ 124 dp_aux_ch0_i2c: i2c@31b0000 { 125 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 126 reg = <0x0 0x031b0000 0x0 0x10000>; 127 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 clocks = <&bpmp 125>; 131 clock-names = "div-clk"; 132 resets = <&bpmp 24>; 133 reset-names = "i2c"; 134 status = "disabled"; 135 }; 136 137 gen7_i2c: i2c@31c0000 { 138 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 139 reg = <0x0 0x031c0000 0x0 0x10000>; 140 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 clocks = <&bpmp 182>; 144 clock-names = "div-clk"; 145 resets = <&bpmp 81>; 146 reset-names = "i2c"; 147 status = "disabled"; 148 }; 149 150 gen9_i2c: i2c@31e0000 { 151 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 152 reg = <0x0 0x031e0000 0x0 0x10000>; 153 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 clocks = <&bpmp 183>; 157 clock-names = "div-clk"; 158 resets = <&bpmp 83>; 159 reset-names = "i2c"; 160 status = "disabled"; 161 }; 162 163 gic: interrupt-controller@3881000 { 164 compatible = "arm,gic-400"; 165 #interrupt-cells = <3>; 166 interrupt-controller; 167 reg = <0x0 0x03881000 0x0 0x1000>, 168 <0x0 0x03882000 0x0 0x2000>; 169 interrupts = <GIC_PPI 9 170 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 171 interrupt-parent = <&gic>; 172 }; 173 174 hsp_top0: hsp@3c00000 { 175 compatible = "nvidia,tegra186-hsp"; 176 reg = <0x0 0x03c00000 0x0 0xa0000>; 177 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 178 interrupt-names = "doorbell"; 179 #mbox-cells = <2>; 180 status = "disabled"; 181 }; 182 183 gen2_i2c: i2c@c240000 { 184 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 185 reg = <0x0 0x0c240000 0x0 0x10000>; 186 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 clocks = <&bpmp 218>; 190 clock-names = "div-clk"; 191 resets = <&bpmp 20>; 192 reset-names = "i2c"; 193 status = "disabled"; 194 }; 195 196 gen8_i2c: i2c@c250000 { 197 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 198 reg = <0x0 0x0c250000 0x0 0x10000>; 199 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 clocks = <&bpmp 219>; 203 clock-names = "div-clk"; 204 resets = <&bpmp 82>; 205 reset-names = "i2c"; 206 status = "disabled"; 207 }; 208 209 uartc: serial@c280000 { 210 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 211 reg = <0x0 0x0c280000 0x0 0x40>; 212 reg-shift = <2>; 213 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 214 clocks = <&bpmp 215>; 215 clock-names = "serial"; 216 resets = <&bpmp 49>; 217 reset-names = "serial"; 218 status = "disabled"; 219 }; 220 221 uartg: serial@c290000 { 222 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 223 reg = <0x0 0x0c290000 0x0 0x40>; 224 reg-shift = <2>; 225 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&bpmp 216>; 227 clock-names = "serial"; 228 resets = <&bpmp 112>; 229 reset-names = "serial"; 230 status = "disabled"; 231 }; 232 233 sysram@30000000 { 234 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 235 reg = <0x0 0x30000000 0x0 0x50000>; 236 #address-cells = <2>; 237 #size-cells = <2>; 238 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 239 240 cpu_bpmp_tx: shmem@4e000 { 241 compatible = "nvidia,tegra186-bpmp-shmem"; 242 reg = <0x0 0x4e000 0x0 0x1000>; 243 label = "cpu-bpmp-tx"; 244 pool; 245 }; 246 247 cpu_bpmp_rx: shmem@4f000 { 248 compatible = "nvidia,tegra186-bpmp-shmem"; 249 reg = <0x0 0x4f000 0x0 0x1000>; 250 label = "cpu-bpmp-rx"; 251 pool; 252 }; 253 }; 254 255 cpus { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 259 cpu@0 { 260 compatible = "nvidia,tegra186-denver", "arm,armv8"; 261 device_type = "cpu"; 262 reg = <0x000>; 263 }; 264 265 cpu@1 { 266 compatible = "nvidia,tegra186-denver", "arm,armv8"; 267 device_type = "cpu"; 268 reg = <0x001>; 269 }; 270 271 cpu@2 { 272 compatible = "arm,cortex-a57", "arm,armv8"; 273 device_type = "cpu"; 274 reg = <0x100>; 275 }; 276 277 cpu@3 { 278 compatible = "arm,cortex-a57", "arm,armv8"; 279 device_type = "cpu"; 280 reg = <0x101>; 281 }; 282 283 cpu@4 { 284 compatible = "arm,cortex-a57", "arm,armv8"; 285 device_type = "cpu"; 286 reg = <0x102>; 287 }; 288 289 cpu@5 { 290 compatible = "arm,cortex-a57", "arm,armv8"; 291 device_type = "cpu"; 292 reg = <0x103>; 293 }; 294 }; 295 296 bpmp: bpmp { 297 compatible = "nvidia,tegra186-bpmp"; 298 mboxes = <&hsp_top0 0 19>; 299 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 300 #clock-cells = <1>; 301 #reset-cells = <1>; 302 303 bpmp_i2c: i2c { 304 compatible = "nvidia,tegra186-bpmp-i2c"; 305 nvidia,bpmp-bus-id = <5>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 }; 311 312 timer { 313 compatible = "arm,armv8-timer"; 314 interrupts = <GIC_PPI 13 315 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 316 <GIC_PPI 14 317 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 318 <GIC_PPI 11 319 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 320 <GIC_PPI 10 321 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 322 interrupt-parent = <&gic>; 323 }; 324}; 325