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/openbmc/linux/drivers/media/platform/renesas/rzg2l-cru/
H A Drzg2l-video.c3 * Driver for Renesas RZ/G2L CRU
21 #include "rzg2l-cru.h"
23 /* HW CRU Registers Definition */
25 /* CRU Control Register */
29 /* CRU Interrupt Enable Register */
33 /* CRU Interrupt Status Register */
37 /* CRU Reset Register */
41 /* Memory Bank Base Address (Lower) Register for CRU Image Data */
44 /* Memory Bank Base Address (Higher) Register for CRU Image Data */
47 /* Memory Bank Enable Register for CRU Image Data */
[all …]
H A Drzg2l-core.c3 * Driver for Renesas RZ/G2L CRU
24 #include "rzg2l-cru.h"
41 struct rzg2l_cru_dev *cru = notifier_to_cru(notifier); in rzg2l_cru_group_notify_complete() local
45 ret = rzg2l_cru_ip_subdev_register(cru); in rzg2l_cru_group_notify_complete()
49 ret = v4l2_device_register_subdev_nodes(&cru->v4l2_dev); in rzg2l_cru_group_notify_complete()
51 dev_err(cru->dev, "Failed to register subdev nodes\n"); in rzg2l_cru_group_notify_complete()
55 ret = rzg2l_cru_video_register(cru); in rzg2l_cru_group_notify_complete()
60 * CRU can be connected either to CSI2 or PARALLEL device in rzg2l_cru_group_notify_complete()
63 * Create media device link between CSI-2 <-> CRU IP in rzg2l_cru_group_notify_complete()
65 source = &cru->csi.subdev->entity; in rzg2l_cru_group_notify_complete()
[all …]
H A Drzg2l-ip.c3 * Driver for Renesas RZ/G2L CRU
8 #include "rzg2l-cru.h"
36 struct v4l2_mbus_framefmt *rzg2l_cru_ip_get_src_fmt(struct rzg2l_cru_dev *cru) in rzg2l_cru_ip_get_src_fmt() argument
41 state = v4l2_subdev_lock_and_get_active_state(&cru->ip.subdev); in rzg2l_cru_ip_get_src_fmt()
42 fmt = v4l2_subdev_get_pad_format(&cru->ip.subdev, state, 1); in rzg2l_cru_ip_get_src_fmt()
50 struct rzg2l_cru_dev *cru; in rzg2l_cru_ip_s_stream() local
54 cru = v4l2_get_subdevdata(sd); in rzg2l_cru_ip_s_stream()
57 ret = v4l2_subdev_call(cru->ip.remote, video, s_stream, enable); in rzg2l_cru_ip_s_stream()
61 ret = v4l2_subdev_call(cru->ip.remote, video, post_streamoff); in rzg2l_cru_ip_s_stream()
66 rzg2l_cru_stop_image_processing(cru); in rzg2l_cru_ip_s_stream()
[all …]
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rv1108.c18 #include <dt-bindings/clock/rv1108-cru.h>
65 static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
117 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, in rkclk_pll_get_rate() argument
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
143 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) in rv1108_mac_set_clk() argument
145 uint32_t con = readl(&cru->clksel_con[24]); in rv1108_mac_set_clk()
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
160 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
[all …]
H A Dclk_rk3128.c17 #include <dt-bindings/clock/rk3128-cru.h>
38 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
140 static void rkclk_init(struct rk3128_cru *cru) in rkclk_init() argument
147 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
153 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); in rkclk_init()
154 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
167 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
172 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
190 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
[all …]
H A Dclk_rk3288.c20 #include <dt-bindings/clock/rk3288-cru.h>
144 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
148 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
175 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, in rkclk_configure_ddr() argument
205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
208 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); in rkclk_configure_ddr()
215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
298 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) in rockchip_mac_set_clk() argument
306 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { in rockchip_mac_set_clk()
310 u32 con = readl(&cru->cru_clksel_con[21]); in rockchip_mac_set_clk()
[all …]
H A Dclk_rk3188.c19 #include <dt-bindings/clock/rk3188-cru.h>
85 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
89 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
119 static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_configure_ddr() argument
149 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
152 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); in rkclk_configure_ddr()
159 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
165 static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_configure_cpu() argument
198 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
201 rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj); in rkclk_configure_cpu()
[all …]
H A Dclk_rk322x.c16 #include <dt-bindings/clock/rk3228-cru.h>
41 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
45 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
79 static void rkclk_init(struct rk322x_cru *cru) in rkclk_init() argument
86 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
92 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); in rkclk_init()
93 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
106 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
111 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
129 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
[all …]
H A Dclk_rk3328.c18 #include <dt-bindings/clock/rk3328-cru.h>
206 static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
216 pll_con = cru->apll_con; in rkclk_set_pll()
220 pll_con = cru->dpll_con; in rkclk_set_pll()
224 pll_con = cru->cpll_con; in rkclk_set_pll()
228 pll_con = cru->gpll_con; in rkclk_set_pll()
232 pll_con = cru->npll_con; in rkclk_set_pll()
256 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift); in rkclk_set_pll()
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
279 static void rkclk_init(struct rk3328_cru *cru) in rkclk_init() argument
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588s.dtsi6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
406 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
417 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
428 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
439 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
476 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
478 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
501 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
503 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
[all …]
H A Drk3588.dtsi24 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
31 resets = <&cru SRST_M_I2S8_8CH_TX>;
41 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
43 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
44 assigned-clock-parents = <&cru PLL_AUPLL>;
48 resets = <&cru SRST_M_I2S6_8CH_TX>;
58 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
60 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
[all …]
H A Drk356x.dtsi6 #include <dt-bindings/clock/rk3568-cru.h>
257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
258 <&cru CLK_SATA1_RXOOB>;
271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
272 <&cru CLK_SATA2_RXOOB>;
286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
287 <&cru ACLK_USB3OTG0>;
293 resets = <&cru SRST_USB3OTG0>;
302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
303 <&cru ACLK_USB3OTG1>;
[all …]
H A Drk3399.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
75 clocks = <&cru ARMCLKL>;
87 clocks = <&cru ARMCLKL>;
99 clocks = <&cru ARMCLKL>;
111 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKB>;
141 clocks = <&cru ARMCLKB>;
185 clocks = <&cru SCLK_DDRC>;
232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
[all …]
H A Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
42 clocks = <&cru ARMCLK>;
55 clocks = <&cru ARMCLK>;
68 clocks = <&cru ARMCLK>;
81 clocks = <&cru ARMCLK>;
217 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
229 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
241 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
253 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
266 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
[all …]
H A Drk3368.dtsi6 #include <dt-bindings/clock/rk3368-cru.h>
183 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
184 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188 resets = <&cru SRST_MMC0>;
197 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
198 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202 resets = <&cru SRST_SDIO0>;
211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
212 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216 resets = <&cru SRST_EMMC>;
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
35 clocks = <&cru ARMCLK>;
43 clocks = <&cru ARMCLK>;
51 clocks = <&cru ARMCLK>;
59 clocks = <&cru ARMCLK>;
178 clocks = <&cru HCLK_EMMC>,
179 <&cru CLK_EMMC>,
180 <&cru HCLK_NANDC>,
181 <&cru CLK_NANDC>,
182 <&cru HCLK_SFC>,
[all …]
H A Drk322x.dtsi7 #include <dt-bindings/clock/rk3228-cru.h>
32 resets = <&cru SRST_CORE0>;
36 clocks = <&cru ARMCLK>;
44 resets = <&cru SRST_CORE1>;
54 resets = <&cru SRST_CORE2>;
64 resets = <&cru SRST_CORE3>;
140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
153 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
163 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
177 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
[all …]
H A Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
61 resets = <&cru SRST_CORE0>;
65 clocks = <&cru ARMCLK>;
72 resets = <&cru SRST_CORE1>;
76 clocks = <&cru ARMCLK>;
83 resets = <&cru SRST_CORE2>;
87 clocks = <&cru ARMCLK>;
94 resets = <&cru SRST_CORE3>;
98 clocks = <&cru ARMCLK>;
199 clocks = <&cru PCLK_TIMER>, <&xin24m>;
[all …]
H A Drk3xxx.dtsi42 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
44 assigned-clocks = <&cru ACLK_GPU>;
46 resets = <&cru SRST_GPU>;
56 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
57 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
78 clocks = <&cru CORE_PERI>;
92 clocks = <&cru CORE_PERI>;
110 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
121 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
169 clocks = <&cru HCLK_OTG0>;
[all …]
H A Drk3066a.dtsi9 #include <dt-bindings/clock/rk3066a-cru.h>
36 clocks = <&cru ARMCLK>;
68 clocks = <&cru ACLK_LCDC0>,
69 <&cru DCLK_LCDC0>,
70 <&cru HCLK_LCDC0>;
73 resets = <&cru SRST_LCDC0_AXI>,
74 <&cru SRST_LCDC0_AHB>,
75 <&cru SRST_LCDC0_DCLK>;
94 clocks = <&cru ACLK_LCDC1>,
95 <&cru DCLK_LCDC1>,
[all …]
H A Drk3036.dtsi7 #include <dt-bindings/clock/rk3036-cru.h>
41 resets = <&cru SRST_CORE0>;
47 clocks = <&cru ARMCLK>;
54 resets = <&cru SRST_CORE1>;
111 assigned-clocks = <&cru SCLK_GPU>;
113 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
116 resets = <&cru SRST_GPU>;
125 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
135 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
145 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
[all …]
H A Drv1108.dtsi6 #include <dt-bindings/clock/rv1108-cru.h>
36 clocks = <&cru ARMCLK>;
103 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
118 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
133 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
147 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
161 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
175 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
187 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
199 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
79 clocks = <&cru ARMCLK>;
80 resets = <&cru SRST_CORE0>;
86 resets = <&cru SRST_CORE1>;
92 resets = <&cru SRST_CORE2>;
98 resets = <&cru SRST_CORE3>;
115 clocks = <&cru ACLK_DMAC2>;
126 clocks = <&cru ACLK_DMAC1>;
138 clocks = <&cru ACLK_DMAC1>;
169 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
[all …]
H A Drk3399.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
77 clocks = <&cru ARMCLKL>;
85 clocks = <&cru ARMCLKL>;
93 clocks = <&cru ARMCLKL>;
101 clocks = <&cru ARMCLKL>;
110 clocks = <&cru ARMCLKB>;
118 clocks = <&cru ARMCLKB>;
165 clocks = <&cru ACLK_DMAC0_PERILP>;
175 clocks = <&cru ACLK_DMAC1_PERILP>;
190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
[all …]
H A Drk3xxx.dtsi45 clocks = <&cru ACLK_DMA1>;
56 clocks = <&cru ACLK_DMA1>;
68 clocks = <&cru ACLK_DMA2>;
96 clocks = <&cru CORE_PERI>;
103 clocks = <&cru CORE_PERI>;
121 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
132 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
146 clocks = <&cru HCLK_OTG0>;
162 clocks = <&cru HCLK_OTG1>;
179 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
[all …]

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