Lines Matching full:cru
24 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
26 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
27 assigned-clock-parents = <&cru PLL_AUPLL>;
31 resets = <&cru SRST_M_I2S8_8CH_TX>;
41 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
43 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
44 assigned-clock-parents = <&cru PLL_AUPLL>;
48 resets = <&cru SRST_M_I2S6_8CH_TX>;
58 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
60 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
61 assigned-clock-parents = <&cru PLL_AUPLL>;
65 resets = <&cru SRST_M_I2S7_8CH_RX>;
75 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
77 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
78 assigned-clock-parents = <&cru PLL_AUPLL>;
82 resets = <&cru SRST_M_I2S10_8CH_RX>;
93 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
94 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
95 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
126 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
144 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
145 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
146 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
177 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
193 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
194 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
195 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
226 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
247 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
248 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
249 <&cru CLK_GMAC0_PTP_REF>;
254 resets = <&cru SRST_A_GMAC0>;
294 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
295 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
296 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
316 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
317 <&cru PCLK_PHP_ROOT>;
319 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
322 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
333 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
335 resets = <&cru SRST_PCIE30_PHY>;