Lines Matching full:cru
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
406 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
417 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
428 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
439 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
476 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
478 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
501 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
503 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
529 cru: clock-controller@fd7c0000 { label
530 compatible = "rockchip,rk3588-cru";
533 <&cru PLL_PPLL>, <&cru PLL_AUPLL>,
534 <&cru PLL_NPLL>, <&cru PLL_GPLL>,
535 <&cru ACLK_CENTER_ROOT>,
536 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
537 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
538 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
539 <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
540 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
541 <&cru CLK_GPU>;
561 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
574 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
588 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
599 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
610 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
621 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
649 clocks = <&cru HCLK_NPU_ROOT>,
650 <&cru PCLK_NPU_ROOT>,
651 <&cru CLK_NPU_DSU0>,
652 <&cru HCLK_NPU_CM0_ROOT>;
662 clocks = <&cru HCLK_NPU_ROOT>,
663 <&cru PCLK_NPU_ROOT>,
664 <&cru CLK_NPU_DSU0>;
670 clocks = <&cru HCLK_NPU_ROOT>,
671 <&cru PCLK_NPU_ROOT>,
672 <&cru CLK_NPU_DSU0>;
681 clocks = <&cru CLK_GPU>,
682 <&cru CLK_GPU_COREGROUP>,
683 <&cru CLK_GPU_STACKS>;
699 clocks = <&cru HCLK_RKVDEC0>,
700 <&cru HCLK_VDPU_ROOT>,
701 <&cru ACLK_VDPU_ROOT>,
702 <&cru ACLK_RKVDEC0>,
703 <&cru ACLK_RKVDEC_CCU>;
709 clocks = <&cru HCLK_RKVDEC1>,
710 <&cru HCLK_VDPU_ROOT>,
711 <&cru ACLK_VDPU_ROOT>,
712 <&cru ACLK_RKVDEC1>;
718 clocks = <&cru HCLK_RKVENC0>,
719 <&cru ACLK_RKVENC0>;
729 clocks = <&cru HCLK_RKVENC1>,
730 <&cru HCLK_RKVENC0>,
731 <&cru ACLK_RKVENC0>,
732 <&cru ACLK_RKVENC1>;
743 clocks = <&cru HCLK_VDPU_ROOT>,
744 <&cru ACLK_VDPU_LOW_ROOT>,
745 <&cru ACLK_VDPU_ROOT>,
746 <&cru ACLK_JPEG_DECODER_ROOT>,
747 <&cru ACLK_IEP2P0>,
748 <&cru HCLK_IEP2P0>,
749 <&cru ACLK_JPEG_ENCODER0>,
750 <&cru HCLK_JPEG_ENCODER0>,
751 <&cru ACLK_JPEG_ENCODER1>,
752 <&cru HCLK_JPEG_ENCODER1>,
753 <&cru ACLK_JPEG_ENCODER2>,
754 <&cru HCLK_JPEG_ENCODER2>,
755 <&cru ACLK_JPEG_ENCODER3>,
756 <&cru HCLK_JPEG_ENCODER3>,
757 <&cru ACLK_JPEG_DECODER>,
758 <&cru HCLK_JPEG_DECODER>,
759 <&cru ACLK_RGA2>,
760 <&cru HCLK_RGA2>;
776 clocks = <&cru PCLK_AV1>,
777 <&cru ACLK_AV1>,
778 <&cru HCLK_VDPU_ROOT>;
784 clocks = <&cru HCLK_RKVDEC0>,
785 <&cru HCLK_VDPU_ROOT>,
786 <&cru ACLK_VDPU_ROOT>,
787 <&cru ACLK_RKVDEC0>;
793 clocks = <&cru HCLK_RKVDEC1>,
794 <&cru HCLK_VDPU_ROOT>,
795 <&cru ACLK_VDPU_ROOT>;
801 clocks = <&cru ACLK_RGA3_0>,
802 <&cru HCLK_RGA3_0>;
809 clocks = <&cru PCLK_VOP_ROOT>,
810 <&cru HCLK_VOP_ROOT>,
811 <&cru ACLK_VOP>;
820 clocks = <&cru PCLK_VO0_ROOT>,
821 <&cru PCLK_VO0_S_ROOT>,
822 <&cru HCLK_VO0_S_ROOT>,
823 <&cru ACLK_VO0_ROOT>,
824 <&cru HCLK_HDCP0>,
825 <&cru ACLK_HDCP0>,
826 <&cru HCLK_VOP_ROOT>;
833 clocks = <&cru PCLK_VO1_ROOT>,
834 <&cru PCLK_VO1_S_ROOT>,
835 <&cru HCLK_VO1_S_ROOT>,
836 <&cru HCLK_HDCP1>,
837 <&cru ACLK_HDCP1>,
838 <&cru ACLK_HDMIRX_ROOT>,
839 <&cru HCLK_VO1USB_TOP_ROOT>;
846 clocks = <&cru HCLK_VI_ROOT>,
847 <&cru PCLK_VI_ROOT>,
848 <&cru HCLK_ISP0>,
849 <&cru ACLK_ISP0>,
850 <&cru HCLK_VICAP>,
851 <&cru ACLK_VICAP>;
862 clocks = <&cru HCLK_ISP1>,
863 <&cru ACLK_ISP1>,
864 <&cru HCLK_VI_ROOT>,
865 <&cru PCLK_VI_ROOT>;
872 clocks = <&cru HCLK_FISHEYE0>,
873 <&cru ACLK_FISHEYE0>,
874 <&cru HCLK_FISHEYE1>,
875 <&cru ACLK_FISHEYE1>,
876 <&cru PCLK_VI_ROOT>;
884 clocks = <&cru HCLK_RGA3_1>,
885 <&cru ACLK_RGA3_1>;
891 clocks = <&cru PCLK_PHP_ROOT>,
892 <&cru ACLK_USB_ROOT>,
893 <&cru ACLK_USB>,
894 <&cru HCLK_USB_ROOT>,
895 <&cru HCLK_HOST0>,
896 <&cru HCLK_HOST_ARB0>,
897 <&cru HCLK_HOST1>,
898 <&cru HCLK_HOST_ARB1>;
907 clocks = <&cru PCLK_PHP_ROOT>,
908 <&cru ACLK_PCIE_ROOT>,
909 <&cru ACLK_PHP_ROOT>;
914 clocks = <&cru PCLK_PHP_ROOT>,
915 <&cru ACLK_PCIE_ROOT>,
916 <&cru ACLK_PHP_ROOT>;
921 clocks = <&cru HCLK_SDIO>,
922 <&cru HCLK_NVM_ROOT>;
928 clocks = <&cru HCLK_AUDIO_ROOT>,
929 <&cru PCLK_AUDIO_ROOT>;
944 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
946 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
947 assigned-clock-parents = <&cru PLL_AUPLL>;
951 resets = <&cru SRST_M_I2S4_8CH_TX>;
961 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
963 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
964 assigned-clock-parents = <&cru PLL_AUPLL>;
968 resets = <&cru SRST_M_I2S5_8CH_TX>;
978 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
980 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
981 assigned-clock-parents = <&cru PLL_AUPLL>;
985 resets = <&cru SRST_M_I2S9_8CH_RX>;
1234 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
1235 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
1236 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
1267 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
1285 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
1286 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
1287 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
1318 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
1339 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
1340 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
1341 <&cru CLK_GMAC1_PTP_REF>;
1346 resets = <&cru SRST_A_GMAC1>;
1386 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
1387 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
1388 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
1409 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
1410 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
1411 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
1433 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1447 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
1448 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1462 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
1464 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1465 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1466 <&cru TMCLK_EMMC>;
1472 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1473 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1474 <&cru SRST_T_EMMC>;
1483 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1485 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1486 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
1490 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1512 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
1516 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1538 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1540 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1541 assigned-clock-parents = <&cru PLL_AUPLL>;
1558 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
1560 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
1561 assigned-clock-parents = <&cru PLL_AUPLL>;
1619 clocks = <&cru ACLK_DMAC0>;
1630 clocks = <&cru ACLK_DMAC1>;
1638 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1651 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1664 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1677 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1690 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1704 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
1711 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
1720 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1736 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1752 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1768 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1784 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1799 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1814 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1829 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1844 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1859 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1874 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1889 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1904 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1918 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1929 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1940 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1951 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1962 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1973 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1984 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1995 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
2006 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2017 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2028 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2039 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
2051 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
2053 assigned-clocks = <&cru CLK_TSADC>;
2055 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
2058 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2072 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
2074 resets = <&cru SRST_P_SARADC>;
2082 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
2095 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
2108 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
2122 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
2137 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
2138 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
2140 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
2141 <&cru SRST_OTPC_ARB>;
2194 clocks = <&cru ACLK_DMAC2>;
2202 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
2203 <&cru PCLK_PHP_ROOT>;
2205 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
2208 resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
2218 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
2219 <&cru PCLK_PHP_ROOT>;
2221 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
2224 resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
2250 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2262 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2274 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2286 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2298 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;