Lines Matching full:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
77 clocks = <&cru ARMCLKL>;
85 clocks = <&cru ARMCLKL>;
93 clocks = <&cru ARMCLKL>;
101 clocks = <&cru ARMCLKL>;
110 clocks = <&cru ARMCLKB>;
118 clocks = <&cru ARMCLKB>;
165 clocks = <&cru ACLK_DMAC0_PERILP>;
175 clocks = <&cru ACLK_DMAC1_PERILP>;
190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
191 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
210 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
211 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
212 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
213 <&cru SRST_A_PCIE>;
230 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
231 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
232 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
233 <&cru PCLK_GMAC>;
239 resets = <&cru SRST_A_GMAC>;
251 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
252 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
256 resets = <&cru SRST_SDIO0>;
267 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
268 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
272 resets = <&cru SRST_SDMMC>;
283 assigned-clocks = <&cru SCLK_EMMC>;
286 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
300 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
314 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
328 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
342 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
357 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
358 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
359 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
363 resets = <&cru SRST_A_USB3_OTG0>;
390 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
391 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
392 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
396 resets = <&cru SRST_A_USB3_OTG1>;
422 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
424 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
425 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
429 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
430 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
490 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
492 resets = <&cru SRST_P_SARADC>;
500 assigned-clocks = <&cru SCLK_I2C1>;
502 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
515 assigned-clocks = <&cru SCLK_I2C2>;
517 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
530 assigned-clocks = <&cru SCLK_I2C3>;
532 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
545 assigned-clocks = <&cru SCLK_I2C5>;
547 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
560 assigned-clocks = <&cru SCLK_I2C6>;
562 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
575 assigned-clocks = <&cru SCLK_I2C7>;
577 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
590 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
603 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
616 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
630 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
643 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
656 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
669 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
682 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
695 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
778 assigned-clocks = <&cru SCLK_TSADC>;
780 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
782 resets = <&cru SRST_TSADC>;
939 clocks = <&cru ACLK_IEP>,
940 <&cru HCLK_IEP>;
945 clocks = <&cru ACLK_RGA>,
946 <&cru HCLK_RGA>;
952 clocks = <&cru ACLK_VCODEC>,
953 <&cru HCLK_VCODEC>;
958 clocks = <&cru ACLK_VDU>,
959 <&cru HCLK_VDU>;
967 clocks = <&cru ACLK_GPU>;
974 clocks = <&cru PCLK_EDP_CTRL>;
978 clocks = <&cru ACLK_EMMC>;
983 clocks = <&cru ACLK_GMAC>,
984 <&cru PCLK_GMAC>;
991 clocks = <&cru ACLK_PERIHP>;
999 clocks = <&cru HCLK_SDMMC>,
1000 <&cru SCLK_SDMMC>;
1006 clocks = <&cru HCLK_SDIO>;
1011 clocks = <&cru ACLK_USB3>;
1022 clocks = <&cru ACLK_HDCP>,
1023 <&cru HCLK_HDCP>,
1024 <&cru PCLK_HDCP>;
1029 clocks = <&cru ACLK_ISP0>,
1030 <&cru HCLK_ISP0>;
1036 clocks = <&cru ACLK_ISP1>,
1037 <&cru HCLK_ISP1>;
1043 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1044 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1048 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1049 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1058 clocks = <&cru ACLK_VOP0>,
1059 <&cru HCLK_VOP0>;
1065 clocks = <&cru ACLK_VOP1>,
1066 <&cru HCLK_VOP1>;
1216 clocks = <&cru PCLK_DDR_MON>;
1226 clocks = <&cru SCLK_DDRCLK>;
1243 clocks = <&cru PCLK_EFUSE1024NS>;
1281 cru: clock-controller@ff760000 { label
1283 compatible = "rockchip,rk3399-cru";
1289 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1290 <&cru PLL_NPLL>,
1291 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1292 <&cru PCLK_PERIHP>,
1293 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1294 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1295 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1296 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1297 <&cru ACLK_GIC_PRE>,
1298 <&cru PCLK_DDR>;
1327 clocks = <&cru SCLK_USB2PHY0_REF>;
1354 clocks = <&cru SCLK_USB2PHY1_REF>;
1389 clocks = <&cru SCLK_PCIEPHY_REF>;
1392 resets = <&cru SRST_PCIEPHY>;
1401 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1402 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1404 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1407 resets = <&cru SRST_UPHY0>,
1408 <&cru SRST_UPHY0_PIPE_L00>,
1409 <&cru SRST_P_UPHY0_TCPHY>;
1426 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1427 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1429 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1432 resets = <&cru SRST_UPHY1>,
1433 <&cru SRST_UPHY1_PIPE_L00>,
1434 <&cru SRST_P_UPHY1_TCPHY>;
1451 clocks = <&cru PCLK_WDT>;
1459 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1470 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1486 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1501 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1516 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1527 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1529 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1533 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1573 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1585 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1587 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1591 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1631 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1643 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1655 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1681 clocks = <&cru PCLK_HDMI_CTRL>,
1682 <&cru SCLK_HDMI_SFR>,
1683 <&cru PLL_VPLL>,
1684 <&cru PCLK_VIO_GRF>,
1685 <&cru SCLK_HDMI_CEC>;
1714 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1715 <&cru SCLK_DPHY_TX0_CFG>;
1742 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1743 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1746 resets = <&cru SRST_P_MIPI_DSI1>;
1777 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1782 resets = <&cru SRST_P_EDP_CTRL>;
1815 clocks = <&cru ACLK_GPU>;
1858 clocks = <&cru PCLK_GPIO2>;
1871 clocks = <&cru PCLK_GPIO3>;
1884 clocks = <&cru PCLK_GPIO4>;