Lines Matching full:cru
9 #include <dt-bindings/clock/rk3066a-cru.h>
36 clocks = <&cru ARMCLK>;
68 clocks = <&cru ACLK_LCDC0>,
69 <&cru DCLK_LCDC0>,
70 <&cru HCLK_LCDC0>;
73 resets = <&cru SRST_LCDC0_AXI>,
74 <&cru SRST_LCDC0_AHB>,
75 <&cru SRST_LCDC0_DCLK>;
94 clocks = <&cru ACLK_LCDC1>,
95 <&cru DCLK_LCDC1>,
96 <&cru HCLK_LCDC1>;
99 resets = <&cru SRST_LCDC1_AXI>,
100 <&cru SRST_LCDC1_AHB>,
101 <&cru SRST_LCDC1_DCLK>;
120 clocks = <&cru HCLK_HDMI>;
161 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
177 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
193 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
203 cru: clock-controller@20000000 { label
204 compatible = "rockchip,rk3066a-cru";
211 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
212 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
213 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
214 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
225 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
234 clocks = <&cru PCLK_EFUSE>;
246 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
254 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
261 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
265 resets = <&cru SRST_TSADC>;
281 clocks = <&cru PCLK_GPIO0>;
294 clocks = <&cru PCLK_GPIO1>;
307 clocks = <&cru PCLK_GPIO2>;
320 clocks = <&cru PCLK_GPIO3>;
333 clocks = <&cru PCLK_GPIO4>;
346 clocks = <&cru PCLK_GPIO6>;
693 clocks = <&cru SCLK_OTGPHY0>;
701 clocks = <&cru SCLK_OTGPHY1>;
764 clocks = <&cru ACLK_LCDC0>,
765 <&cru ACLK_LCDC1>,
766 <&cru DCLK_LCDC0>,
767 <&cru DCLK_LCDC1>,
768 <&cru HCLK_LCDC0>,
769 <&cru HCLK_LCDC1>,
770 <&cru SCLK_CIF1>,
771 <&cru ACLK_CIF1>,
772 <&cru HCLK_CIF1>,
773 <&cru SCLK_CIF0>,
774 <&cru ACLK_CIF0>,
775 <&cru HCLK_CIF0>,
776 <&cru HCLK_HDMI>,
777 <&cru ACLK_IPP>,
778 <&cru HCLK_IPP>,
779 <&cru ACLK_RGA>,
780 <&cru HCLK_RGA>;
792 clocks = <&cru ACLK_VDPU>,
793 <&cru ACLK_VEPU>,
794 <&cru HCLK_VDPU>,
795 <&cru HCLK_VEPU>;
802 clocks = <&cru ACLK_GPU>;