Lines Matching full:cru
18 #include <dt-bindings/clock/rv1108-cru.h>
65 static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
117 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, in rkclk_pll_get_rate() argument
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
143 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) in rv1108_mac_set_clk() argument
145 uint32_t con = readl(&cru->clksel_con[24]); in rv1108_mac_set_clk()
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
160 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
168 static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) in rv1108_sfc_set_clk() argument
170 u32 con = readl(&cru->clksel_con[27]); in rv1108_sfc_set_clk()
175 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
177 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
181 rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, in rv1108_sfc_set_clk()
189 static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru) in rv1108_saradc_get_clk() argument
193 val = readl(&cru->clksel_con[22]); in rv1108_saradc_get_clk()
200 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_saradc_set_clk() argument
207 rk_clrsetreg(&cru->clksel_con[22], in rv1108_saradc_set_clk()
211 return rv1108_saradc_get_clk(cru); in rv1108_saradc_set_clk()
214 static ulong rv1108_aclk_vio1_get_clk(struct rv1108_cru *cru) in rv1108_aclk_vio1_get_clk() argument
218 val = readl(&cru->clksel_con[28]); in rv1108_aclk_vio1_get_clk()
225 static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio1_set_clk() argument
232 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio1_set_clk()
237 return rv1108_aclk_vio1_get_clk(cru); in rv1108_aclk_vio1_set_clk()
240 static ulong rv1108_aclk_vio0_get_clk(struct rv1108_cru *cru) in rv1108_aclk_vio0_get_clk() argument
244 val = readl(&cru->clksel_con[28]); in rv1108_aclk_vio0_get_clk()
251 static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_vio0_set_clk() argument
258 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio0_set_clk()
264 rk_clrsetreg(&cru->clksel_con[29], in rv1108_aclk_vio0_set_clk()
268 rk_clrsetreg(&cru->clksel_con[29], in rv1108_aclk_vio0_set_clk()
272 return rv1108_aclk_vio0_get_clk(cru); in rv1108_aclk_vio0_set_clk()
275 static ulong rv1108_dclk_vop_get_clk(struct rv1108_cru *cru) in rv1108_dclk_vop_get_clk() argument
279 val = readl(&cru->clksel_con[32]); in rv1108_dclk_vop_get_clk()
286 static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_dclk_vop_set_clk() argument
293 rk_clrsetreg(&cru->clksel_con[32], in rv1108_dclk_vop_set_clk()
300 return rv1108_dclk_vop_get_clk(cru); in rv1108_dclk_vop_set_clk()
303 static ulong rv1108_aclk_bus_get_clk(struct rv1108_cru *cru) in rv1108_aclk_bus_get_clk() argument
306 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_get_clk()
308 val = readl(&cru->clksel_con[2]); in rv1108_aclk_bus_get_clk()
315 static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_bus_set_clk() argument
318 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_set_clk()
323 rk_clrsetreg(&cru->clksel_con[2], in rv1108_aclk_bus_set_clk()
328 return rv1108_aclk_bus_get_clk(cru); in rv1108_aclk_bus_set_clk()
331 static ulong rv1108_aclk_peri_get_clk(struct rv1108_cru *cru) in rv1108_aclk_peri_get_clk() argument
334 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_get_clk()
336 val = readl(&cru->clksel_con[23]); in rv1108_aclk_peri_get_clk()
343 static ulong rv1108_hclk_peri_get_clk(struct rv1108_cru *cru) in rv1108_hclk_peri_get_clk() argument
346 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_get_clk()
348 val = readl(&cru->clksel_con[23]); in rv1108_hclk_peri_get_clk()
355 static ulong rv1108_pclk_peri_get_clk(struct rv1108_cru *cru) in rv1108_pclk_peri_get_clk() argument
358 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_get_clk()
360 val = readl(&cru->clksel_con[23]); in rv1108_pclk_peri_get_clk()
367 static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_aclk_peri_set_clk() argument
370 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_set_clk()
375 rk_clrsetreg(&cru->clksel_con[23], in rv1108_aclk_peri_set_clk()
380 return rv1108_aclk_peri_get_clk(cru); in rv1108_aclk_peri_set_clk()
383 static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_hclk_peri_set_clk() argument
386 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_set_clk()
391 rk_clrsetreg(&cru->clksel_con[23], in rv1108_hclk_peri_set_clk()
395 return rv1108_hclk_peri_get_clk(cru); in rv1108_hclk_peri_set_clk()
398 static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz) in rv1108_pclk_peri_set_clk() argument
401 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_set_clk()
406 rk_clrsetreg(&cru->clksel_con[23], in rv1108_pclk_peri_set_clk()
410 return rv1108_pclk_peri_get_clk(cru); in rv1108_pclk_peri_set_clk()
413 static ulong rv1108_i2c_get_clk(struct rv1108_cru *cru, ulong clk_id) in rv1108_i2c_get_clk() argument
419 con = readl(&cru->clksel_con[19]); in rv1108_i2c_get_clk()
424 con = readl(&cru->clksel_con[19]); in rv1108_i2c_get_clk()
429 con = readl(&cru->clksel_con[20]); in rv1108_i2c_get_clk()
434 con = readl(&cru->clksel_con[20]); in rv1108_i2c_get_clk()
446 static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz) in rv1108_i2c_set_clk() argument
456 rk_clrsetreg(&cru->clksel_con[19], in rv1108_i2c_set_clk()
462 rk_clrsetreg(&cru->clksel_con[19], in rv1108_i2c_set_clk()
468 rk_clrsetreg(&cru->clksel_con[20], in rv1108_i2c_set_clk()
474 rk_clrsetreg(&cru->clksel_con[20], in rv1108_i2c_set_clk()
484 return rv1108_i2c_get_clk(cru, clk_id); in rv1108_i2c_set_clk()
487 static ulong rv1108_mmc_get_clk(struct rv1108_cru *cru) in rv1108_mmc_get_clk() argument
492 con = readl(&cru->clksel_con[26]); in rv1108_mmc_get_clk()
495 con = readl(&cru->clksel_con[25]); in rv1108_mmc_get_clk()
506 static ulong rv1108_mmc_set_clk(struct rv1108_cru *cru, ulong rate) in rv1108_mmc_set_clk() argument
511 div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate); in rv1108_mmc_set_clk()
515 rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK, in rv1108_mmc_set_clk()
517 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mmc_set_clk()
520 rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK, in rv1108_mmc_set_clk()
526 rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK, in rv1108_mmc_set_clk()
540 return rkclk_pll_get_rate(priv->cru, clk->id); in rv1108_clk_get_rate()
542 return rv1108_saradc_get_clk(priv->cru); in rv1108_clk_get_rate()
544 return rv1108_aclk_vio0_get_clk(priv->cru); in rv1108_clk_get_rate()
546 return rv1108_aclk_vio1_get_clk(priv->cru); in rv1108_clk_get_rate()
548 return rv1108_dclk_vop_get_clk(priv->cru); in rv1108_clk_get_rate()
550 return rv1108_aclk_bus_get_clk(priv->cru); in rv1108_clk_get_rate()
552 return rv1108_aclk_peri_get_clk(priv->cru); in rv1108_clk_get_rate()
554 return rv1108_hclk_peri_get_clk(priv->cru); in rv1108_clk_get_rate()
556 return rv1108_pclk_peri_get_clk(priv->cru); in rv1108_clk_get_rate()
561 return rv1108_i2c_get_clk(priv->cru, clk->id); in rv1108_clk_get_rate()
565 return rv1108_mmc_get_clk(priv->cru); in rv1108_clk_get_rate()
578 new_rate = rv1108_mac_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
581 new_rate = rv1108_sfc_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
584 new_rate = rv1108_saradc_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
587 new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
590 new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
593 new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
596 new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
599 new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
602 new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
605 new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
611 new_rate = rv1108_i2c_set_clk(priv->cru, clk->id, rate); in rv1108_clk_set_rate()
615 new_rate = rv1108_mmc_set_clk(priv->cru, rate); in rv1108_clk_set_rate()
629 static void rkclk_init(struct rv1108_cru *cru) in rkclk_init() argument
634 aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ / 2); in rkclk_init()
635 aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ / 2); in rkclk_init()
636 hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ / 2); in rkclk_init()
637 pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ / 2); in rkclk_init()
638 rv1108_aclk_vio0_set_clk(cru, 297000000); in rkclk_init()
639 rv1108_aclk_vio1_set_clk(cru, 297000000); in rkclk_init()
642 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); in rkclk_init()
643 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
644 aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ); in rkclk_init()
645 aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ); in rkclk_init()
646 hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ); in rkclk_init()
647 pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ); in rkclk_init()
649 apll = rkclk_pll_get_rate(cru, CLK_ARM); in rkclk_init()
650 dpll = rkclk_pll_get_rate(cru, CLK_DDR); in rkclk_init()
651 gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); in rkclk_init()
653 rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, in rkclk_init()
665 priv->cru = dev_read_addr_ptr(dev); in rv1108_clk_ofdata_to_platdata()
674 rkclk_init(priv->cru); in rv1108_clk_probe()
722 { .compatible = "rockchip,rv1108-cru" },