Lines Matching full:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
75 clocks = <&cru ARMCLKL>;
87 clocks = <&cru ARMCLKL>;
99 clocks = <&cru ARMCLKL>;
111 clocks = <&cru ARMCLKL>;
123 clocks = <&cru ARMCLKB>;
141 clocks = <&cru ARMCLKB>;
185 clocks = <&cru SCLK_DDRC>;
232 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
233 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
253 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
254 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
255 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
256 <&cru SRST_A_PCIE>;
273 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
274 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
279 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
280 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
281 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
282 <&cru SRST_A_PCIE>;
300 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
301 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
302 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
303 <&cru PCLK_GMAC>;
309 resets = <&cru SRST_A_GMAC>;
322 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
323 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
327 resets = <&cru SRST_SDIO0>;
338 assigned-clocks = <&cru HCLK_SD>;
340 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
341 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
345 resets = <&cru SRST_SDMMC>;
355 assigned-clocks = <&cru SCLK_EMMC>;
357 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
372 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
383 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
394 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
405 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
415 clocks = <&cru PCLK_COREDBG_L>;
423 clocks = <&cru PCLK_COREDBG_L>;
431 clocks = <&cru PCLK_COREDBG_L>;
439 clocks = <&cru PCLK_COREDBG_L>;
447 clocks = <&cru PCLK_COREDBG_B>;
455 clocks = <&cru PCLK_COREDBG_B>;
465 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
466 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
467 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
471 resets = <&cru SRST_A_USB3_OTG0>;
479 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
480 <&cru SCLK_USB3OTG0_SUSPEND>;
501 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
502 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
503 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
507 resets = <&cru SRST_A_USB3_OTG1>;
515 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
516 <&cru SCLK_USB3OTG1_SUSPEND>;
536 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
538 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
539 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
543 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
544 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
605 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
607 resets = <&cru SRST_P_SARADC>;
616 clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
618 resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
626 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
628 resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
635 assigned-clocks = <&cru SCLK_I2C1>;
637 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
650 assigned-clocks = <&cru SCLK_I2C2>;
652 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
665 assigned-clocks = <&cru SCLK_I2C3>;
667 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
680 assigned-clocks = <&cru SCLK_I2C5>;
682 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
695 assigned-clocks = <&cru SCLK_I2C6>;
697 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
710 assigned-clocks = <&cru SCLK_I2C7>;
712 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
725 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
738 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
751 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
764 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
777 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
792 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
807 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
822 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
837 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
928 assigned-clocks = <&cru SCLK_TSADC>;
930 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
932 resets = <&cru SRST_TSADC>;
1089 clocks = <&cru ACLK_IEP>,
1090 <&cru HCLK_IEP>;
1096 clocks = <&cru ACLK_RGA>,
1097 <&cru HCLK_RGA>;
1104 clocks = <&cru ACLK_VCODEC>,
1105 <&cru HCLK_VCODEC>;
1111 clocks = <&cru ACLK_VDU>,
1112 <&cru HCLK_VDU>,
1113 <&cru SCLK_VDU_CA>,
1114 <&cru SCLK_VDU_CORE>;
1123 clocks = <&cru ACLK_GPU>;
1131 clocks = <&cru PCLK_EDP_CTRL>;
1136 clocks = <&cru ACLK_EMMC>;
1142 clocks = <&cru ACLK_GMAC>,
1143 <&cru PCLK_GMAC>;
1149 clocks = <&cru HCLK_SDMMC>,
1150 <&cru SCLK_SDMMC>;
1156 clocks = <&cru HCLK_SDIO>;
1162 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1163 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1168 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1169 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1174 clocks = <&cru ACLK_USB3>;
1187 clocks = <&cru ACLK_HDCP>,
1188 <&cru HCLK_HDCP>,
1189 <&cru PCLK_HDCP>;
1195 clocks = <&cru ACLK_ISP0>,
1196 <&cru HCLK_ISP0>;
1203 clocks = <&cru ACLK_ISP1>,
1204 <&cru HCLK_ISP1>;
1217 clocks = <&cru ACLK_VOP0>,
1218 <&cru HCLK_VOP0>;
1225 clocks = <&cru ACLK_VOP1>,
1226 <&cru HCLK_VOP1>;
1361 clocks = <&cru PCLK_DDR_MON>;
1372 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1382 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1392 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1393 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1403 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1413 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1423 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1425 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1435 clocks = <&cru PCLK_EFUSE1024NS>;
1469 clocks = <&cru ACLK_DMAC0_PERILP>;
1480 clocks = <&cru ACLK_DMAC1_PERILP>;
1496 cru: clock-controller@ff760000 { label
1497 compatible = "rockchip,rk3399-cru";
1505 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1506 <&cru PLL_NPLL>,
1507 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1508 <&cru PCLK_PERIHP>,
1509 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1510 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1511 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1512 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1513 <&cru ACLK_GIC_PRE>,
1514 <&cru PCLK_DDR>,
1515 <&cru ACLK_VDU>;
1543 clocks = <&cru SCLK_MIPIDPHY_REF>,
1544 <&cru SCLK_DPHY_RX0_CFG>,
1545 <&cru PCLK_VIO_GRF>;
1555 clocks = <&cru SCLK_USB2PHY0_REF>;
1582 clocks = <&cru SCLK_USB2PHY1_REF>;
1618 clocks = <&cru SCLK_PCIEPHY_REF>;
1621 resets = <&cru SRST_PCIEPHY>;
1630 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1631 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1633 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1636 resets = <&cru SRST_UPHY0>,
1637 <&cru SRST_UPHY0_PIPE_L00>,
1638 <&cru SRST_P_UPHY0_TCPHY>;
1655 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1656 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1658 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1661 resets = <&cru SRST_UPHY1>,
1662 <&cru SRST_UPHY1_PIPE_L00>,
1663 <&cru SRST_P_UPHY1_TCPHY>;
1680 clocks = <&cru PCLK_WDT>;
1688 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1699 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1715 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1731 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1746 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1756 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1758 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1762 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1801 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1812 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1814 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1818 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1857 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1868 clocks = <&cru SCLK_ISP0>,
1869 <&cru ACLK_ISP0_WRAPPER>,
1870 <&cru HCLK_ISP0_WRAPPER>;
1894 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1905 clocks = <&cru SCLK_ISP1>,
1906 <&cru ACLK_ISP1_WRAPPER>,
1907 <&cru HCLK_ISP1_WRAPPER>;
1931 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1958 clocks = <&cru PCLK_HDMI_CTRL>,
1959 <&cru SCLK_HDMI_SFR>,
1960 <&cru SCLK_HDMI_CEC>,
1961 <&cru PCLK_VIO_GRF>,
1962 <&cru PLL_VPLL>;
1998 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1999 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
2002 resets = <&cru SRST_P_MIPI_DSI0>;
2039 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
2040 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
2043 resets = <&cru SRST_P_MIPI_DSI1>;
2081 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
2086 resets = <&cru SRST_P_EDP_CTRL>;
2124 clocks = <&cru ACLK_GPU>;
2167 clocks = <&cru PCLK_GPIO2>;
2180 clocks = <&cru PCLK_GPIO3>;
2193 clocks = <&cru PCLK_GPIO4>;