20 #include <dt-bindings/clock/rk3288-cru.h>
144 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,  in rkclk_set_pll()  argument
148 	struct rk3288_pll *pll = &cru->pll[pll_id];  in rkclk_set_pll()
175 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf,  in rkclk_configure_ddr()  argument
205 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rkclk_configure_ddr()
208 	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);  in rkclk_configure_ddr()
215 	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,  in rkclk_configure_ddr()
298 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq)  in rockchip_mac_set_clk()  argument
306 	if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {  in rockchip_mac_set_clk()
310 		u32 con = readl(&cru->cru_clksel_con[21]);  in rockchip_mac_set_clk()
325 			rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,  in rockchip_mac_set_clk()
336 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,  in rockchip_vop_set_clk()  argument
347 	rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,  in rockchip_vop_set_clk()
349 	rkclk_set_pll(cru, CLK_NEW, &npll_config);  in rockchip_vop_set_clk()
358 	rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,  in rockchip_vop_set_clk()
364 		rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,  in rockchip_vop_set_clk()
368 		rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,  in rockchip_vop_set_clk()
387 static ulong rockchip_i2s_get_clk(struct rk3288_cru *cru, uint gclk_rate)  in rockchip_i2s_get_clk()  argument
393 	val = readl(&cru->cru_clksel_con[8]);  in rockchip_i2s_get_clk()
403 static ulong rockchip_i2s_set_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_i2s_set_clk()  argument
415 	       &cru->cru_clksel_con[8]);  in rockchip_i2s_set_clk()
417 	return rockchip_i2s_get_clk(cru, gclk_rate);  in rockchip_i2s_set_clk()
421 static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf)  in rkclk_init()  argument
428 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
434 	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);  in rkclk_init()
435 	rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);  in rkclk_init()
457 	rk_clrsetreg(&cru->cru_clksel_con[1],  in rkclk_init()
480 	rk_clrsetreg(&cru->cru_clksel_con[10],  in rkclk_init()
489 	rk_clrsetreg(&cru->cru_mode_con,  in rkclk_init()
495 void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf)  in rk3288_clk_configure_cpu()  argument
498 	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,  in rk3288_clk_configure_cpu()
501 	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);  in rk3288_clk_configure_cpu()
513 	rk_clrsetreg(&cru->cru_clksel_con[0],  in rk3288_clk_configure_cpu()
524 	rk_clrsetreg(&cru->cru_clksel_con[37],  in rk3288_clk_configure_cpu()
532 	rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,  in rk3288_clk_configure_cpu()
537 static uint32_t rkclk_pll_get_rate(struct rk3288_cru *cru,  in rkclk_pll_get_rate()  argument
543 	struct rk3288_pll *pll = &cru->pll[pll_id];  in rkclk_pll_get_rate()
550 	con = readl(&cru->cru_mode_con);  in rkclk_pll_get_rate()
570 static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_mmc_get_clk()  argument
580 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
586 		con = readl(&cru->cru_clksel_con[11]);  in rockchip_mmc_get_clk()
592 		con = readl(&cru->cru_clksel_con[12]);  in rockchip_mmc_get_clk()
604 static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_mmc_set_clk()  argument
611 	/* mmc clock default div 2 internal, need provide double in cru */  in rockchip_mmc_set_clk()
628 		rk_clrsetreg(&cru->cru_clksel_con[12],  in rockchip_mmc_set_clk()
635 		rk_clrsetreg(&cru->cru_clksel_con[11],  in rockchip_mmc_set_clk()
642 		rk_clrsetreg(&cru->cru_clksel_con[12],  in rockchip_mmc_set_clk()
651 	return rockchip_mmc_get_clk(cru, gclk_rate, periph);  in rockchip_mmc_set_clk()
654 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_spi_get_clk()  argument
662 		con = readl(&cru->cru_clksel_con[25]);  in rockchip_spi_get_clk()
667 		con = readl(&cru->cru_clksel_con[25]);  in rockchip_spi_get_clk()
672 		con = readl(&cru->cru_clksel_con[39]);  in rockchip_spi_get_clk()
684 static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,  in rockchip_spi_set_clk()  argument
694 		rk_clrsetreg(&cru->cru_clksel_con[25],  in rockchip_spi_set_clk()
700 		rk_clrsetreg(&cru->cru_clksel_con[25],  in rockchip_spi_set_clk()
706 		rk_clrsetreg(&cru->cru_clksel_con[39],  in rockchip_spi_set_clk()
715 	return rockchip_spi_get_clk(cru, gclk_rate, periph);  in rockchip_spi_set_clk()
718 static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)  in rockchip_saradc_get_clk()  argument
722 	val = readl(&cru->cru_clksel_con[24]);  in rockchip_saradc_get_clk()
729 static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)  in rockchip_saradc_set_clk()  argument
736 	rk_clrsetreg(&cru->cru_clksel_con[24],  in rockchip_saradc_set_clk()
740 	return rockchip_saradc_get_clk(cru);  in rockchip_saradc_set_clk()
748 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk3288_clk_get_rate()
751 		new_rate = rkclk_pll_get_rate(priv->cru, clk->id);  in rk3288_clk_get_rate()
759 		new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);  in rk3288_clk_get_rate()
764 		new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);  in rk3288_clk_get_rate()
776 		new_rate = rockchip_saradc_get_clk(priv->cru);  in rk3288_clk_get_rate()
788 	struct rk3288_cru *cru = priv->cru;  in rk3288_clk_set_rate()  local
791 	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);  in rk3288_clk_set_rate()
797 		rk3288_clk_configure_cpu(priv->cru, priv->grf);  in rk3288_clk_set_rate()
801 		new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);  in rk3288_clk_set_rate()
809 		new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);  in rk3288_clk_set_rate()
814 		new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);  in rk3288_clk_set_rate()
818 		new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);  in rk3288_clk_set_rate()
821 		new_rate = rockchip_mac_set_clk(priv->cru, rate);  in rk3288_clk_set_rate()
825 		new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);  in rk3288_clk_set_rate()
829 		rk_setreg(&cru->cru_clksel_con[28], 1 << 15);  in rk3288_clk_set_rate()
832 		rk_setreg(&cru->cru_clksel_con[6], 1 << 15);  in rk3288_clk_set_rate()
834 		rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);  in rk3288_clk_set_rate()
847 			rk_clrsetreg(&cru->cru_clksel_con[31],  in rk3288_clk_set_rate()
852 			rk_clrsetreg(&cru->cru_clksel_con[31],  in rk3288_clk_set_rate()
862 		rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);  in rk3288_clk_set_rate()
865 		rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);  in rk3288_clk_set_rate()
867 		rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);  in rk3288_clk_set_rate()
872 		new_rate = rockchip_saradc_set_clk(priv->cru, rate);  in rk3288_clk_set_rate()
895 	struct rk3288_cru *cru = priv->cru;  in rk3288_gmac_set_parent()  local
906 		rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);  in rk3288_gmac_set_parent()
922 		rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,  in rk3288_gmac_set_parent()
979 	priv->cru = dev_read_addr_ptr(dev);  in rk3288_clk_ofdata_to_platdata()
997 	priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);  in rk3288_clk_probe()
1009 		reg = readl(&priv->cru->cru_mode_con);  in rk3288_clk_probe()
1016 		rkclk_init(priv->cru, priv->grf);  in rk3288_clk_probe()
1052 	{ .compatible = "rockchip,rk3288-cru" },