Lines Matching full:cru
6 #include <dt-bindings/clock/rk3328-cru.h>
42 clocks = <&cru ARMCLK>;
55 clocks = <&cru ARMCLK>;
68 clocks = <&cru ARMCLK>;
81 clocks = <&cru ARMCLK>;
217 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
229 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
241 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
253 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
266 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
311 clocks = <&cru ACLK_RKVDEC>,
312 <&cru HCLK_RKVDEC>,
313 <&cru SCLK_VDEC_CABAC>,
314 <&cru SCLK_VDEC_CORE>;
319 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
338 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
353 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
368 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
385 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
398 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
411 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
424 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
437 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
450 clocks = <&cru PCLK_WDT>;
456 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
467 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
478 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
490 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
504 clocks = <&cru ACLK_DMAC>;
553 assigned-clocks = <&cru SCLK_TSADC>;
555 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
561 resets = <&cru SRST_TSADC>;
574 clocks = <&cru SCLK_EFUSE>;
599 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
601 resets = <&cru SRST_SARADC_P>;
623 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
625 resets = <&cru SRST_GPU_A>;
632 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
642 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
653 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
663 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
673 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
674 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
676 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>,
677 <&cru SCLK_VDEC_CORE>;
687 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
697 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
699 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
719 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
730 clocks = <&cru PCLK_HDMI>,
731 <&cru SCLK_HDMI_SFC>,
732 <&cru SCLK_RTC32K>;
765 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
776 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
786 cru: clock-controller@ff440000 { label
787 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
799 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
800 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
801 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
802 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
803 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
804 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
805 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
806 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
807 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
808 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
809 <&cru SCLK_WIFI>, <&cru ARMCLK>,
810 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
811 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
812 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
813 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
814 <&cru SCLK_RTC32K>;
816 <&cru HDMIPHY>, <&cru PLL_APLL>,
817 <&cru PLL_GPLL>, <&xin24m>,
852 assigned-clocks = <&cru USB480M>;
879 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
880 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
891 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
892 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
903 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
904 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
916 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
917 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
918 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
919 <&cru PCLK_MAC2IO>;
924 resets = <&cru SRST_GMAC2IO_A>;
937 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
938 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
939 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
940 <&cru SCLK_MAC2PHY_OUT>;
945 resets = <&cru SRST_GMAC2PHY_A>;
961 clocks = <&cru SCLK_MAC2PHY_OUT>;
962 resets = <&cru SRST_MACPHY>;
975 clocks = <&cru HCLK_OTG>;
990 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1000 clocks = <&cru HCLK_HOST0>, <&u2phy>;
1010 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1011 <&cru ACLK_USB3OTG>;
1042 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>,
1043 <&cru SCLK_CRYPTO>;
1045 resets = <&cru SRST_CRYPTO>;
1060 clocks = <&cru PCLK_GPIO0>;
1073 clocks = <&cru PCLK_GPIO1>;
1086 clocks = <&cru PCLK_GPIO2>;
1099 clocks = <&cru PCLK_GPIO3>;