Home
last modified time | relevance | path

Searched +full:cortex +full:- +full:r5 (Results 1 – 15 of 15) sorted by relevance

/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7r/
H A Dtune-cortexr5.inc2 # Tune Settings for Cortex-R5
6 TUNEVALID[cortexr5] = "Enable Cortex-R5 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexr5', ' -mcpu=cortex-r5', '', d)}"
9 require conf/machine/include/arm/arch-armv7r.inc
12 ARMPKGARCH:tune-cortexr5 = "cortexr5"
13 TUNE_FEATURES:tune-cortexr5 = "${TUNE_FEATURES:tune-armv7r-vfpv3d16} cortexr5 idiv"
14 PACKAGE_EXTRA_ARCHS:tune-cortexr5 = "${PACKAGE_EXTRA_ARCHS:tune-armv7r-vfpv3d16} cortexr5-vfpv…
17 ARMPKGARCH:tune-cortexr5hf = "cortexr5"
18 TUNE_FEATURES:tune-cortexr5hf = "${TUNE_FEATURES:tune-cortexr5} callconvention-hard"
19 PACKAGE_EXTRA_ARCHS:tune-cortexr5hf = "cortexr5hf-vfpv3d16"
/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * include/asm-arm/macro.h
5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
20 * Registers r4 and r5 are used, any data in these registers are
24 * caches are enabled or on a multi-core system.
29 ldr r5, =\data
30 str r5, [r4]
35 ldrh r5, =\data
36 strh r5, [r4]
41 ldrb r5, =\data
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-r5.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP R5
10 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "xlnx,zynqmp-r5";
16 model = "Xilinx ZynqMP R5";
19 #address-cells = <0x1>;
20 #size-cells = <0x0>;
23 compatible = "arm,cortex-r5";
[all …]
/openbmc/openbmc/poky/meta/recipes-support/boost/boost/
H A D0001-Don-t-set-up-arch-instruction-set-flags-we-do-that-o.patch4 Subject: [PATCH] Don't set up arch/instruction-set flags, we do that
8 Upstream-Status: Inappropriate
9 Signed-off-by: Christopher Larson <chris_larson@mentor.com>
10 Signed-off-by: Alexander Kanavin <alex.kanavin@gmail.com>
11 ---
12 tools/build/src/tools/gcc.jam | 153 ----------------------------------
13 1 file changed, 153 deletions(-)
15 diff --git a/tools/build/src/tools/gcc.jam b/tools/build/src/tools/gcc.jam
17 --- a/tools/build/src/tools/gcc.jam
19 @@ -1144,156 +1144,3 @@ local rule cpu-flags ( toolset variable : architecture : instruction-set + :
[all …]
/openbmc/u-boot/arch/arm/mach-k3/
H A DKconfig62 bool "Start Cortex-A from SPL"
65 Enabling this will try to start Cortex-A (typically with ATF)
66 after SPL from R5.
/openbmc/u-boot/board/ti/am65x/
H A DREADME2 -------------
9 1. Wake-up (WKUP) domain:
10 - Device Management and Security Controller (DMSC)
12 - Dual Core ARM Cortex-R5F processor
14 - Quad core 64-bit ARM Cortex-A53
19 ----------
20 On AM65x family devices, ROM supports boot only via MCU(R5). This means that
21 bootloader has to run on R5 core. In order to meet this constraint, and for
23 1. Need to move away from R5 asap, so that we want to start *any*
24 firmware on the r5 cores like.... autosar can be loaded to receive CAN
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
5 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
15 #include <asm-offsets.h>
45 * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
49 adr r0, reset /* r0 <- Runtime value of reset */
50 ldr r1, =reset /* r1 <- Linked value of reset */
51 subs r4, r0, r1 /* r4 <- Run-vs-link offset */
[all …]
/openbmc/qemu/docs/system/arm/
H A Demulation.rst3 A-profile CPU architecture support
7 Armv8 and Armv9 versions of the A-profile architecture. It also has support for
10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11 - FEAT_AA32EL0 (Support for AArch32 at EL0)
12 - FEAT_AA32EL1 (Support for AArch32 at EL1)
13 - FEAT_AA32EL2 (Support for AArch32 at EL2)
14 - FEAT_AA32EL3 (Support for AArch32 at EL3)
15 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
16 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
17 - FEAT_AA64EL0 (Support for AArch64 at EL0)
[all …]
/openbmc/u-boot/arch/arm/
H A DKconfig14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
20 information that is embedded into the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
28 U-Boot typically uses a hard-coded value for the stack pointer
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that can be loaded and executed at arbitrary
41 Place a Linux kernel image header at the start of the U-Boot binary.
45 U-Boot needs to use, but which isn't part of the binary.
74 Do not enable instruction cache in U-Boot
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c2 * QEMU ARM TCG-only CPUs.
8 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "accel/tcg/cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
26 ARMISARegisters *isar = &cpu->isar; in aa32_max_features()
48 t = cpu->isar.mvfr1; in aa32_max_features()
51 cpu->isar.mvfr1 = t; in aa32_max_features()
53 t = cpu->isar.mvfr2; in aa32_max_features()
56 cpu->isar.mvfr2 = t; in aa32_max_features()
97 cpu->isar.dbgdidr = t; in aa32_max_features()
[all …]
H A Dtranslate.c5 * Copyright (c) 2005-2007 CodeSourcery
24 #include "translate-a32.h"
29 #include "exec/helper-proto.h"
33 #include "exec/helper-info.c.inc"
56 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
88 /* no-op */ in asimd_imm_const()
156 if (!s->condjmp) { in arm_gen_condlabel()
157 s->condlabel = gen_disas_label(s); in arm_gen_condlabel()
158 s->condjmp = 1; in arm_gen_condlabel()
230 switch (s->mmu_idx) { in get_a32_user_mem_index()
[all …]
/openbmc/openbmc/meta-raspberrypi/recipes-multimedia/rpidistro-ffmpeg/files/
H A D0001-ffmpeg-5.1.4-rpi_24.patch2 Upstream-Status: Inappropriate
4 RPI-Distro repo clones original ffmpeg and applies patches to enable
7 --- a/configure
9 @@ -205,6 +205,7 @@ External library support:
10 --disable-bzlib disable bzlib [autodetect]
11 --disable-coreimage disable Apple CoreImage framework [autodetect]
12 --enable-chromaprint enable audio fingerprinting with chromaprint [no]
13 + --disable-epoxy disable epoxy [autodetect]
14 --enable-frei0r enable frei0r video filtering [no]
15 --enable-gcrypt enable gcrypt, needed for rtmp(t)e support
[all …]
/openbmc/qemu/target/arm/
H A Dhelper.c6 * SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cpu-features.h"
15 #include "exec/page-protection.h"
16 #include "exec/mmap-lock.h"
17 #include "qemu/main-loop.h"
20 #include "qemu/qemu-print.h"
22 #include "exec/translation-block.h"
24 #include "system/cpu-timers.h"
29 #include "qemu/guest-random.h"
33 #include "semihosting/common-semi.h"
[all …]
/openbmc/
Dopengrok1.0.log1 2025-12-29 03:01:08.582-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-29 03:01:08.650-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
[all...]
Dopengrok2.0.log1 2025-12-28 03:01:08.732-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-28 03:01:08.788-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
[all...]