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/openbmc/linux/arch/arm/mm/
H A Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
116 ldr r5, [r0, #V7M_SCB_SHCSR]
117 orr r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
118 str r5, [r0, #V7M_SCB_SHCSR]
121 mov r5, #0x80000000
[all …]
H A Dproc-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
22 #include "proc-v7-3level.S"
24 #include "proc-v7-2level.S"
27 .arch armv7-a
48 * - loc - location to jump to for soft reset
[all …]
H A Dcache-v7.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v7.S
15 #include <asm/hardware/cache-b15-rac.h>
17 #include "proc-macros.S"
19 .arch armv7-a
51 mov r3, r3, lsl r1 @ NumWays-1 shifted into bits [31:...]
64 subs r0, r0, #1 @ Set--
66 subs r3, r3, r1 @ Way--
68 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR
78 * Flush the whole I-cache.
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv7r/
H A Dtune-cortexr5.inc2 # Tune Settings for Cortex-R5
6 TUNEVALID[cortexr5] = "Enable Cortex-R5 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexr5', ' -mcpu=cortex-r5', '', d)}"
9 require conf/machine/include/arm/arch-armv7r.inc
12 ARMPKGARCH:tune-cortexr5 = "cortexr5"
13 TUNE_FEATURES:tune-cortexr5 = "${TUNE_FEATURES:tune-armv7r-vfpv3d16} cortexr5 idiv"
14 PACKAGE_EXTRA_ARCHS:tune-cortexr5 = "${PACKAGE_EXTRA_ARCHS:tune-armv7r-vfpv3d16} cortexr5-vfpv…
17 ARMPKGARCH:tune-cortexr5hf = "cortexr5"
18 TUNE_FEATURES:tune-cortexr5hf = "${TUNE_FEATURES:tune-cortexr5} callconvention-hard"
19 PACKAGE_EXTRA_ARCHS:tune-cortexr5hf = "cortexr5hf-vfpv3d16"
/openbmc/u-boot/arch/arm/include/asm/
H A Dmacro.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * include/asm-arm/macro.h
5 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
20 * Registers r4 and r5 are used, any data in these registers are
24 * caches are enabled or on a multi-core system.
29 ldr r5, =\data
30 str r5, [r4]
35 ldrh r5, =\data
36 strh r5, [r4]
41 ldrb r5, =\data
[all …]
/openbmc/openbmc/poky/meta/recipes-support/boost/boost/
H A D0001-Don-t-set-up-arch-instruction-set-flags-we-do-that-o.patch4 Subject: [PATCH] Don't set up arch/instruction-set flags, we do that
8 Upstream-Status: Inappropriate
9 Signed-off-by: Christopher Larson <chris_larson@mentor.com>
10 Signed-off-by: Alexander Kanavin <alex.kanavin@gmail.com>
11 ---
12 tools/build/src/tools/gcc.jam | 153 ----------------------------------
13 1 file changed, 153 deletions(-)
15 diff --git a/tools/build/src/tools/gcc.jam b/tools/build/src/tools/gcc.jam
17 --- a/tools/build/src/tools/gcc.jam
19 @@ -1144,156 +1144,3 @@ local rule cpu-flags ( toolset variable : architecture : instruction-set + :
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-r5.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP R5
10 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "xlnx,zynqmp-r5";
16 model = "Xilinx ZynqMP R5";
19 #address-cells = <0x1>;
20 #size-cells = <0x0>;
23 compatible = "arm,cortex-r5";
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dentry-header.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
9 #include <asm/uaccess-asm.h>
13 @ -----------------
59 * ARMv7-M exception entry/exit macros.
86 @ we cannot rely on r0-r3 and r12 matching the value saved in the
87 @ exception frame because of tail-chaining. So these have to be
89 ldmia r12!, {r0-r3}
94 sub sp, #PT_REGS_SIZE-S_IP
95 stmdb sp!, {r0-r11}
[all …]
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1994-2002 Russell King
9 * Kernel startup code for all 32-bit CPUs
19 #include <asm/asm-offsets.h>
48 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
74 * ---------------------------
77 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
83 * See linux/arch/arm/tools/mach-types for the complete list of machine
87 * crap here - that's what the boot loader (or in extreme, well justified
97 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dsha1-armv4-large.S2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small 392/+29% 1958/+64% 2250/+96%
29 @ armv4-compact 740/+89% 1552/+26% 1840/+22%
30 @ armv4-large 1420/+92% 1307/+19% 1370/+34%[***]
42 @ i-cache availability, branch penalties, etc.
49 @ [***] which is also ~35% better than compiler generated code. Dual-
50 @ issue Cortex A8 core was measured to process input block in
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
56 @ Cortex A8 core and in absolute terms ~870 cycles per input block
[all …]
H A Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions
12 .arch armv8-a
13 .fpu crypto-neon-fp-armv8
102 vld1.32 {q10-q11}, [ip]!
104 vld1.32 {q12-q13}, [ip]!
106 vld1.32 {q10-q11}, [ip]!
108 vld1.32 {q12-q13}, [ip]!
110 blo 0f @ AES-128: 10 rounds
111 vld1.32 {q10-q11}, [ip]!
[all …]
H A Dpoly1305-armv4.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
9 # IALU(*)/gcc-4.4 NEON
11 # ARM11xx(ARMv6) 7.78/+100% -
12 # Cortex-A5 6.35/+130% 3.00
13 # Cortex-A8 6.25/+115% 2.36
14 # Cortex-A9 5.10/+95% 2.55
15 # Cortex-A15 3.85/+85% 1.25(**)
18 # (*) this is for -march=armv6, i.e. with bunch of ldrb loading data;
19 # (**) these are trade-off results, they can be improved by ~8% but at
[all …]
/openbmc/u-boot/arch/arm/mach-k3/
H A DKconfig62 bool "Start Cortex-A from SPL"
65 Enabling this will try to start Cortex-A (typically with ATF)
66 after SPL from R5.
/openbmc/u-boot/board/ti/am65x/
H A DREADME2 -------------
9 1. Wake-up (WKUP) domain:
10 - Device Management and Security Controller (DMSC)
12 - Dual Core ARM Cortex-R5F processor
14 - Quad core 64-bit ARM Cortex-A53
19 ----------
20 On AM65x family devices, ROM supports boot only via MCU(R5). This means that
21 bootloader has to run on R5 core. In order to meet this constraint, and for
23 1. Need to move away from R5 asap, so that we want to start *any*
24 firmware on the r5 cores like.... autosar can be loaded to receive CAN
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62a.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
13 #include "k3-pinctrl.h"
18 interrupt-parent = <&gic500>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
H A Dk3-am62p.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
13 #include "k3-pinctrl.h"
18 interrupt-parent = <&gic500>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
5 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
15 #include <asm-offsets.h>
45 * Fix .rela.dyn relocations. This allows U-Boot to loaded to and
49 adr r0, reset /* r0 <- Runtime value of reset */
50 ldr r1, =reset /* r1 <- Linked value of reset */
51 subs r4, r0, r1 /* r4 <- Run-vs-link offset */
[all …]
/openbmc/linux/arch/arm/mach-tegra/
H A Dreset-handler.S1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <asm/asm-offsets.h>
22 .arch armv7-a
30 * re-enabling sdram.
74 /* L2 cache resume & re-enable */
106 * r0=3 for the wake-up notification.
135 * must be position-independent.
147 ldr r5, [r12, #RESET_DATA(TF_PRESENT)]
148 cmp r5, #0
156 # Tegra20 is a Cortex-A9 r1p1
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dxlnx_r5_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * ZynqMP R5 Remote Processor driver
7 #include <dt-bindings/power/xlnx-zynqmp-power.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/firmware/xlnx-zynqmp.h>
12 #include <linux/mailbox/zynqmp-ipi-message.h>
30 * reflects possible values of xlnx,cluster-mode dt-property
34 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */
39 * struct mem_bank_data - Memory Bank description
43 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
[all …]
/openbmc/linux/arch/arm/mach-exynos/
H A Dmcpm-exynos.c1 // SPDX-License-Identifier: GPL-2.0
5 // Based on arch/arm/mach-vexpress/dcscb.c
7 #include <linux/arm-cci.h>
12 #include <linux/soc/samsung/exynos-regs-pmu.h>
54 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", \
65 return -EINVAL; in exynos_cpu_powerup()
71 * This assumes the cluster number of the big cores(Cortex A15) in exynos_cpu_powerup()
72 * is 0 and the Little cores(Cortex A7) is 1. in exynos_cpu_powerup()
87 timeout--; in exynos_cpu_powerup()
95 return -ETIMEDOUT; in exynos_cpu_powerup()
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsleep44xx.S1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <asm/hardware/cache-l2x0.h>
15 #include "omap-secure.h"
19 #include "omap4-sar-layout.h"
21 .arch armv7-a
46 * 0 - No context lost
47 * 1 - CPUx L1 and logic lost: MPUSS CSWR
48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
49 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
51 * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
[all …]
/openbmc/qemu/docs/system/arm/
H A Demulation.rst3 A-profile CPU architecture support
7 Armv8 and Armv9 versions of the A-profile architecture. It also has support for
10 - FEAT_AA32BF16 (AArch32 BFloat16 instructions)
11 - FEAT_AA32EL0 (Support for AArch32 at EL0)
12 - FEAT_AA32EL1 (Support for AArch32 at EL1)
13 - FEAT_AA32EL2 (Support for AArch32 at EL2)
14 - FEAT_AA32EL3 (Support for AArch32 at EL3)
15 - FEAT_AA32HPD (AArch32 hierarchical permission disables)
16 - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)
17 - FEAT_AA64EL0 (Support for AArch64 at EL0)
[all …]
/openbmc/u-boot/arch/arm/
H A DKconfig14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
20 information that is embedded into the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
28 U-Boot typically uses a hard-coded value for the stack pointer
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that can be loaded and executed at arbitrary
41 Place a Linux kernel image header at the start of the U-Boot binary.
45 U-Boot needs to use, but which isn't part of the binary.
74 Do not enable instruction cache in U-Boot
[all …]

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