1347863d4SKrzysztof Kozlowski // SPDX-License-Identifier: GPL-2.0
2347863d4SKrzysztof Kozlowski // Copyright (c) 2014 Samsung Electronics Co., Ltd.
3347863d4SKrzysztof Kozlowski // http://www.samsung.com
4347863d4SKrzysztof Kozlowski //
5347863d4SKrzysztof Kozlowski // Based on arch/arm/mach-vexpress/dcscb.c
6ccf55117SAbhilash Kesavan
7ccf55117SAbhilash Kesavan #include <linux/arm-cci.h>
8ccf55117SAbhilash Kesavan #include <linux/delay.h>
9ccf55117SAbhilash Kesavan #include <linux/io.h>
10ccf55117SAbhilash Kesavan #include <linux/of_address.h>
11adc548d7SAbhilash Kesavan #include <linux/syscore_ops.h>
122262d6efSPankaj Dubey #include <linux/soc/samsung/exynos-regs-pmu.h>
13ccf55117SAbhilash Kesavan
14ccf55117SAbhilash Kesavan #include <asm/cputype.h>
15ccf55117SAbhilash Kesavan #include <asm/cp15.h>
16ccf55117SAbhilash Kesavan #include <asm/mcpm.h>
17833b5794SChanho Park #include <asm/smp_plat.h>
18ccf55117SAbhilash Kesavan
19ccf55117SAbhilash Kesavan #include "common.h"
20ccf55117SAbhilash Kesavan
21ccf55117SAbhilash Kesavan #define EXYNOS5420_CPUS_PER_CLUSTER 4
22ccf55117SAbhilash Kesavan #define EXYNOS5420_NR_CLUSTERS 2
23ccf55117SAbhilash Kesavan
2420fe6f98SAbhilash Kesavan #define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9)
2520fe6f98SAbhilash Kesavan #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
2620fe6f98SAbhilash Kesavan #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
2720fe6f98SAbhilash Kesavan
28731d97c2SKrzysztof Kozlowski static void __iomem *ns_sram_base_addr __ro_after_init;
29ea9dd8f6SMarek Szyprowski static bool secure_firmware __ro_after_init;
30adc548d7SAbhilash Kesavan
31ccf55117SAbhilash Kesavan /*
32ccf55117SAbhilash Kesavan * The common v7_exit_coherency_flush API could not be used because of the
33ccf55117SAbhilash Kesavan * Erratum 799270 workaround. This macro is the same as the common one (in
34ccf55117SAbhilash Kesavan * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
35ccf55117SAbhilash Kesavan */
36ccf55117SAbhilash Kesavan #define exynos_v7_exit_coherency_flush(level) \
37ccf55117SAbhilash Kesavan asm volatile( \
38ccf55117SAbhilash Kesavan "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \
39ccf55117SAbhilash Kesavan "bic r0, r0, #"__stringify(CR_C)"\n\t" \
40ccf55117SAbhilash Kesavan "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
41ccf55117SAbhilash Kesavan "isb\n\t"\
42ccf55117SAbhilash Kesavan "bl v7_flush_dcache_"__stringify(level)"\n\t" \
43ccf55117SAbhilash Kesavan "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
44ccf55117SAbhilash Kesavan "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
45ccf55117SAbhilash Kesavan /* Dummy Load of a device register to avoid Erratum 799270 */ \
46ccf55117SAbhilash Kesavan "ldr r4, [%0]\n\t" \
47ccf55117SAbhilash Kesavan "and r4, r4, #0\n\t" \
48ccf55117SAbhilash Kesavan "orr r0, r0, r4\n\t" \
49ccf55117SAbhilash Kesavan "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \
50ccf55117SAbhilash Kesavan "isb\n\t" \
51ccf55117SAbhilash Kesavan "dsb\n\t" \
52ccf55117SAbhilash Kesavan : \
532e94ac42SPankaj Dubey : "Ir" (pmu_base_addr + S5P_INFORM0) \
54*1f640552SArd Biesheuvel : "r0", "r1", "r2", "r3", "r4", "r5", "r6", \
55*1f640552SArd Biesheuvel "r9", "r10", "ip", "lr", "memory")
56ccf55117SAbhilash Kesavan
exynos_cpu_powerup(unsigned int cpu,unsigned int cluster)575f493aceSNicolas Pitre static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster)
58ccf55117SAbhilash Kesavan {
59ccf55117SAbhilash Kesavan unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
60ea9dd8f6SMarek Szyprowski bool state;
61ccf55117SAbhilash Kesavan
62ccf55117SAbhilash Kesavan pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
63ccf55117SAbhilash Kesavan if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
64ccf55117SAbhilash Kesavan cluster >= EXYNOS5420_NR_CLUSTERS)
65ccf55117SAbhilash Kesavan return -EINVAL;
66ccf55117SAbhilash Kesavan
67ea9dd8f6SMarek Szyprowski state = exynos_cpu_power_state(cpunr);
68ccf55117SAbhilash Kesavan exynos_cpu_power_up(cpunr);
69ea9dd8f6SMarek Szyprowski if (!state && secure_firmware) {
70833b5794SChanho Park /*
71833b5794SChanho Park * This assumes the cluster number of the big cores(Cortex A15)
72833b5794SChanho Park * is 0 and the Little cores(Cortex A7) is 1.
73833b5794SChanho Park * When the system was booted from the Little core,
74833b5794SChanho Park * they should be reset during power up cpu.
75833b5794SChanho Park */
76833b5794SChanho Park if (cluster &&
77833b5794SChanho Park cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) {
7898a3308eSMarek Szyprowski unsigned int timeout = 16;
7998a3308eSMarek Szyprowski
80833b5794SChanho Park /*
81833b5794SChanho Park * Before we reset the Little cores, we should wait
82833b5794SChanho Park * the SPARE2 register is set to 1 because the init
83833b5794SChanho Park * codes of the iROM will set the register after
84833b5794SChanho Park * initialization.
85833b5794SChanho Park */
8698a3308eSMarek Szyprowski while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) {
8798a3308eSMarek Szyprowski timeout--;
88833b5794SChanho Park udelay(10);
8998a3308eSMarek Szyprowski }
9098a3308eSMarek Szyprowski
9198a3308eSMarek Szyprowski if (timeout == 0) {
9298a3308eSMarek Szyprowski pr_err("cpu %u cluster %u powerup failed\n",
9398a3308eSMarek Szyprowski cpu, cluster);
9498a3308eSMarek Szyprowski exynos_cpu_power_down(cpunr);
9598a3308eSMarek Szyprowski return -ETIMEDOUT;
9698a3308eSMarek Szyprowski }
97833b5794SChanho Park
98833b5794SChanho Park pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu),
99833b5794SChanho Park EXYNOS_SWRESET);
100833b5794SChanho Park }
101833b5794SChanho Park }
102833b5794SChanho Park
10320fe6f98SAbhilash Kesavan return 0;
104ccf55117SAbhilash Kesavan }
105ccf55117SAbhilash Kesavan
exynos_cluster_powerup(unsigned int cluster)1065f493aceSNicolas Pitre static int exynos_cluster_powerup(unsigned int cluster)
107ccf55117SAbhilash Kesavan {
1085f493aceSNicolas Pitre pr_debug("%s: cluster %u\n", __func__, cluster);
1095f493aceSNicolas Pitre if (cluster >= EXYNOS5420_NR_CLUSTERS)
1105f493aceSNicolas Pitre return -EINVAL;
111ccf55117SAbhilash Kesavan
1125f493aceSNicolas Pitre exynos_cluster_power_up(cluster);
1135f493aceSNicolas Pitre return 0;
1145f493aceSNicolas Pitre }
1155f493aceSNicolas Pitre
exynos_cpu_powerdown_prepare(unsigned int cpu,unsigned int cluster)1165f493aceSNicolas Pitre static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster)
1175f493aceSNicolas Pitre {
1185f493aceSNicolas Pitre unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
119ccf55117SAbhilash Kesavan
120ccf55117SAbhilash Kesavan pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
121ccf55117SAbhilash Kesavan BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
122ccf55117SAbhilash Kesavan cluster >= EXYNOS5420_NR_CLUSTERS);
123ccf55117SAbhilash Kesavan exynos_cpu_power_down(cpunr);
1245f493aceSNicolas Pitre }
125ccf55117SAbhilash Kesavan
exynos_cluster_powerdown_prepare(unsigned int cluster)1265f493aceSNicolas Pitre static void exynos_cluster_powerdown_prepare(unsigned int cluster)
1275f493aceSNicolas Pitre {
1285f493aceSNicolas Pitre pr_debug("%s: cluster %u\n", __func__, cluster);
1295f493aceSNicolas Pitre BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS);
13020fe6f98SAbhilash Kesavan exynos_cluster_power_down(cluster);
131ccf55117SAbhilash Kesavan }
132ccf55117SAbhilash Kesavan
exynos_cpu_cache_disable(void)1335f493aceSNicolas Pitre static void exynos_cpu_cache_disable(void)
1345f493aceSNicolas Pitre {
1355f493aceSNicolas Pitre /* Disable and flush the local CPU cache. */
1365f493aceSNicolas Pitre exynos_v7_exit_coherency_flush(louis);
1375f493aceSNicolas Pitre }
138ccf55117SAbhilash Kesavan
exynos_cluster_cache_disable(void)1395f493aceSNicolas Pitre static void exynos_cluster_cache_disable(void)
1405f493aceSNicolas Pitre {
141af040ffcSRussell King if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
142ccf55117SAbhilash Kesavan /*
143ccf55117SAbhilash Kesavan * On the Cortex-A15 we need to disable
144ccf55117SAbhilash Kesavan * L2 prefetching before flushing the cache.
145ccf55117SAbhilash Kesavan */
146ccf55117SAbhilash Kesavan asm volatile(
147ccf55117SAbhilash Kesavan "mcr p15, 1, %0, c15, c0, 3\n\t"
148ccf55117SAbhilash Kesavan "isb\n\t"
149ccf55117SAbhilash Kesavan "dsb"
150ccf55117SAbhilash Kesavan : : "r" (0x400));
151ccf55117SAbhilash Kesavan }
152ccf55117SAbhilash Kesavan
153ccf55117SAbhilash Kesavan /* Flush all cache levels for this cluster. */
154ccf55117SAbhilash Kesavan exynos_v7_exit_coherency_flush(all);
155ccf55117SAbhilash Kesavan
156ccf55117SAbhilash Kesavan /*
157ccf55117SAbhilash Kesavan * Disable cluster-level coherency by masking
158ccf55117SAbhilash Kesavan * incoming snoops and DVM messages:
159ccf55117SAbhilash Kesavan */
1605f493aceSNicolas Pitre cci_disable_port_by_cpu(read_cpuid_mpidr());
161ccf55117SAbhilash Kesavan }
162ccf55117SAbhilash Kesavan
exynos_wait_for_powerdown(unsigned int cpu,unsigned int cluster)1637c5688e7SKukjin Kim static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
164ccf55117SAbhilash Kesavan {
165ccf55117SAbhilash Kesavan unsigned int tries = 100;
166ccf55117SAbhilash Kesavan unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
167ccf55117SAbhilash Kesavan
168ccf55117SAbhilash Kesavan pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
169ccf55117SAbhilash Kesavan BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
170ccf55117SAbhilash Kesavan cluster >= EXYNOS5420_NR_CLUSTERS);
171ccf55117SAbhilash Kesavan
172ccf55117SAbhilash Kesavan /* Wait for the core state to be OFF */
173ccf55117SAbhilash Kesavan while (tries--) {
174ccf55117SAbhilash Kesavan if ((exynos_cpu_power_state(cpunr) == 0))
175ccf55117SAbhilash Kesavan return 0; /* success: the CPU is halted */
176ccf55117SAbhilash Kesavan
177ccf55117SAbhilash Kesavan /* Otherwise, wait and retry: */
178ccf55117SAbhilash Kesavan msleep(1);
179ccf55117SAbhilash Kesavan }
180ccf55117SAbhilash Kesavan
181ccf55117SAbhilash Kesavan return -ETIMEDOUT; /* timeout */
182ccf55117SAbhilash Kesavan }
183ccf55117SAbhilash Kesavan
exynos_cpu_is_up(unsigned int cpu,unsigned int cluster)1845f493aceSNicolas Pitre static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster)
185fc2cac41SChander Kashyap {
1865f493aceSNicolas Pitre /* especially when resuming: make sure power control is set */
1875f493aceSNicolas Pitre exynos_cpu_powerup(cpu, cluster);
188fc2cac41SChander Kashyap }
189fc2cac41SChander Kashyap
190ccf55117SAbhilash Kesavan static const struct mcpm_platform_ops exynos_power_ops = {
1915f493aceSNicolas Pitre .cpu_powerup = exynos_cpu_powerup,
1925f493aceSNicolas Pitre .cluster_powerup = exynos_cluster_powerup,
1935f493aceSNicolas Pitre .cpu_powerdown_prepare = exynos_cpu_powerdown_prepare,
1945f493aceSNicolas Pitre .cluster_powerdown_prepare = exynos_cluster_powerdown_prepare,
1955f493aceSNicolas Pitre .cpu_cache_disable = exynos_cpu_cache_disable,
1965f493aceSNicolas Pitre .cluster_cache_disable = exynos_cluster_cache_disable,
1977c5688e7SKukjin Kim .wait_for_powerdown = exynos_wait_for_powerdown,
1985f493aceSNicolas Pitre .cpu_is_up = exynos_cpu_is_up,
199ccf55117SAbhilash Kesavan };
200ccf55117SAbhilash Kesavan
201ccf55117SAbhilash Kesavan /*
202ccf55117SAbhilash Kesavan * Enable cluster-level coherency, in preparation for turning on the MMU.
203ccf55117SAbhilash Kesavan */
exynos_pm_power_up_setup(unsigned int affinity_level)204ccf55117SAbhilash Kesavan static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
205ccf55117SAbhilash Kesavan {
206ccf55117SAbhilash Kesavan asm volatile ("\n"
207ccf55117SAbhilash Kesavan "cmp r0, #1\n"
208ccf55117SAbhilash Kesavan "bxne lr\n"
209ccf55117SAbhilash Kesavan "b cci_enable_port_for_self");
210ccf55117SAbhilash Kesavan }
211ccf55117SAbhilash Kesavan
212f99acff1SAbhilash Kesavan static const struct of_device_id exynos_dt_mcpm_match[] = {
213f99acff1SAbhilash Kesavan { .compatible = "samsung,exynos5420" },
214f99acff1SAbhilash Kesavan { .compatible = "samsung,exynos5800" },
215f99acff1SAbhilash Kesavan {},
216f99acff1SAbhilash Kesavan };
217f99acff1SAbhilash Kesavan
exynos_mcpm_setup_entry_point(void)218adc548d7SAbhilash Kesavan static void exynos_mcpm_setup_entry_point(void)
219adc548d7SAbhilash Kesavan {
220adc548d7SAbhilash Kesavan /*
221adc548d7SAbhilash Kesavan * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
222adc548d7SAbhilash Kesavan * as part of secondary_cpu_start(). Let's redirect it to the
223adc548d7SAbhilash Kesavan * mcpm_entry_point(). This is done during both secondary boot-up as
224adc548d7SAbhilash Kesavan * well as system resume.
225adc548d7SAbhilash Kesavan */
226adc548d7SAbhilash Kesavan __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
227adc548d7SAbhilash Kesavan __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
22864fc2a94SFlorian Fainelli __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
229adc548d7SAbhilash Kesavan }
230adc548d7SAbhilash Kesavan
231adc548d7SAbhilash Kesavan static struct syscore_ops exynos_mcpm_syscore_ops = {
232adc548d7SAbhilash Kesavan .resume = exynos_mcpm_setup_entry_point,
233adc548d7SAbhilash Kesavan };
234adc548d7SAbhilash Kesavan
exynos_mcpm_init(void)235ccf55117SAbhilash Kesavan static int __init exynos_mcpm_init(void)
236ccf55117SAbhilash Kesavan {
237ccf55117SAbhilash Kesavan struct device_node *node;
23820fe6f98SAbhilash Kesavan unsigned int value, i;
239ccf55117SAbhilash Kesavan int ret;
240ccf55117SAbhilash Kesavan
241f99acff1SAbhilash Kesavan node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
242ccf55117SAbhilash Kesavan if (!node)
243ccf55117SAbhilash Kesavan return -ENODEV;
244ccf55117SAbhilash Kesavan of_node_put(node);
245ccf55117SAbhilash Kesavan
246ccf55117SAbhilash Kesavan if (!cci_probed())
247ccf55117SAbhilash Kesavan return -ENODEV;
248ccf55117SAbhilash Kesavan
249ccf55117SAbhilash Kesavan node = of_find_compatible_node(NULL, NULL,
250ccf55117SAbhilash Kesavan "samsung,exynos4210-sysram-ns");
251ccf55117SAbhilash Kesavan if (!node)
252ccf55117SAbhilash Kesavan return -ENODEV;
253ccf55117SAbhilash Kesavan
254ccf55117SAbhilash Kesavan ns_sram_base_addr = of_iomap(node, 0);
255ccf55117SAbhilash Kesavan of_node_put(node);
256ccf55117SAbhilash Kesavan if (!ns_sram_base_addr) {
257ccf55117SAbhilash Kesavan pr_err("failed to map non-secure iRAM base address\n");
258ccf55117SAbhilash Kesavan return -ENOMEM;
259ccf55117SAbhilash Kesavan }
260ccf55117SAbhilash Kesavan
261ea9dd8f6SMarek Szyprowski secure_firmware = exynos_secure_firmware_available();
262ea9dd8f6SMarek Szyprowski
263ccf55117SAbhilash Kesavan /*
264ccf55117SAbhilash Kesavan * To increase the stability of KFC reset we need to program
265ccf55117SAbhilash Kesavan * the PMU SPARE3 register
266ccf55117SAbhilash Kesavan */
2672e94ac42SPankaj Dubey pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
268ccf55117SAbhilash Kesavan
269ccf55117SAbhilash Kesavan ret = mcpm_platform_register(&exynos_power_ops);
270ccf55117SAbhilash Kesavan if (!ret)
271ccf55117SAbhilash Kesavan ret = mcpm_sync_init(exynos_pm_power_up_setup);
272fbb04990SNicolas Pitre if (!ret)
2735f493aceSNicolas Pitre ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */
274ccf55117SAbhilash Kesavan if (ret) {
275ccf55117SAbhilash Kesavan iounmap(ns_sram_base_addr);
276ccf55117SAbhilash Kesavan return ret;
277ccf55117SAbhilash Kesavan }
278ccf55117SAbhilash Kesavan
279ccf55117SAbhilash Kesavan mcpm_smp_set_ops();
280ccf55117SAbhilash Kesavan
281ccf55117SAbhilash Kesavan pr_info("Exynos MCPM support installed\n");
282ccf55117SAbhilash Kesavan
283ccf55117SAbhilash Kesavan /*
28420fe6f98SAbhilash Kesavan * On Exynos5420/5800 for the A15 and A7 clusters:
28520fe6f98SAbhilash Kesavan *
28620fe6f98SAbhilash Kesavan * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
28720fe6f98SAbhilash Kesavan * in a cluster are turned off before turning off the cluster L2.
28820fe6f98SAbhilash Kesavan *
28920fe6f98SAbhilash Kesavan * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
29020fe6f98SAbhilash Kesavan * off before waking it up.
29120fe6f98SAbhilash Kesavan *
29220fe6f98SAbhilash Kesavan * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
29320fe6f98SAbhilash Kesavan * turned on before the first man is powered up.
29420fe6f98SAbhilash Kesavan */
29520fe6f98SAbhilash Kesavan for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
2962e94ac42SPankaj Dubey value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
29720fe6f98SAbhilash Kesavan value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
29820fe6f98SAbhilash Kesavan EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
29920fe6f98SAbhilash Kesavan EXYNOS5420_USE_L2_COMMON_UP_STATE;
3002e94ac42SPankaj Dubey pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
30120fe6f98SAbhilash Kesavan }
30220fe6f98SAbhilash Kesavan
303adc548d7SAbhilash Kesavan exynos_mcpm_setup_entry_point();
304ccf55117SAbhilash Kesavan
305adc548d7SAbhilash Kesavan register_syscore_ops(&exynos_mcpm_syscore_ops);
306ccf55117SAbhilash Kesavan
307ccf55117SAbhilash Kesavan return ret;
308ccf55117SAbhilash Kesavan }
309ccf55117SAbhilash Kesavan
310ccf55117SAbhilash Kesavan early_initcall(exynos_mcpm_init);
311