Lines Matching +full:cortex +full:- +full:r5
1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <asm/hardware/cache-l2x0.h>
15 #include "omap-secure.h"
19 #include "omap4-sar-layout.h"
21 .arch armv7-a
46 * 0 - No context lost
47 * 1 - CPUx L1 and logic lost: MPUSS CSWR
48 * 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
49 * 3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
51 * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
62 stmfd sp!, {r4-r12, lr}
76 stmfd r13!, {r4-r12, r14}
79 ldmfd r13!, {r4-r12, r14}
113 stmfd r13!, {r4-r12, r14}
116 ldmfd r13!, {r4-r12, r14}
136 * Common cache-l2x0.c functions can't be used here since it
146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
147 ands r5, r5, #0x0f
198 * In non-coherent mode CPU can lock-up and lead to
213 stmfd r13!, {r4-r12, r14}
216 ldmfd r13!, {r4-r12, r14}
225 ldmfd sp!, {r4-r12, pc}
243 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
246 * OMAP443X GP devices- SMP bit isn't accessible.
247 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
325 .long ppa_por_params - .
357 * NOPs as per Cortex-A9 pipeline.
379 .long ppa_zero_params - .