arm/crypto/sha1-armv4-large.S

2 @ SPDX-License-Identifier: GPL-2.0
23 @ Size/performance trade-off
28 @ armv4-small	392/+29%	1958/+64%	2250/+96%
29 @ armv4-compact	740/+89%	1552/+26%	1840/+22%
30 @ armv4-large	1420/+92%	1307/+19%	1370/+34%[***]
42 @	i-cache availability, branch penalties, etc.
49 @ [***]	which is also ~35% better than compiler generated code. Dual-
50 @	issue Cortex A8 core was measured to process input block in
55 @ Rescheduling for dual-issue pipeline resulted in 13% improvement on
56 @ Cortex A8 core and in absolute terms ~870 cycles per input block
61 @ Profiler-assisted and platform-specific optimization resulted in 10%
62 @ improvement on Cortex A8 core and 12.2 cycles per byte.
70 	stmdb	sp!,{r4-r12,lr}
72 	ldmia	r0,{r3,r4,r5,r6,r7}
77 	mov	r5,r5,ror#30
88 	eor	r10,r5,r6			@ F_xx_xx
95 	eor	r10,r5,r6			@ F_xx_xx
104 	str	r9,[r14,#-4]!
113 	eor	r10,r4,r5			@ F_xx_xx
120 	eor	r10,r4,r5			@ F_xx_xx
128 	eor	r10,r10,r5,ror#2		@ F_00_19(B,C,D)
129 	str	r9,[r14,#-4]!
135 	add	r5,r8,r5,ror#2			@ E+=K_00_19
140 	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
144 	add	r5,r8,r5,ror#2			@ E+=K_00_19
146 	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
152 	add	r5,r5,r9			@ E+=X[i]
154 	str	r9,[r14,#-4]!
155 	add	r5,r5,r10			@ E+=F_00_19(B,C,D)
165 	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
171 	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
179 	str	r9,[r14,#-4]!
201 	and	r10,r5,r10,ror#2
204 	str	r9,[r14,#-4]!
216 	eor	r10,r5,r6			@ F_xx_xx
223 	eor	r10,r5,r6			@ F_xx_xx
232 	str	r9,[r14,#-4]!
241 	eor	r10,r4,r5			@ F_xx_xx
245 	str	r9,[r14,#-4]!
249 	eor	r10,r10,r5,ror#2		@ F_00_19(B,C,D)
254 	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
260 	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
262 	str	r9,[r14,#-4]!
265 	add	r5,r5,r9			@ E+=X[i]
267 	add	r5,r5,r10			@ E+=F_00_19(B,C,D)
277 	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
279 	str	r9,[r14,#-4]!
296 	str	r9,[r14,#-4]!
297 	and r10,r5,r10,ror#2					@ F_xx_xx
313 	eor	r10,r5,r6			@ F_xx_xx
317 	str	r9,[r14,#-4]!
329 	eor	r10,r4,r5			@ F_xx_xx
333 	str	r9,[r14,#-4]!
341 	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
347 	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
349 	str	r9,[r14,#-4]!
352 	add	r5,r5,r9			@ E+=X[i]
353 	add	r5,r5,r10			@ E+=F_20_39(B,C,D)
363 	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
365 	str	r9,[r14,#-4]!
381 	str	r9,[r14,#-4]!
382 	eor r10,r5,r10,ror#2					@ F_xx_xx
402 	eor	r10,r5,r6			@ F_xx_xx
406 	str	r9,[r14,#-4]!
408 	and r11,r5,r6					@ F_xx_xx
419 	eor	r10,r4,r5			@ F_xx_xx
423 	str	r9,[r14,#-4]!
425 	and r11,r4,r5					@ F_xx_xx
432 	add	r5,r8,r5,ror#2			@ E+=K_xx_xx
438 	add	r5,r5,r6,ror#27			@ E+=ROR(A,27)
440 	str	r9,[r14,#-4]!
443 	add	r5,r5,r9			@ E+=X[i]
444 	add	r5,r5,r10			@ E+=F_40_59(B,C,D)
445 	add	r5,r5,r11,ror#2
455 	add	r4,r4,r5,ror#27			@ E+=ROR(A,27)
457 	str	r9,[r14,#-4]!
474 	str	r9,[r14,#-4]!
475 	and r10,r5,r10,ror#2					@ F_xx_xx
492 	add	r5,r10,r5,ror#2
495 	stmia	r0,{r3,r4,r5,r6,r7}
499 	ldmia	sp!,{r4-r12,pc}