arm/kernel/head.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  *  Copyright (C) 1994-2002 Russell King
9  *  Kernel startup code for all 32-bit CPUs
19 #include <asm/asm-offsets.h>
48 	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
74  * ---------------------------
77  * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
83  * See linux/arch/arm/tools/mach-types for the complete list of machine
87  * crap here - that's what the boot loader (or in extreme, well justified
97  THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
108 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
109 	movs	r10, r5				@ invalid processor (r5=0)?
110  THUMB( it	eq )		@ force fixup-able long branch encoding
116 	cmp	r3, #5				@ long-descriptor translation table format?
117  THUMB( it	lo )				@ force fixup-able long branch encoding
143 	 * manner.  See arch/arm/mm/proc-*.S for details.  r10 = base of
148 	 *  r1 - machine type
149 	 *  r2 - boot data (atags/dt) pointer
150 	 *  r4 - translation table base (low word)
151 	 *  r5 - translation table base (high word, if LPAE)
152 	 *  r8 - translation table base 1 (pfn if LPAE)
153 	 *  r9 - cpuid
154 	 *  r13 - virtual address for __enable_mmu -> __turn_mmu_on
158 	 * r9 will be preserved.  r5 will also be preserved if LPAE.
164 	mov	r5, #0				@ high TTBR0
184  *  r0, r3, r5-r7 corrupted
206 	 * entry is 64-bit wide.
212 	mov	r7, #1 << (55 - 32)		@ L_PGD_SWAPPER
237 	adr_l	r5, __turn_mmu_on		@ _pa(__turn_mmu_on)
239 	mov	r5, r5, lsr #SECTION_SHIFT
242 1:	orr	r3, r7, r5, lsl #SECTION_SHIFT	@ flags + kernel base
243 	str	r3, [r4, r5, lsl #PMD_ENTRY_ORDER]	@ identity mapping
244 	cmp	r5, r6
245 	addlo	r5, r5, #1			@ next section
253 	add	r0, r4, #KERNEL_OFFSET >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
254 	ldr	r6, =(_end - 1)
258 	adr_l	r5, kernel_sec_start		@ _pa(kernel_sec_start)
260 	str	r8, [r5, #4]			@ Save physical start of kernel (BE)
262 	str	r8, [r5]			@ Save physical start of kernel (LE)
266 	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ENTRY_ORDER)
273 	adr_l	r5, kernel_sec_end		@ _pa(kernel_sec_end)
275 	str	r3, [r5, #4]			@ Save physical end of kernel (BE)
277 	str	r3, [r5]			@ Save physical end of kernel (LE)
287 	add	r0, r4,  #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
289 	ldr	r6, =(_edata_loc - 1)
291 	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ENTRY_ORDER)
304 	ldrne	r3, =FDT_FIXED_BASE >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
313 						@ for 64-bit descriptors
333 	mov	r7, #1 << (54 - 32)		@ XN
354 	 * in the 16550-type serial port for the debug messages
356 	add	r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
363 	 * Similar reasons here - for debug.  This is
366 	add	r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
369 	add	r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ENTRY_ORDER)
385  THUMB(	bx	r9		)	@ If this is a Thumb-2 kernel,
393 	 * the processor type - there is no need to check the machine type
406 	movs	r10, r5				@ invalid processor?
408  THUMB( it	eq )		@ force fixup-able long branch encoding
415 	ldr	r3, =(secondary_data + PLAT_PHYS_OFFSET - PAGE_OFFSET)
420 	ldrd	r4, r5, [r3, #0]		@ get secondary_data.pgdir
421 ARM_BE8(eor	r4, r4, r5)			@ Swap r5 and r4 in BE:
422 ARM_BE8(eor	r5, r4, r5)			@ it can be done in 3 steps
423 ARM_BE8(eor	r4, r4, r5)			@ without using a temp reg.
463  *  r5  = TTBR pointer (high word if LPAE)
483 	mcrr	p15, 0, r4, r5, c2		@ load TTBR0
485 	mov	r5, #DACR_INIT
486 	mcr	p15, 0, r5, c3, c0, 0		@ load domain access register
495  * If you have an enquiry about this, *please* check the linux-arm-kernel
543 	@ Cortex-A9 CPU is present but SMP operations fault.
547 	teq	r3, r4			@ Check for ARM Cortex-A9
548 	retne	lr			@ Not ARM Cortex-A9,
564 	adr_l	r5, __smpalt_end
579 	cmp	r4, r5
586  THUMB(	mov	r6, r6, ror #16	)	@ Convert word order for big-endian.
588  THUMB(	strh	r6, [r0], #2	)	@ For Thumb-2, store as two halfwords
595 	stmfd	sp!, {r4 - r6, lr}
597 	add	r5, r0, r1
599 	ldmfd	sp!, {r4 - r6, pc}
602 #include "head-common.S"