arm/mm/proc-v7.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/mm/proc-v7.S
9 #include <linux/arm-smccc.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/pgtable-hwdef.h>
19 #include "proc-macros.S"
22 #include "proc-v7-3level.S"
24 #include "proc-v7-2level.S"
27 .arch armv7-a
48  *	- loc   - location to jump to for soft reset
49  *	- hyp   - indicate if restart occurs in HYP mode
78 	dsb					@ WFI may enter a low-power mode
99 	stmfd	sp!, {r0 - r3}
103 	ldmfd	sp!, {r0 - r3}
108 	stmfd	sp!, {r0 - r3}
112 	ldmfd	sp!, {r0 - r3}
130 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
135 	stmfd	sp!, {r4 - r11, lr}
137 	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
138 	stmia	r0!, {r4 - r5}
142 	mrrc	p15, 1, r5, r7, c2	@ TTB 1
150 	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
151 	stmia	r0, {r5 - r11}
152 	ldmfd	sp!, {r4 - r11, pc}
159 	ldmia	r0!, {r4 - r5}
161 	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
162 	ldmia	r0, {r5 - r11}
168 	mcrr	p15, 1, r5, r7, c2	@ TTB 1
177 	ldr	r5, =NMRR		@ NMRR
179 	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
184 	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
196 	stmfd	sp!, {r4 - r5}
198 	mrc	p15, 0, r5, c15, c0, 0		@ Power register
199 	stmia	r0!, {r4 - r5}
200 	ldmfd	sp!, {r4 - r5}
205 	ldmia	r0!, {r4 - r5}
210 	teq	r5, r10				@ Already restored?
211 	mcrne	p15, 0, r5, c15, c0, 0		@ No, so restore it
224 	dsb					@ WFI may enter a low-power mode
235 	stmfd	sp!, {r6 - r10}
236 	mrc	p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
237 	mrc	p15, 1, r7, c15, c2, 0	@ save CP15 - Aux Func Modes Ctrl 0
238 	mrc	p15, 1, r8, c15, c1, 2	@ save CP15 - Aux Debug Modes Ctrl 2
239 	mrc	p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
240 	mrc	p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
241 	stmia	r0!, {r6 - r10}
242 	ldmfd	sp!, {r6 - r10}
247 	ldmia	r0!, {r6 - r10}
248 	mcr	p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
249 	mcr	p15, 1, r7, c15, c2, 0	@ restore CP15 - Aux Func Modes Ctrl 0
250 	mcr	p15, 1, r8, c15, c1, 2	@ restore CP15 - Aux Debug Modes Ctrl 2
251 	mcr	p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
252 	mcr	p15, 0, r10, c9, c14, 0  @ restore CP15 - PMC
269 	bl	v7_invalidate_l1		@ corrupts {r0-r3, ip, lr}
281  *	r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
283  *	r5: TTBR0 (high word if LPAE)
290  *	- cache type register is implemented
320  *  r1, r2, r4, r5, r9, r13: must be preserved
321  *  r3: contains MIDR rX number in bits 23-20
322  *  r6: contains MIDR rXpY as 8-bit XY number
445 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
455 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
495 	orr	r6, r6, r3, lsr #20-4		@ combine variant and revision
498 	/* Cortex-A8 Errata */
499 	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
503 	/* Cortex-A9 Errata */
504 	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
508 	/* Cortex-A12 Errata */
509 	ldr	r10, =0x00000c0d		@ Cortex-A12 primary part number
513 	/* Cortex-A17 Errata */
514 	ldr	r10, =0x00000c0e		@ Cortex-A17 primary part number
518 	/* Cortex-A15 Errata */
519 	ldr	r10, =0x00000c0f		@ Cortex-A15 primary part number
528 	v7_ttb_setup r10, r4, r5, r8, r3	@ TTBCR, TTBRx setup
549  ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
565 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
589 	@ Cortex-A8 - always needs bpiall switch_mm implementation
604 	@ Cortex-A9 - needs more registers preserved across suspend/resume
620 	@ Cortex-A15 - needs iciallu switch_mm for hardening
672 	 * ARM Ltd. Cortex A5 processor.
679 	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
682 	 * ARM Ltd. Cortex A9 processor.
689 	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
692 	 * ARM Ltd. Cortex A8 processor.
699 	.size	__v7_ca8_proc_info, . - __v7_ca8_proc_info
712 	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
716 	 * ARM Ltd. Cortex R7 processor.
723 	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
726 	 * ARM Ltd. Cortex R8 processor.
733 	.size	__v7_cr8mp_proc_info, . - __v7_cr8mp_proc_info
736 	 * ARM Ltd. Cortex A7 processor.
743 	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
746 	 * ARM Ltd. Cortex A12 processor.
753 	.size	__v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
756 	 * ARM Ltd. Cortex A15 processor.
763 	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
766 	 * Broadcom Corporation Brahma-B15 processor.
773 	.size	__v7_b15mp_proc_info, . - __v7_b15mp_proc_info
776 	 * ARM Ltd. Cortex A17 processor.
783 	.size	__v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
785 	/* ARM Ltd. Cortex A73 processor */
791 	.size	__v7_ca73_proc_info, . - __v7_ca73_proc_info
793 	/* ARM Ltd. Cortex A75 processor */
799 	.size	__v7_ca75_proc_info, . - __v7_ca75_proc_info
815 	.size	__krait_proc_info, . - __krait_proc_info
825 	.size	__v7_proc_info, . - __v7_proc_info