arm/dts/zynqmp-r5.dts

1 // SPDX-License-Identifier: GPL-2.0
3  * dts file for Xilinx ZynqMP R5
10 /dts-v1/;
13 	#address-cells = <1>;
14 	#size-cells = <1>;
15 	compatible = "xlnx,zynqmp-r5";
16 	model = "Xilinx ZynqMP R5";
19 		#address-cells = <0x1>;
20 		#size-cells = <0x0>;
23 			compatible = "arm,cortex-r5";
40 		stdout-path = "serial0:115200n8";
44 		compatible = "fixed-clock";
45 		#clock-cells = <0>;
46 		clock-frequency = <100000000>;
47 		u-boot,dm-pre-reloc;
51 		u-boot,dm-pre-reloc;
52 		compatible = "simple-bus";
53 		#address-cells = <1>;
54 		#size-cells = <1>;
61 			timer-width = <32>;
66 			u-boot,dm-pre-reloc;
67 			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
69 			clock-names = "uart_clk", "pclk";