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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992.dtsi29 reg = <0xfdd00000 0x2000>, <0xfec00000 0x100000>;
31 gmu-sram@0 {
32 reg = <0x0 0x80000>;
H A Dmsm8994.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
62 reg = <0x0 0x1>;
70 reg = <0x0 0x2>;
78 reg = <0x0 0x3>;
86 reg = <0x0 0x100>;
99 reg = <0x0 0x101>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,rk3568-cru.yaml63 reg = <0xfdd00000 0x1000>;
70 reg = <0xfdd20000 0x1000>;
/openbmc/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,ocmem.yaml86 "-sram@[0-9a-f]+$":
106 reg = <0xfdd00000 0x2000>,
107 <0xfec00000 0x180000>;
118 ranges = <0 0xfec00000 0x100000>;
120 gmu-sram@0 {
121 reg = <0x0 0x100000>;
/openbmc/linux/arch/arm/mach-dove/
H A Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/openbmc/u-boot/include/configs/
H A Dt4qds.h16 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
40 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
48 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
49 #define CONFIG_SYS_MEMTEST_END 0x00400000
54 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
64 #define CONFIG_SYS_DCSRBAR 0xf0000000
65 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
71 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
82 #define CONFIG_SYS_FLASH_BASE 0xe0000000
83 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
[all …]
H A Dcyrus.h27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
53 #define CONFIG_SYS_MMC_ENV_DEV 0
54 #define CONFIG_ENV_SIZE 0x2000
68 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
80 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
81 #define CONFIG_SYS_MEMTEST_END 0x00400000
88 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
96 #define CONFIG_SYS_DCSRBAR 0xf0000000
97 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
[all …]
H A Dcorenet_ds.h17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
64 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
65 #define CONFIG_ENV_SECT_SIZE 0x10000
68 #define CONFIG_SYS_MMC_ENV_DEV 0
[all …]
H A DT1040QDS.h32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
44 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
62 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
63 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
64 #define CONFIG_ENV_SECT_SIZE 0x10000
66 #define CONFIG_SYS_MMC_ENV_DEV 0
67 #define CONFIG_ENV_SIZE 0x2000
74 #define CONFIG_ENV_SIZE 0x2000
75 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
78 #define CONFIG_ENV_SIZE 0x2000
[all …]
H A DT4240RDB.h21 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
25 #define CONFIG_SPL_PAD_TO 0x40000
26 #define CONFIG_SPL_MAX_SIZE 0x28000
27 #define RESET_VECTOR_OFFSET 0x27FFC
28 #define BOOT_PAGE_OFFSET 0x27000
31 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
33 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
34 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
[all …]
H A DT102xQDS.h32 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
33 #define CONFIG_SPL_PAD_TO 0x40000
34 #define CONFIG_SPL_MAX_SIZE 0x28000
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
54 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
[all …]
H A DB4860QDS.h17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
20 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
21 #define CONFIG_SPL_PAD_TO 0x40000
22 #define CONFIG_SPL_MAX_SIZE 0x28000
23 #define RESET_VECTOR_OFFSET 0x27FFC
24 #define BOOT_PAGE_OFFSET 0x27000
26 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
27 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
[all …]
H A DT208xRDB.h33 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
34 #define CONFIG_SPL_PAD_TO 0x40000
35 #define CONFIG_SPL_MAX_SIZE 0x28000
36 #define RESET_VECTOR_OFFSET 0x27FFC
37 #define BOOT_PAGE_OFFSET 0x27000
46 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
55 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
[all …]
H A DT208xQDS.h39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40 #define CONFIG_SPL_PAD_TO 0x40000
41 #define CONFIG_SPL_MAX_SIZE 0x28000
42 #define RESET_VECTOR_OFFSET 0x27FFC
43 #define BOOT_PAGE_OFFSET 0x27000
52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
53 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
[all …]
H A DT102xRDB.h35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
36 #define CONFIG_SPL_PAD_TO 0x40000
37 #define CONFIG_SPL_MAX_SIZE 0x28000
38 #define RESET_VECTOR_OFFSET 0x27FFC
39 #define BOOT_PAGE_OFFSET 0x27000
48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
49 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
61 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
[all …]
H A DT104xRDB.h24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
25 #define CONFIG_SPL_PAD_TO 0x40000
26 #define CONFIG_SPL_MAX_SIZE 0x28000
32 #define RESET_VECTOR_OFFSET 0x27FFC
33 #define BOOT_PAGE_OFFSET 0x27000
47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
48 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml20 … - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'
26 - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
32 - pattern: '^amd,imageon-200\.[0-1]$'
130 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
206 pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
233 reg = <0xfdb00000 0x10000>;
247 iommus = <&gpu_iommu 0>;
254 reg = <0xfdd00000 0x2000>,
255 <0xfec00000 0x180000>;
264 ranges = <0 0xfec00000 0x100000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8226.dtsi23 memory@0 {
25 reg = <0x0 0x0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
61 qcom,ipc = <&apcs 8 0>;
113 reg = <0x3000000 0x100000>;
118 reg = <0x0dc00000 0x1900000>;
141 qcom,local-pid = <0>;
165 reg = <0xf9000000 0x1000>,
166 <0xf9002000 0x1000>;
[all …]
H A Dqcom-msm8974.dtsi20 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #size-cells = <0>;
34 interrupts = <GIC_PPI 9 0xf04>;
36 CPU0: cpu@0 {
40 reg = <0>;
108 reg = <0x0 0x0>;
113 interrupts = <GIC_PPI 7 0xf04>;
121 qcom,ipc = <&apcs 8 0>;
144 reg = <0x08000000 0x5100000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk356x.dtsi50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
65 reg = <0x0 0x100>;
74 reg = <0x0 0x200>;
83 reg = <0x0 0x300>;
90 cpu0_opp_table: opp-table-0 {
140 arm,smc-id = <0x82000010>;
143 #size-cells = <0>;
[all …]