Lines Matching +full:0 +full:xfdd00000
17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
20 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
21 #define CONFIG_SPL_PAD_TO 0x40000
22 #define CONFIG_SPL_MAX_SIZE 0x28000
23 #define RESET_VECTOR_OFFSET 0x27FFC
24 #define BOOT_PAGE_OFFSET 0x27000
26 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
27 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
68 #define I2C_MUX_PCA_ADDR 0x77
72 #define I2C_CH_DEFAULT 0x8
73 #define I2C_CH_VSC3316 0xc
74 #define I2C_CH_VSC3308 0xd
76 #define VSC3316_TX_ADDRESS 0x70
77 #define VSC3316_RX_ADDRESS 0x71
78 #define VSC3308_TX_ADDRESS 0x02
79 #define VSC3308_RX_ADDRESS 0x03
83 #define I2C_CH_IDT 0x9
85 #define IDT_SERDES1_ADDRESS 0x6E
86 #define IDT_SERDES2_ADDRESS 0x6C
89 #define I2C_MUX_CH_VOL_MONITOR 0xa
90 #define I2C_VOL_MONITOR_ADDR 0x40
91 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
92 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
96 #define I2C_MUX_CH_DPM 0xa
97 #define I2C_DPM_ADDR 0x28
102 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
103 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
104 #define CONFIG_ENV_SECT_SIZE 0x10000
106 #define CONFIG_SYS_MMC_ENV_DEV 0
107 #define CONFIG_ENV_SIZE 0x2000
110 #define CONFIG_ENV_SIZE 0x2000
113 #define CONFIG_ENV_ADDR 0xffe20000
114 #define CONFIG_ENV_SIZE 0x2000
116 #define CONFIG_ENV_SIZE 0x2000
119 #define CONFIG_ENV_SIZE 0x2000
120 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
138 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
148 #if 0
151 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
152 #define CONFIG_SYS_MEMTEST_END 0x00400000
157 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
168 #define CONFIG_SYS_DCSRBAR 0xf0000000
169 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
175 #define CONFIG_SYS_EEPROM_BUS_NUM 0
176 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
185 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
194 #define CONFIG_SYS_SPD_BUS_NUM 0
195 #define SPD_EEPROM_ADDRESS1 0x51
196 #define SPD_EEPROM_ADDRESS2 0x53
204 #define CONFIG_SYS_FLASH_BASE 0xe0000000
206 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
211 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
213 + 0x8000000) | \
217 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
225 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
226 FTIM0_NOR_TEADC(0x04) | \
227 FTIM0_NOR_TEAHC(0x20))
228 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
229 FTIM1_NOR_TRAD_NOR(0x1A) |\
230 FTIM1_NOR_TSEQRAD_NOR(0x13))
231 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
232 FTIM2_NOR_TCH(0x0E) | \
233 FTIM2_NOR_TWPH(0x0E) | \
234 FTIM2_NOR_TWP(0x1c))
235 #define CONFIG_SYS_NOR_FTIM3 0x0
247 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
251 #define QIXIS_BASE 0xffdf0000
253 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
257 #define QIXIS_LBMAP_SWITCH 0x01
258 #define QIXIS_LBMAP_MASK 0x0f
259 #define QIXIS_LBMAP_SHIFT 0
260 #define QIXIS_LBMAP_DFLTBANK 0x00
261 #define QIXIS_LBMAP_ALTBANK 0x02
262 #define QIXIS_RST_CTL_RESET 0x31
263 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
264 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
265 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
267 #define CONFIG_SYS_CSPR3_EXT (0xf)
273 #define CONFIG_SYS_CSOR3 0x0
275 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
276 FTIM0_GPCM_TEADC(0x0e) | \
277 FTIM0_GPCM_TEAHC(0x0e))
278 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
279 FTIM1_GPCM_TRAD(0x1f))
280 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
281 FTIM2_GPCM_TCH(0x8) | \
282 FTIM2_GPCM_TWP(0x1f))
283 #define CONFIG_SYS_CS3_FTIM3 0x0
289 #define CONFIG_SYS_NAND_BASE 0xff800000
291 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
296 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
314 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
315 FTIM0_NAND_TWP(0x18) | \
316 FTIM0_NAND_TWCHT(0x07) | \
317 FTIM0_NAND_TWH(0x0a))
318 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
319 FTIM1_NAND_TWBE(0x39) | \
320 FTIM1_NAND_TRR(0x0e) | \
321 FTIM1_NAND_TRP(0x18))
322 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
323 FTIM2_NAND_TREH(0x0a) | \
324 FTIM2_NAND_TWHRE(0x1e))
325 #define CONFIG_SYS_NAND_FTIM3 0x0
393 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
395 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
396 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
402 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
403 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
406 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
421 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
426 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
427 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
428 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
429 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
435 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
437 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
438 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
439 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
446 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
453 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
455 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
457 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
459 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
463 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
465 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
467 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
469 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
477 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
478 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
479 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
480 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
485 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
486 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
487 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
490 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
491 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
497 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
499 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
510 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
512 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
517 * Memory space is mapped 1-1, but I/O space must start from 0.
521 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
523 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
524 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
526 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
527 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
529 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
530 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
531 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
533 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
535 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
537 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
542 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
544 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
548 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
549 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
550 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
556 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
558 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
560 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
564 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
565 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
566 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
572 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
581 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
582 * env, so we got 0x110000.
585 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
588 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
590 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
606 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
609 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
611 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
612 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
620 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
621 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
622 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
623 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
633 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
634 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
637 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
638 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/
640 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
641 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
642 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
643 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
671 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
707 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
708 "netdev=eth0\0" \
709 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
710 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
716 "cmp.b $loadaddr $ubootaddr $filesize\0" \
717 "consoledev=ttyS0\0" \
718 "ramdiskaddr=2000000\0" \
719 "ramdiskfile=b4860qds/ramdisk.uboot\0" \
720 "fdtaddr=1e00000\0" \
721 "fdtfile=b4860qds/b4860qds.dtb\0" \
722 "bdev=sda3\0"
729 "cpu 1 release 0x29000000 - - -;" \
730 "cpu 2 release 0x29000000 - - -;" \
731 "cpu 3 release 0x29000000 - - -;" \
732 "cpu 4 release 0x29000000 - - -;" \
733 "cpu 5 release 0x29000000 - - -;" \
734 "cpu 6 release 0x29000000 - - -;" \
735 "cpu 7 release 0x29000000 - - -;" \
736 "go 0x29000000"
739 "setenv bootargs config-addr=0x60000000; " \
740 "bootm 0x01000000 - 0x00f00000"
745 "cpu 1 release 0x01000000 - - -;" \
746 "cpu 2 release 0x01000000 - - -;" \
747 "cpu 3 release 0x01000000 - - -;" \
748 "cpu 4 release 0x01000000 - - -;" \
749 "cpu 5 release 0x01000000 - - -;" \
750 "cpu 6 release 0x01000000 - - -;" \
751 "cpu 7 release 0x01000000 - - -;" \
752 "go 0x01000000"
757 "setenv ramdiskaddr 0x02000000;" \
758 "setenv fdtaddr 0x01e00000;" \
759 "setenv loadaddr 0x1000000;" \