include/configs/t4qds.h

16 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
40 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
48 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
49 #define CONFIG_SYS_MEMTEST_END		0x00400000
54 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
64 #define CONFIG_SYS_DCSRBAR		0xf0000000
65 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
71 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
82 #define CONFIG_SYS_FLASH_BASE	0xe0000000
83 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
96 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
97 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
98 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
103 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
118 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
123 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
124 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
125 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
126 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
131 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
132 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
133 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
134 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
139 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
140 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
141 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
143 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
144 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
145 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
149  * Memory space is mapped 1-1, but I/O space must start from 0.
153 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
154 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
155 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
156 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
157 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
158 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
159 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
160 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
163 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
164 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
165 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
166 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
167 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
168 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
169 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
170 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
173 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
174 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
175 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
176 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
177 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
178 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
179 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
180 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
183 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
184 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
185 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
186 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
187 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
188 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
226 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
251  "setenv bootargs config-addr=0x60000000; "	\
252  "bootm 0x01000000 - 0x00f00000"