Lines Matching +full:0 +full:xfdd00000
32 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
33 #define CONFIG_SPL_PAD_TO 0x40000
34 #define CONFIG_SPL_MAX_SIZE 0x28000
35 #define RESET_VECTOR_OFFSET 0x27FFC
36 #define BOOT_PAGE_OFFSET 0x27000
45 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
46 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
54 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
69 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
71 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
72 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
85 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
94 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
95 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
97 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
98 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
100 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
101 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
108 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
109 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
111 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
112 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
114 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
116 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
117 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
121 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
123 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
125 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
127 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
128 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
132 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
133 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
134 #define CONFIG_ENV_SECT_SIZE 0x10000
136 #define CONFIG_SYS_MMC_ENV_DEV 0
137 #define CONFIG_ENV_SIZE 0x2000
138 #define CONFIG_ENV_OFFSET (512 * 0x800)
140 #define CONFIG_ENV_SIZE 0x2000
143 #define CONFIG_ENV_ADDR 0xffe20000
144 #define CONFIG_ENV_SIZE 0x2000
146 #define CONFIG_ENV_SIZE 0x2000
149 #define CONFIG_ENV_SIZE 0x2000
150 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
171 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
174 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
175 #define CONFIG_SYS_MEMTEST_END 0x00400000
180 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
191 #define CONFIG_SYS_DCSRBAR 0xf0000000
192 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
198 #define CONFIG_SYS_EEPROM_BUS_NUM 0
199 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
208 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
214 #define CONFIG_SYS_SPD_BUS_NUM 0
215 #define SPD_EEPROM_ADDRESS 0x51
222 #define CONFIG_SYS_FLASH_BASE 0xe0000000
224 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
229 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
231 + 0x8000000) | \
235 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
243 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
244 FTIM0_NOR_TEADC(0x5) | \
245 FTIM0_NOR_TEAHC(0x5))
246 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
247 FTIM1_NOR_TRAD_NOR(0x1A) |\
248 FTIM1_NOR_TSEQRAD_NOR(0x13))
249 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
250 FTIM2_NOR_TCH(0x4) | \
251 FTIM2_NOR_TWPH(0x0E) | \
252 FTIM2_NOR_TWP(0x1c))
253 #define CONFIG_SYS_NOR_FTIM3 0x0
265 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
267 #define QIXIS_BASE 0xffdf0000
269 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
273 #define QIXIS_LBMAP_SWITCH 0x06
274 #define QIXIS_LBMAP_MASK 0x0f
275 #define QIXIS_LBMAP_SHIFT 0
276 #define QIXIS_LBMAP_DFLTBANK 0x00
277 #define QIXIS_LBMAP_ALTBANK 0x04
278 #define QIXIS_RST_CTL_RESET 0x31
279 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
280 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
281 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
282 #define QIXIS_RST_FORCE_MEM 0x01
284 #define CONFIG_SYS_CSPR3_EXT (0xf)
290 #define CONFIG_SYS_CSOR3 0x0
292 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
293 FTIM0_GPCM_TEADC(0x0e) | \
294 FTIM0_GPCM_TEAHC(0x0e))
295 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
296 FTIM1_GPCM_TRAD(0x3f))
297 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
298 FTIM2_GPCM_TCH(0x8) | \
299 FTIM2_GPCM_TWP(0x1f))
300 #define CONFIG_SYS_CS3_FTIM3 0x0
303 #define CONFIG_SYS_NAND_BASE 0xff800000
305 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
309 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
327 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
328 FTIM0_NAND_TWP(0x18) | \
329 FTIM0_NAND_TWCHT(0x07) | \
330 FTIM0_NAND_TWH(0x0a))
331 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
332 FTIM1_NAND_TWBE(0x39) | \
333 FTIM1_NAND_TRR(0x0e) | \
334 FTIM1_NAND_TRP(0x18))
335 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
336 FTIM2_NAND_TREH(0x0a) | \
337 FTIM2_NAND_TWHRE(0x1e))
338 #define CONFIG_SYS_NAND_FTIM3 0x0
413 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
415 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
422 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
426 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
438 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
443 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
444 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
445 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
446 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
453 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
469 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
471 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
472 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
473 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
475 #define I2C_MUX_PCA_ADDR 0x77
476 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
477 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
478 #define I2C_RETIMER_ADDR 0x18
481 #define I2C_MUX_CH_DEFAULT 0x8
482 #define I2C_MUX_CH_DIU 0xC
483 #define I2C_MUX_CH5 0xD
484 #define I2C_MUX_CH7 0xF
487 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
488 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
495 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
503 * Memory space is mapped 1-1, but I/O space must start from 0.
515 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
517 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
518 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
520 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
521 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
523 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
524 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
525 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
527 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
529 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
531 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
536 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
538 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
539 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
541 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
542 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
544 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
545 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
546 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
548 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
550 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
552 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
557 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
559 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
560 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
562 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
563 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
565 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
566 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
567 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
569 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
571 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
573 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
611 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
613 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
617 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
618 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
619 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
625 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
627 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
629 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
633 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
634 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
635 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
641 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
649 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
650 * env, so we got 0x110000.
653 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
654 #define CONFIG_SYS_QE_FW_ADDR 0x130000
657 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
659 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
662 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
663 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
677 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
680 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
681 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
683 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
684 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
693 #define RGMII_PHY1_ADDR 0x1
694 #define RGMII_PHY2_ADDR 0x2
695 #define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
696 #define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
697 #define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
698 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
699 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
700 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
701 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
721 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
745 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
746 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
747 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
748 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
749 "fdtfile=t1024qds/t1024qds.dtb\0" \
750 "netdev=eth0\0" \
751 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
752 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
753 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
759 "cmp.b $loadaddr $ubootaddr $filesize\0" \
760 "consoledev=ttyS0\0" \
761 "ramdiskaddr=2000000\0" \
762 "fdtaddr=d00000\0" \
763 "bdev=sda3\0"
768 "setenv ramdiskaddr 0x02000000;" \
769 "setenv fdtaddr 0x00c00000;" \
770 "setenv loadaddr 0x1000000;" \