Lines Matching +full:0 +full:xfdd00000
39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
40 #define CONFIG_SPL_PAD_TO 0x40000
41 #define CONFIG_SPL_MAX_SIZE 0x28000
42 #define RESET_VECTOR_OFFSET 0x27FFC
43 #define BOOT_PAGE_OFFSET 0x27000
52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
53 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
65 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
84 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
86 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
87 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
106 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
108 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
109 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
113 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
124 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
128 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
129 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
130 #define CONFIG_ENV_SECT_SIZE 0x10000
132 #define CONFIG_SYS_MMC_ENV_DEV 0
133 #define CONFIG_ENV_SIZE 0x2000
134 #define CONFIG_ENV_OFFSET (512 * 0x800)
136 #define CONFIG_ENV_SIZE 0x2000
139 #define CONFIG_ENV_ADDR 0xffe20000
140 #define CONFIG_ENV_SIZE 0x2000
142 #define CONFIG_ENV_SIZE 0x2000
145 #define CONFIG_ENV_SIZE 0x2000
146 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
160 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
170 #define CONFIG_SYS_DCSRBAR 0xf0000000
171 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
176 #define CONFIG_SYS_EEPROM_BUS_NUM 0
177 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
184 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
189 #define CONFIG_SYS_SPD_BUS_NUM 0
191 #define SPD_EEPROM_ADDRESS1 0x51
192 #define SPD_EEPROM_ADDRESS2 0x52
199 #define CONFIG_SYS_FLASH_BASE 0xe0000000
200 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
201 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
203 + 0x8000000) | \
207 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
216 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
217 FTIM0_NOR_TEADC(0x5) | \
218 FTIM0_NOR_TEAHC(0x5))
219 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
220 FTIM1_NOR_TRAD_NOR(0x1A) |\
221 FTIM1_NOR_TSEQRAD_NOR(0x13))
222 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
223 FTIM2_NOR_TCH(0x4) | \
224 FTIM2_NOR_TWPH(0x0E) | \
225 FTIM2_NOR_TWP(0x1c))
226 #define CONFIG_SYS_NOR_FTIM3 0x0
238 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
241 #define QIXIS_BASE 0xffdf0000
243 #define QIXIS_LBMAP_MASK 0x0f
244 #define QIXIS_LBMAP_SHIFT 0
245 #define QIXIS_LBMAP_DFLTBANK 0x00
246 #define QIXIS_LBMAP_ALTBANK 0x04
247 #define QIXIS_LBMAP_NAND 0x09
248 #define QIXIS_LBMAP_SD 0x00
249 #define QIXIS_RCW_SRC_NAND 0x104
250 #define QIXIS_RCW_SRC_SD 0x040
251 #define QIXIS_RST_CTL_RESET 0x83
252 #define QIXIS_RST_FORCE_MEM 0x1
253 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
254 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
255 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
256 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
258 #define CONFIG_SYS_CSPR3_EXT (0xf)
264 #define CONFIG_SYS_CSOR3 0x0
266 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
267 FTIM0_GPCM_TEADC(0x0e) | \
268 FTIM0_GPCM_TEAHC(0x0e))
269 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
270 FTIM1_GPCM_TRAD(0x3f))
271 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
272 FTIM2_GPCM_TCH(0x8) | \
273 FTIM2_GPCM_TWP(0x1f))
274 #define CONFIG_SYS_CS3_FTIM3 0x0
278 #define CONFIG_SYS_NAND_BASE 0xff800000
279 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
281 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
299 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
300 FTIM0_NAND_TWP(0x18) | \
301 FTIM0_NAND_TWCHT(0x07) | \
302 FTIM0_NAND_TWH(0x0a))
303 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
304 FTIM1_NAND_TWBE(0x39) | \
305 FTIM1_NAND_TRR(0x0e) | \
306 FTIM1_NAND_TRP(0x18))
307 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
308 FTIM2_NAND_TREH(0x0a) | \
309 FTIM2_NAND_TWHRE(0x1e))
310 #define CONFIG_SYS_NAND_FTIM3 0x0
384 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
391 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
403 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
408 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
409 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
416 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
417 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
418 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
419 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
420 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
421 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
422 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
423 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
428 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
429 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
430 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
431 #define I2C_MUX_CH_DEFAULT 0x8
433 #define I2C_MUX_CH_VOL_MONITOR 0xa
436 #define I2C_VOL_MONITOR_ADDR 0x40
437 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
438 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
454 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
455 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
456 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
457 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
458 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
459 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
464 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
465 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
466 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
467 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
472 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
473 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
474 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
477 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
478 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
484 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
486 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
495 * Memory space is mapped 1-1, but I/O space must start from 0.
505 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
506 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
507 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
508 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
509 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
510 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
511 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
512 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
515 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
516 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
517 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
518 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
519 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
520 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
521 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
522 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
525 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
526 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
527 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
528 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
529 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
530 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
531 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
532 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
535 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
536 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
537 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
538 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
539 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
540 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
541 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
551 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
552 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
553 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
554 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
555 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
561 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
563 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
564 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
565 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
566 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
567 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
573 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
585 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
586 * env, so we got 0x110000.
589 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
592 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
594 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
597 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
610 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
613 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
615 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
616 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
624 #define RGMII_PHY1_ADDR 0x1
625 #define RGMII_PHY2_ADDR 0x2
626 #define FM1_10GEC1_PHY_ADDR 0x3
627 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
628 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
629 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
630 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
684 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
714 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
715 "netdev=eth0\0" \
716 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
717 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
723 "cmp.b $loadaddr $ubootaddr $filesize\0" \
724 "consoledev=ttyS0\0" \
725 "ramdiskaddr=2000000\0" \
726 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
727 "fdtaddr=1e00000\0" \
728 "fdtfile=t2080qds/t2080qds.dtb\0" \
729 "bdev=sda3\0"
738 "cpu 1 release 0x29000000 - - -;" \
739 "cpu 2 release 0x29000000 - - -;" \
740 "cpu 3 release 0x29000000 - - -;" \
741 "cpu 4 release 0x29000000 - - -;" \
742 "cpu 5 release 0x29000000 - - -;" \
743 "cpu 6 release 0x29000000 - - -;" \
744 "cpu 7 release 0x29000000 - - -;" \
745 "go 0x29000000"
748 "setenv bootargs config-addr=0x60000000; " \
749 "bootm 0x01000000 - 0x00f00000"
754 "cpu 1 release 0x01000000 - - -;" \
755 "cpu 2 release 0x01000000 - - -;" \
756 "cpu 3 release 0x01000000 - - -;" \
757 "cpu 4 release 0x01000000 - - -;" \
758 "cpu 5 release 0x01000000 - - -;" \
759 "cpu 6 release 0x01000000 - - -;" \
760 "cpu 7 release 0x01000000 - - -;" \
761 "go 0x01000000"
766 "setenv ramdiskaddr 0x02000000;" \
767 "setenv fdtaddr 0x00c00000;" \
768 "setenv loadaddr 0x1000000;" \