Lines Matching +full:0 +full:xfdd00000
24 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
25 #define CONFIG_SPL_PAD_TO 0x40000
26 #define CONFIG_SPL_MAX_SIZE 0x28000
32 #define RESET_VECTOR_OFFSET 0x27FFC
33 #define BOOT_PAGE_OFFSET 0x27000
47 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
48 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
75 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
78 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
79 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
109 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
111 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
112 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
150 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
167 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
168 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
169 #define CONFIG_ENV_SECT_SIZE 0x10000
171 #define CONFIG_SYS_MMC_ENV_DEV 0
172 #define CONFIG_ENV_SIZE 0x2000
173 #define CONFIG_ENV_OFFSET (512 * 0x800)
179 #define CONFIG_ENV_SIZE 0x2000
183 #define CONFIG_ENV_SIZE 0x2000
184 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
200 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
208 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
209 #define CONFIG_SYS_MEMTEST_END 0x00400000
214 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
220 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
230 #define CONFIG_SYS_DCSRBAR 0xf0000000
231 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
237 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
245 #define CONFIG_SYS_SPD_BUS_NUM 0
246 #define SPD_EEPROM_ADDRESS 0x51
253 #define CONFIG_SYS_FLASH_BASE 0xe8000000
254 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
256 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
266 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
270 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
271 FTIM0_NOR_TEADC(0x5) | \
272 FTIM0_NOR_TEAHC(0x5))
273 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
274 FTIM1_NOR_TRAD_NOR(0x1A) |\
275 FTIM1_NOR_TSEQRAD_NOR(0x13))
276 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
277 FTIM2_NOR_TCH(0x4) | \
278 FTIM2_NOR_TWPH(0x0E) | \
279 FTIM2_NOR_TWP(0x1c))
280 #define CONFIG_SYS_NOR_FTIM3 0x0
294 #define CPLD_LBMAP_MASK 0x3F
295 #define CPLD_BANK_SEL_MASK 0x07
296 #define CPLD_BANK_OVERRIDE 0x40
297 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
298 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
299 #define CPLD_LBMAP_RESET 0xFF
300 #define CPLD_LBMAP_SHIFT 0x03
303 #define CPLD_DIU_SEL_DFP 0x80
305 #define CPLD_DIU_SEL_DFP 0xc0
309 #define CPLD_INT_MASK_ALL 0xFF
310 #define CPLD_INT_MASK_THERM 0x80
311 #define CPLD_INT_MASK_DVI_DFP 0x40
312 #define CPLD_INT_MASK_QSGMII1 0x20
313 #define CPLD_INT_MASK_QSGMII2 0x10
314 #define CPLD_INT_MASK_SGMI1 0x08
315 #define CPLD_INT_MASK_SGMI2 0x04
316 #define CPLD_INT_MASK_TDMR1 0x02
317 #define CPLD_INT_MASK_TDMR2 0x01
320 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
321 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
322 #define CONFIG_SYS_CSPR2_EXT (0xf)
328 #define CONFIG_SYS_CSOR2 0x0
330 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
331 FTIM0_GPCM_TEADC(0x0e) | \
332 FTIM0_GPCM_TEAHC(0x0e))
333 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
334 FTIM1_GPCM_TRAD(0x1f))
335 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
336 FTIM2_GPCM_TCH(0x8) | \
337 FTIM2_GPCM_TWP(0x1f))
338 #define CONFIG_SYS_CS2_FTIM3 0x0
342 #define CONFIG_SYS_NAND_BASE 0xff800000
343 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
345 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
363 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
364 FTIM0_NAND_TWP(0x18) | \
365 FTIM0_NAND_TWCHT(0x07) | \
366 FTIM0_NAND_TWH(0x0a))
367 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
368 FTIM1_NAND_TWBE(0x39) | \
369 FTIM1_NAND_TRR(0x0e) | \
370 FTIM1_NAND_TRP(0x18))
371 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
372 FTIM2_NAND_TREH(0x0a) | \
373 FTIM2_NAND_TWHRE(0x1e))
374 #define CONFIG_SYS_NAND_FTIM3 0x0
439 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
441 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
446 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
461 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
466 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
467 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
468 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
469 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
477 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
490 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
491 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
492 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
493 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
494 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
495 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
496 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
497 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
500 #define I2C_MUX_PCA_ADDR 0x70
501 #define I2C_MUX_CH_DEFAULT 0x8
507 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
508 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
515 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
518 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
527 * Memory space is mapped 1-1, but I/O space must start from 0.
533 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
534 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
535 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
536 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
537 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
538 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
539 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
540 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
545 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
546 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
547 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
548 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
549 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
550 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
551 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
552 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
557 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
558 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
559 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
560 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
561 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
562 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
563 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
564 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
569 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
570 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
571 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
572 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
573 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
574 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
575 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
576 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
612 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
613 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
614 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
615 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
616 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
622 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
624 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
625 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
626 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
627 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
628 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
634 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
645 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
646 * env, so we got 0x110000.
649 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
652 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
654 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
657 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
663 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
667 #define CONFIG_SYS_QE_FW_ADDR 0x130000
669 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
673 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
676 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
677 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
688 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
690 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
692 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
693 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
694 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
698 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
699 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
701 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
702 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
709 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
710 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
712 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
713 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
729 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
781 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
782 "netdev=eth0\0" \
783 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
784 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
785 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
791 "cmp.b $loadaddr $ubootaddr $filesize\0" \
792 "consoledev=ttyS0\0" \
793 "ramdiskaddr=2000000\0" \
794 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
795 "fdtaddr=1e00000\0" \
796 "fdtfile=" __stringify(FDTFILE) "\0" \
797 "bdev=sda3\0"
802 "setenv ramdiskaddr 0x02000000;" \
803 "setenv fdtaddr 0x00c00000;" \
804 "setenv loadaddr 0x1000000;" \