Lines Matching +full:0 +full:xfdd00000
17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
40 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
42 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
63 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
64 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
65 #define CONFIG_ENV_SECT_SIZE 0x10000
68 #define CONFIG_SYS_MMC_ENV_DEV 0
69 #define CONFIG_ENV_SIZE 0x2000
75 #define CONFIG_ENV_ADDR 0xffe20000
76 #define CONFIG_ENV_SIZE 0x2000
78 #define CONFIG_ENV_SIZE 0x2000
81 #define CONFIG_ENV_SIZE 0x2000
82 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
97 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
108 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
109 #define CONFIG_SYS_MEMTEST_END 0x00400000
116 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
124 #define CONFIG_SYS_DCSRBAR 0xf0000000
125 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
131 #define CONFIG_SYS_EEPROM_BUS_NUM 0
132 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
139 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
148 #define SPD_EEPROM_ADDRESS1 0x51
149 #define SPD_EEPROM_ADDRESS2 0x52
160 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
162 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
168 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
170 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
175 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
177 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
179 #define PIXIS_BASE_PHYS 0xfffdf0000ull
185 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
188 #define PIXIS_LBMAP_MASK 0xf0
190 #define PIXIS_LBMAP_ALTBANK 0x40
208 #define CONFIG_SYS_NAND_BASE 0xffa00000
210 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
225 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
252 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_…
259 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
261 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
269 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
272 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
286 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
293 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
294 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
300 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
301 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
303 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
304 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
309 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
311 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
313 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
315 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
317 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
319 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
321 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
323 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
329 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
330 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
331 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
332 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
337 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
338 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
339 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
342 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
343 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
349 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
351 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
360 * Memory space is mapped 1-1, but I/O space must start from 0.
364 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
366 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
367 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
369 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
370 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
372 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
373 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
374 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
376 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
378 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
380 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
383 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
385 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
386 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
388 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
389 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
391 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
392 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
393 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
395 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
397 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
399 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
402 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
404 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
405 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
407 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
408 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
410 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
411 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
412 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
414 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
416 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
418 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
421 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
422 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
423 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
424 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
425 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
426 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
430 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
432 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
436 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
437 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
438 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
444 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
446 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
448 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
452 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
453 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
454 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
460 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
467 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
468 * env, so we got 0x110000.
471 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
474 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
476 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
492 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
495 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
497 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
498 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
527 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
528 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
529 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
530 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
533 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
534 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
535 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
536 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
537 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
568 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
602 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
603 "netdev=eth0\0" \
604 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
605 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
611 "cmp.b $loadaddr $ubootaddr $filesize\0" \
612 "consoledev=ttyS0\0" \
613 "ramdiskaddr=2000000\0" \
614 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
615 "fdtaddr=1e00000\0" \
616 "fdtfile=p4080ds/p4080ds.dtb\0" \
617 "bdev=sda3\0"