1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 248c6f328SShengzhou Liu /* 348c6f328SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 448c6f328SShengzhou Liu */ 548c6f328SShengzhou Liu 648c6f328SShengzhou Liu /* 748c6f328SShengzhou Liu * T1024/T1023 RDB board configuration file 848c6f328SShengzhou Liu */ 948c6f328SShengzhou Liu 1048c6f328SShengzhou Liu #ifndef __T1024RDB_H 1148c6f328SShengzhou Liu #define __T1024RDB_H 1248c6f328SShengzhou Liu 1348c6f328SShengzhou Liu /* High Level Configuration Options */ 1448c6f328SShengzhou Liu #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 1548c6f328SShengzhou Liu #define CONFIG_ENABLE_36BIT_PHYS 1648c6f328SShengzhou Liu 1748c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 1848c6f328SShengzhou Liu #define CONFIG_ADDR_MAP 1 1948c6f328SShengzhou Liu #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 2048c6f328SShengzhou Liu #endif 2148c6f328SShengzhou Liu 2248c6f328SShengzhou Liu #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 2351370d56SYork Sun #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 2448c6f328SShengzhou Liu 2548c6f328SShengzhou Liu #define CONFIG_ENV_OVERWRITE 2648c6f328SShengzhou Liu 2748c6f328SShengzhou Liu /* support deep sleep */ 28e5d5f5a8SYork Sun #ifdef CONFIG_ARCH_T1024 2948c6f328SShengzhou Liu #define CONFIG_DEEP_SLEEP 30e8a7f1c3SShengzhou Liu #endif 3148c6f328SShengzhou Liu 3248c6f328SShengzhou Liu #ifdef CONFIG_RAMBOOT_PBL 3348c6f328SShengzhou Liu #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 3448c6f328SShengzhou Liu #define CONFIG_SPL_FLUSH_IMAGE 3548c6f328SShengzhou Liu #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 3648c6f328SShengzhou Liu #define CONFIG_SPL_PAD_TO 0x40000 3748c6f328SShengzhou Liu #define CONFIG_SPL_MAX_SIZE 0x28000 3848c6f328SShengzhou Liu #define RESET_VECTOR_OFFSET 0x27FFC 3948c6f328SShengzhou Liu #define BOOT_PAGE_OFFSET 0x27000 4048c6f328SShengzhou Liu #ifdef CONFIG_SPL_BUILD 4148c6f328SShengzhou Liu #define CONFIG_SPL_SKIP_RELOCATE 4248c6f328SShengzhou Liu #define CONFIG_SPL_COMMON_INIT_DDR 4348c6f328SShengzhou Liu #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 4448c6f328SShengzhou Liu #endif 4548c6f328SShengzhou Liu 4648c6f328SShengzhou Liu #ifdef CONFIG_NAND 4748c6f328SShengzhou Liu #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 48f49b8c1bStang yuantian #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 49f49b8c1bStang yuantian #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 5048c6f328SShengzhou Liu #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 5148c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 52960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 53ec90ac73SZhao Qiang #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 549082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 55ec90ac73SZhao Qiang #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 56ec90ac73SZhao Qiang #endif 5748c6f328SShengzhou Liu #define CONFIG_SPL_NAND_BOOT 5848c6f328SShengzhou Liu #endif 5948c6f328SShengzhou Liu 6048c6f328SShengzhou Liu #ifdef CONFIG_SPIFLASH 61f49b8c1bStang yuantian #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 6248c6f328SShengzhou Liu #define CONFIG_SPL_SPI_FLASH_MINIMAL 6348c6f328SShengzhou Liu #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 64f49b8c1bStang yuantian #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 65f49b8c1bStang yuantian #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 6648c6f328SShengzhou Liu #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 6748c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 6848c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 6948c6f328SShengzhou Liu #define CONFIG_SYS_MPC85XX_NO_RESETVEC 7048c6f328SShengzhou Liu #endif 71960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 72ec90ac73SZhao Qiang #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 739082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 74ec90ac73SZhao Qiang #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 75ec90ac73SZhao Qiang #endif 7648c6f328SShengzhou Liu #define CONFIG_SPL_SPI_BOOT 7748c6f328SShengzhou Liu #endif 7848c6f328SShengzhou Liu 7948c6f328SShengzhou Liu #ifdef CONFIG_SDCARD 80f49b8c1bStang yuantian #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 8148c6f328SShengzhou Liu #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 82f49b8c1bStang yuantian #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 83f49b8c1bStang yuantian #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 8448c6f328SShengzhou Liu #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 8548c6f328SShengzhou Liu #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 8648c6f328SShengzhou Liu #ifndef CONFIG_SPL_BUILD 8748c6f328SShengzhou Liu #define CONFIG_SYS_MPC85XX_NO_RESETVEC 8848c6f328SShengzhou Liu #endif 89960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 90ec90ac73SZhao Qiang #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 919082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 92ec90ac73SZhao Qiang #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 93ec90ac73SZhao Qiang #endif 9448c6f328SShengzhou Liu #define CONFIG_SPL_MMC_BOOT 9548c6f328SShengzhou Liu #endif 9648c6f328SShengzhou Liu 9748c6f328SShengzhou Liu #endif /* CONFIG_RAMBOOT_PBL */ 9848c6f328SShengzhou Liu 9948c6f328SShengzhou Liu #ifndef CONFIG_RESET_VECTOR_ADDRESS 10048c6f328SShengzhou Liu #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 10148c6f328SShengzhou Liu #endif 10248c6f328SShengzhou Liu 10348c6f328SShengzhou Liu /* PCIe Boot - Master */ 10448c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_MASTER 10548c6f328SShengzhou Liu /* 10648c6f328SShengzhou Liu * for slave u-boot IMAGE instored in master memory space, 10748c6f328SShengzhou Liu * PHYS must be aligned based on the SIZE 10848c6f328SShengzhou Liu */ 10948c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 11048c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 11148c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 11248c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 11348c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 11448c6f328SShengzhou Liu #else 11548c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 11648c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 11748c6f328SShengzhou Liu #endif 11848c6f328SShengzhou Liu /* 11948c6f328SShengzhou Liu * for slave UCODE and ENV instored in master memory space, 12048c6f328SShengzhou Liu * PHYS must be aligned based on the SIZE 12148c6f328SShengzhou Liu */ 12248c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 12348c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 12448c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 12548c6f328SShengzhou Liu #else 12648c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 12748c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 12848c6f328SShengzhou Liu #endif 12948c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 13048c6f328SShengzhou Liu /* slave core release by master*/ 13148c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 13248c6f328SShengzhou Liu #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 13348c6f328SShengzhou Liu 13448c6f328SShengzhou Liu /* PCIe Boot - Slave */ 13548c6f328SShengzhou Liu #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 13648c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 13748c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 13848c6f328SShengzhou Liu (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 13948c6f328SShengzhou Liu /* Set 1M boot space for PCIe boot */ 14048c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 14148c6f328SShengzhou Liu #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 14248c6f328SShengzhou Liu (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 14348c6f328SShengzhou Liu #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 14448c6f328SShengzhou Liu #endif 14548c6f328SShengzhou Liu 14648c6f328SShengzhou Liu #if defined(CONFIG_SPIFLASH) 14748c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 14848c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 149960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 15048c6f328SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x10000 1519082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 152e8a7f1c3SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x40000 153e8a7f1c3SShengzhou Liu #endif 15448c6f328SShengzhou Liu #elif defined(CONFIG_SDCARD) 15548c6f328SShengzhou Liu #define CONFIG_SYS_MMC_ENV_DEV 0 15648c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 15748c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET (512 * 0x800) 15848c6f328SShengzhou Liu #elif defined(CONFIG_NAND) 15948c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 160960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 16148c6f328SShengzhou Liu #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 1629082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 163e8a7f1c3SShengzhou Liu #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 164e8a7f1c3SShengzhou Liu #endif 16548c6f328SShengzhou Liu #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 16648c6f328SShengzhou Liu #define CONFIG_ENV_ADDR 0xffe20000 16748c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 16848c6f328SShengzhou Liu #elif defined(CONFIG_ENV_IS_NOWHERE) 16948c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 17048c6f328SShengzhou Liu #else 17148c6f328SShengzhou Liu #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 17248c6f328SShengzhou Liu #define CONFIG_ENV_SIZE 0x2000 17348c6f328SShengzhou Liu #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 17448c6f328SShengzhou Liu #endif 17548c6f328SShengzhou Liu 17648c6f328SShengzhou Liu #ifndef __ASSEMBLY__ 17748c6f328SShengzhou Liu unsigned long get_board_sys_clk(void); 17848c6f328SShengzhou Liu unsigned long get_board_ddr_clk(void); 17948c6f328SShengzhou Liu #endif 18048c6f328SShengzhou Liu 18148c6f328SShengzhou Liu #define CONFIG_SYS_CLK_FREQ 100000000 182e8a7f1c3SShengzhou Liu #define CONFIG_DDR_CLK_FREQ 100000000 18348c6f328SShengzhou Liu 18448c6f328SShengzhou Liu /* 18548c6f328SShengzhou Liu * These can be toggled for performance analysis, otherwise use default. 18648c6f328SShengzhou Liu */ 18748c6f328SShengzhou Liu #define CONFIG_SYS_CACHE_STASHING 18848c6f328SShengzhou Liu #define CONFIG_BACKSIDE_L2_CACHE 18948c6f328SShengzhou Liu #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 19048c6f328SShengzhou Liu #define CONFIG_BTB /* toggle branch predition */ 19148c6f328SShengzhou Liu #define CONFIG_DDR_ECC 19248c6f328SShengzhou Liu #ifdef CONFIG_DDR_ECC 19348c6f328SShengzhou Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 19448c6f328SShengzhou Liu #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 19548c6f328SShengzhou Liu #endif 19648c6f328SShengzhou Liu 19748c6f328SShengzhou Liu #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 19848c6f328SShengzhou Liu #define CONFIG_SYS_MEMTEST_END 0x00400000 19948c6f328SShengzhou Liu 20048c6f328SShengzhou Liu /* 20148c6f328SShengzhou Liu * Config the L3 Cache as L3 SRAM 20248c6f328SShengzhou Liu */ 20348c6f328SShengzhou Liu #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 20448c6f328SShengzhou Liu #define CONFIG_SYS_L3_SIZE (256 << 10) 20548c6f328SShengzhou Liu #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 20648c6f328SShengzhou Liu #ifdef CONFIG_RAMBOOT_PBL 20748c6f328SShengzhou Liu #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 20848c6f328SShengzhou Liu #endif 20948c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 21048c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 21148c6f328SShengzhou Liu #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 21248c6f328SShengzhou Liu 21348c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 21448c6f328SShengzhou Liu #define CONFIG_SYS_DCSRBAR 0xf0000000 21548c6f328SShengzhou Liu #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 21648c6f328SShengzhou Liu #endif 21748c6f328SShengzhou Liu 21848c6f328SShengzhou Liu /* EEPROM */ 21948c6f328SShengzhou Liu #define CONFIG_ID_EEPROM 22048c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_NXID 22148c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_BUS_NUM 0 22248c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 22348c6f328SShengzhou Liu #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 22448c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 22548c6f328SShengzhou Liu #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 22648c6f328SShengzhou Liu 22748c6f328SShengzhou Liu /* 22848c6f328SShengzhou Liu * DDR Setup 22948c6f328SShengzhou Liu */ 23048c6f328SShengzhou Liu #define CONFIG_VERY_BIG_RAM 23148c6f328SShengzhou Liu #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 23248c6f328SShengzhou Liu #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 23348c6f328SShengzhou Liu #define CONFIG_DIMM_SLOTS_PER_CTLR 1 23448c6f328SShengzhou Liu #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 235960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 23648c6f328SShengzhou Liu #define CONFIG_DDR_SPD 23748c6f328SShengzhou Liu #define CONFIG_SYS_SPD_BUS_NUM 0 23848c6f328SShengzhou Liu #define SPD_EEPROM_ADDRESS 0x51 23948c6f328SShengzhou Liu #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 2409082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 241e8a7f1c3SShengzhou Liu #define CONFIG_SYS_DDR_RAW_TIMING 242e8a7f1c3SShengzhou Liu #define CONFIG_SYS_SDRAM_SIZE 2048 243e8a7f1c3SShengzhou Liu #endif 24448c6f328SShengzhou Liu 24548c6f328SShengzhou Liu /* 24648c6f328SShengzhou Liu * IFC Definitions 24748c6f328SShengzhou Liu */ 24848c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE 0xe8000000 24948c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 25048c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 25148c6f328SShengzhou Liu #else 25248c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 25348c6f328SShengzhou Liu #endif 25448c6f328SShengzhou Liu 25548c6f328SShengzhou Liu #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 25648c6f328SShengzhou Liu #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 25748c6f328SShengzhou Liu CSPR_PORT_SIZE_16 | \ 25848c6f328SShengzhou Liu CSPR_MSEL_NOR | \ 25948c6f328SShengzhou Liu CSPR_V) 26048c6f328SShengzhou Liu #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 26148c6f328SShengzhou Liu 26248c6f328SShengzhou Liu /* NOR Flash Timing Params */ 263960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 26448c6f328SShengzhou Liu #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 2659082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 266ff7ea2d1SShengzhou Liu #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 267e8a7f1c3SShengzhou Liu CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 268e8a7f1c3SShengzhou Liu #endif 26948c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 27048c6f328SShengzhou Liu FTIM0_NOR_TEADC(0x5) | \ 27148c6f328SShengzhou Liu FTIM0_NOR_TEAHC(0x5)) 27248c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 27348c6f328SShengzhou Liu FTIM1_NOR_TRAD_NOR(0x1A) |\ 27448c6f328SShengzhou Liu FTIM1_NOR_TSEQRAD_NOR(0x13)) 27548c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 27648c6f328SShengzhou Liu FTIM2_NOR_TCH(0x4) | \ 27748c6f328SShengzhou Liu FTIM2_NOR_TWPH(0x0E) | \ 27848c6f328SShengzhou Liu FTIM2_NOR_TWP(0x1c)) 27948c6f328SShengzhou Liu #define CONFIG_SYS_NOR_FTIM3 0x0 28048c6f328SShengzhou Liu 28148c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_QUIET_TEST 28248c6f328SShengzhou Liu #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 28348c6f328SShengzhou Liu 28448c6f328SShengzhou Liu #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 28548c6f328SShengzhou Liu #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 28648c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 28748c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 28848c6f328SShengzhou Liu 28948c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_EMPTY_INFO 29048c6f328SShengzhou Liu #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 29148c6f328SShengzhou Liu 292960286b6SYork Sun #ifdef CONFIG_TARGET_T1024RDB 29348c6f328SShengzhou Liu /* CPLD on IFC */ 29448c6f328SShengzhou Liu #define CONFIG_SYS_CPLD_BASE 0xffdf0000 29548c6f328SShengzhou Liu #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 29648c6f328SShengzhou Liu #define CONFIG_SYS_CSPR2_EXT (0xf) 29748c6f328SShengzhou Liu #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 29848c6f328SShengzhou Liu | CSPR_PORT_SIZE_8 \ 29948c6f328SShengzhou Liu | CSPR_MSEL_GPCM \ 30048c6f328SShengzhou Liu | CSPR_V) 30148c6f328SShengzhou Liu #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 30248c6f328SShengzhou Liu #define CONFIG_SYS_CSOR2 0x0 30348c6f328SShengzhou Liu 30448c6f328SShengzhou Liu /* CPLD Timing parameters for IFC CS2 */ 30548c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 30648c6f328SShengzhou Liu FTIM0_GPCM_TEADC(0x0e) | \ 30748c6f328SShengzhou Liu FTIM0_GPCM_TEAHC(0x0e)) 30848c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 30948c6f328SShengzhou Liu FTIM1_GPCM_TRAD(0x1f)) 31048c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 31148c6f328SShengzhou Liu FTIM2_GPCM_TCH(0x8) | \ 31248c6f328SShengzhou Liu FTIM2_GPCM_TWP(0x1f)) 31348c6f328SShengzhou Liu #define CONFIG_SYS_CS2_FTIM3 0x0 314e8a7f1c3SShengzhou Liu #endif 31548c6f328SShengzhou Liu 31648c6f328SShengzhou Liu /* NAND Flash on IFC */ 31748c6f328SShengzhou Liu #define CONFIG_NAND_FSL_IFC 31848c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE 0xff800000 31948c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 32048c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 32148c6f328SShengzhou Liu #else 32248c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 32348c6f328SShengzhou Liu #endif 32448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 32548c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 32648c6f328SShengzhou Liu | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 32748c6f328SShengzhou Liu | CSPR_MSEL_NAND /* MSEL = NAND */ \ 32848c6f328SShengzhou Liu | CSPR_V) 32948c6f328SShengzhou Liu #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 33048c6f328SShengzhou Liu 331960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 33248c6f328SShengzhou Liu #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 33348c6f328SShengzhou Liu | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 33448c6f328SShengzhou Liu | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 33548c6f328SShengzhou Liu | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 33648c6f328SShengzhou Liu | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 33748c6f328SShengzhou Liu | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 33848c6f328SShengzhou Liu | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 339e8a7f1c3SShengzhou Liu #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 3409082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 3417842950fSJaiprakash Singh #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 3427842950fSJaiprakash Singh | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 3437842950fSJaiprakash Singh | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 344e8a7f1c3SShengzhou Liu | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 345e8a7f1c3SShengzhou Liu | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 346e8a7f1c3SShengzhou Liu | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 347e8a7f1c3SShengzhou Liu | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 348e8a7f1c3SShengzhou Liu #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 349e8a7f1c3SShengzhou Liu #endif 35048c6f328SShengzhou Liu 35148c6f328SShengzhou Liu #define CONFIG_SYS_NAND_ONFI_DETECTION 35248c6f328SShengzhou Liu /* ONFI NAND Flash mode0 Timing Params */ 35348c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 35448c6f328SShengzhou Liu FTIM0_NAND_TWP(0x18) | \ 35548c6f328SShengzhou Liu FTIM0_NAND_TWCHT(0x07) | \ 35648c6f328SShengzhou Liu FTIM0_NAND_TWH(0x0a)) 35748c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 35848c6f328SShengzhou Liu FTIM1_NAND_TWBE(0x39) | \ 35948c6f328SShengzhou Liu FTIM1_NAND_TRR(0x0e) | \ 36048c6f328SShengzhou Liu FTIM1_NAND_TRP(0x18)) 36148c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 36248c6f328SShengzhou Liu FTIM2_NAND_TREH(0x0a) | \ 36348c6f328SShengzhou Liu FTIM2_NAND_TWHRE(0x1e)) 36448c6f328SShengzhou Liu #define CONFIG_SYS_NAND_FTIM3 0x0 36548c6f328SShengzhou Liu 36648c6f328SShengzhou Liu #define CONFIG_SYS_NAND_DDR_LAW 11 36748c6f328SShengzhou Liu #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 36848c6f328SShengzhou Liu #define CONFIG_SYS_MAX_NAND_DEVICE 1 36948c6f328SShengzhou Liu 37048c6f328SShengzhou Liu #if defined(CONFIG_NAND) 37148c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 37248c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 37348c6f328SShengzhou Liu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 37448c6f328SShengzhou Liu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 37548c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 37648c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 37748c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 37848c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 37948c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 38048c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 38148c6f328SShengzhou Liu #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 38248c6f328SShengzhou Liu #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 38348c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 38448c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 38548c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 38648c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 38748c6f328SShengzhou Liu #else 38848c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 38948c6f328SShengzhou Liu #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 39048c6f328SShengzhou Liu #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 39148c6f328SShengzhou Liu #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 39248c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 39348c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 39448c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 39548c6f328SShengzhou Liu #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 39648c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 39748c6f328SShengzhou Liu #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 39848c6f328SShengzhou Liu #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 39948c6f328SShengzhou Liu #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 40048c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 40148c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 40248c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 40348c6f328SShengzhou Liu #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 40448c6f328SShengzhou Liu #endif 40548c6f328SShengzhou Liu 40648c6f328SShengzhou Liu #ifdef CONFIG_SPL_BUILD 40748c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 40848c6f328SShengzhou Liu #else 40948c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 41048c6f328SShengzhou Liu #endif 41148c6f328SShengzhou Liu 41248c6f328SShengzhou Liu #if defined(CONFIG_RAMBOOT_PBL) 41348c6f328SShengzhou Liu #define CONFIG_SYS_RAMBOOT 41448c6f328SShengzhou Liu #endif 41548c6f328SShengzhou Liu 41648c6f328SShengzhou Liu #define CONFIG_HWCONFIG 41748c6f328SShengzhou Liu 41848c6f328SShengzhou Liu /* define to use L1 as initial stack */ 41948c6f328SShengzhou Liu #define CONFIG_L1_INIT_RAM 42048c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_LOCK 42148c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 42248c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 42348c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 424b3142e2cSYork Sun #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 42548c6f328SShengzhou Liu /* The assembler doesn't like typecast */ 42648c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 42748c6f328SShengzhou Liu ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 42848c6f328SShengzhou Liu CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 42948c6f328SShengzhou Liu #else 430b3142e2cSYork Sun #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 43148c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 43248c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 43348c6f328SShengzhou Liu #endif 43448c6f328SShengzhou Liu #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 43548c6f328SShengzhou Liu 43648c6f328SShengzhou Liu #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 43748c6f328SShengzhou Liu GENERATED_GBL_DATA_SIZE) 43848c6f328SShengzhou Liu #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 43948c6f328SShengzhou Liu 44048c6f328SShengzhou Liu #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 44148c6f328SShengzhou Liu #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 44248c6f328SShengzhou Liu 44348c6f328SShengzhou Liu /* Serial Port */ 44448c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_SERIAL 44548c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_REG_SIZE 1 44648c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 44748c6f328SShengzhou Liu 44848c6f328SShengzhou Liu #define CONFIG_SYS_BAUDRATE_TABLE \ 44948c6f328SShengzhou Liu {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 45048c6f328SShengzhou Liu 45148c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 45248c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 45348c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 45448c6f328SShengzhou Liu #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 45548c6f328SShengzhou Liu 45648c6f328SShengzhou Liu /* Video */ 45748c6f328SShengzhou Liu #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 45848c6f328SShengzhou Liu #ifdef CONFIG_FSL_DIU_FB 45948c6f328SShengzhou Liu #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 46048c6f328SShengzhou Liu #define CONFIG_VIDEO_LOGO 46148c6f328SShengzhou Liu #define CONFIG_VIDEO_BMP_LOGO 46248c6f328SShengzhou Liu #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 46348c6f328SShengzhou Liu /* 46448c6f328SShengzhou Liu * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 46548c6f328SShengzhou Liu * disable empty flash sector detection, which is I/O-intensive. 46648c6f328SShengzhou Liu */ 46748c6f328SShengzhou Liu #undef CONFIG_SYS_FLASH_EMPTY_INFO 46848c6f328SShengzhou Liu #endif 46948c6f328SShengzhou Liu 47048c6f328SShengzhou Liu /* I2C */ 47148c6f328SShengzhou Liu #define CONFIG_SYS_I2C 47248c6f328SShengzhou Liu #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 47348c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 47448c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 47548c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 47648c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 47748c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 47848c6f328SShengzhou Liu #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 47948c6f328SShengzhou Liu 480ff7ea2d1SShengzhou Liu #define I2C_PCA6408_BUS_NUM 1 481ff7ea2d1SShengzhou Liu #define I2C_PCA6408_ADDR 0x20 48248c6f328SShengzhou Liu 48348c6f328SShengzhou Liu /* I2C bus multiplexer */ 48448c6f328SShengzhou Liu #define I2C_MUX_CH_DEFAULT 0x8 48548c6f328SShengzhou Liu 48648c6f328SShengzhou Liu /* 48748c6f328SShengzhou Liu * RTC configuration 48848c6f328SShengzhou Liu */ 48948c6f328SShengzhou Liu #define RTC 49048c6f328SShengzhou Liu #define CONFIG_RTC_DS1337 1 49148c6f328SShengzhou Liu #define CONFIG_SYS_I2C_RTC_ADDR 0x68 49248c6f328SShengzhou Liu 49348c6f328SShengzhou Liu /* 49448c6f328SShengzhou Liu * eSPI - Enhanced SPI 49548c6f328SShengzhou Liu */ 49648c6f328SShengzhou Liu 49748c6f328SShengzhou Liu /* 49848c6f328SShengzhou Liu * General PCIe 49948c6f328SShengzhou Liu * Memory space is mapped 1-1, but I/O space must start from 0. 50048c6f328SShengzhou Liu */ 501b38eaec5SRobert P. J. Day #define CONFIG_PCIE1 /* PCIE controller 1 */ 502b38eaec5SRobert P. J. Day #define CONFIG_PCIE2 /* PCIE controller 2 */ 503b38eaec5SRobert P. J. Day #define CONFIG_PCIE3 /* PCIE controller 3 */ 5045d737010SYork Sun #ifdef CONFIG_ARCH_T1040 505b38eaec5SRobert P. J. Day #define CONFIG_PCIE4 /* PCIE controller 4 */ 50648c6f328SShengzhou Liu #endif 50748c6f328SShengzhou Liu #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 50848c6f328SShengzhou Liu #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 50948c6f328SShengzhou Liu #define CONFIG_PCI_INDIRECT_BRIDGE 51048c6f328SShengzhou Liu 51148c6f328SShengzhou Liu #ifdef CONFIG_PCI 51248c6f328SShengzhou Liu /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 51348c6f328SShengzhou Liu #ifdef CONFIG_PCIE1 51448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 51548c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 51648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 51748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 51848c6f328SShengzhou Liu #else 51948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 52048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 52148c6f328SShengzhou Liu #endif 52248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 52348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 52448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 52548c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 52648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 52748c6f328SShengzhou Liu #else 52848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 52948c6f328SShengzhou Liu #endif 53048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 53148c6f328SShengzhou Liu #endif 53248c6f328SShengzhou Liu 53348c6f328SShengzhou Liu /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 53448c6f328SShengzhou Liu #ifdef CONFIG_PCIE2 53548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 53648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 53748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 53848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 53948c6f328SShengzhou Liu #else 54048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 54148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 54248c6f328SShengzhou Liu #endif 54348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 54448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 54548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 54648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 54748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 54848c6f328SShengzhou Liu #else 54948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 55048c6f328SShengzhou Liu #endif 55148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 55248c6f328SShengzhou Liu #endif 55348c6f328SShengzhou Liu 55448c6f328SShengzhou Liu /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 55548c6f328SShengzhou Liu #ifdef CONFIG_PCIE3 55648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 55748c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 55848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 55948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 56048c6f328SShengzhou Liu #else 56148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 56248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 56348c6f328SShengzhou Liu #endif 56448c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 56548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 56648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 56748c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 56848c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 56948c6f328SShengzhou Liu #else 57048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 57148c6f328SShengzhou Liu #endif 57248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 57348c6f328SShengzhou Liu #endif 57448c6f328SShengzhou Liu 57548c6f328SShengzhou Liu /* controller 4, Base address 203000, to be removed */ 57648c6f328SShengzhou Liu #ifdef CONFIG_PCIE4 57748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 57848c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 57948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 58048c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 58148c6f328SShengzhou Liu #else 58248c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 58348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 58448c6f328SShengzhou Liu #endif 58548c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 58648c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 58748c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 58848c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 58948c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 59048c6f328SShengzhou Liu #else 59148c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 59248c6f328SShengzhou Liu #endif 59348c6f328SShengzhou Liu #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 59448c6f328SShengzhou Liu #endif 59548c6f328SShengzhou Liu 59648c6f328SShengzhou Liu #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 59748c6f328SShengzhou Liu #endif /* CONFIG_PCI */ 59848c6f328SShengzhou Liu 59948c6f328SShengzhou Liu /* 60048c6f328SShengzhou Liu * USB 60148c6f328SShengzhou Liu */ 60248c6f328SShengzhou Liu #define CONFIG_HAS_FSL_DR_USB 60348c6f328SShengzhou Liu 60448c6f328SShengzhou Liu #ifdef CONFIG_HAS_FSL_DR_USB 60548c6f328SShengzhou Liu #define CONFIG_USB_EHCI_FSL 60648c6f328SShengzhou Liu #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 60748c6f328SShengzhou Liu #endif 60848c6f328SShengzhou Liu 60948c6f328SShengzhou Liu /* 61048c6f328SShengzhou Liu * SDHC 61148c6f328SShengzhou Liu */ 61248c6f328SShengzhou Liu #ifdef CONFIG_MMC 61348c6f328SShengzhou Liu #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 61448c6f328SShengzhou Liu #endif 61548c6f328SShengzhou Liu 61648c6f328SShengzhou Liu /* Qman/Bman */ 61748c6f328SShengzhou Liu #ifndef CONFIG_NOBQFMAN 6182a8b3422SJeffrey Ladouceur #define CONFIG_SYS_BMAN_NUM_PORTALS 10 61948c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 62048c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 62148c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 62248c6f328SShengzhou Liu #else 62348c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 62448c6f328SShengzhou Liu #endif 62548c6f328SShengzhou Liu #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 6263fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 6273fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 6283fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 6293fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 6303fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 6313fa66db4SJeffrey Ladouceur CONFIG_SYS_BMAN_CENA_SIZE) 6323fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 6333fa66db4SJeffrey Ladouceur #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 6342a8b3422SJeffrey Ladouceur #define CONFIG_SYS_QMAN_NUM_PORTALS 10 63548c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 63648c6f328SShengzhou Liu #ifdef CONFIG_PHYS_64BIT 63748c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 63848c6f328SShengzhou Liu #else 63948c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 64048c6f328SShengzhou Liu #endif 64148c6f328SShengzhou Liu #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 6423fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 6433fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 6443fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 6453fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 6463fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 6473fa66db4SJeffrey Ladouceur CONFIG_SYS_QMAN_CENA_SIZE) 6483fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 6493fa66db4SJeffrey Ladouceur #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 65048c6f328SShengzhou Liu 65148c6f328SShengzhou Liu #define CONFIG_SYS_DPAA_FMAN 65248c6f328SShengzhou Liu 653960286b6SYork Sun #ifdef CONFIG_TARGET_T1024RDB 65448c6f328SShengzhou Liu #define CONFIG_QE 655ff7ea2d1SShengzhou Liu #endif 65648c6f328SShengzhou Liu /* Default address of microcode for the Linux FMan driver */ 65748c6f328SShengzhou Liu #if defined(CONFIG_SPIFLASH) 65848c6f328SShengzhou Liu /* 65948c6f328SShengzhou Liu * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 66048c6f328SShengzhou Liu * env, so we got 0x110000. 66148c6f328SShengzhou Liu */ 66248c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_IN_SPIFLASH 66348c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 66448c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR 0x130000 66548c6f328SShengzhou Liu #elif defined(CONFIG_SDCARD) 66648c6f328SShengzhou Liu /* 66748c6f328SShengzhou Liu * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 66848c6f328SShengzhou Liu * about 1MB (2048 blocks), Env is stored after the image, and the env size is 66948c6f328SShengzhou Liu * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 67048c6f328SShengzhou Liu */ 67148c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 67248c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 67348c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 67448c6f328SShengzhou Liu #elif defined(CONFIG_NAND) 67548c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 676960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 67748c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 67848c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 6799082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 680e8a7f1c3SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 681e8a7f1c3SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 682e8a7f1c3SShengzhou Liu #endif 68348c6f328SShengzhou Liu #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 68448c6f328SShengzhou Liu /* 68548c6f328SShengzhou Liu * Slave has no ucode locally, it can fetch this from remote. When implementing 68648c6f328SShengzhou Liu * in two corenet boards, slave's ucode could be stored in master's memory 68748c6f328SShengzhou Liu * space, the address can be mapped from slave TLB->slave LAW-> 68848c6f328SShengzhou Liu * slave SRIO or PCIE outbound window->master inbound window-> 68948c6f328SShengzhou Liu * master LAW->the ucode address in master's memory space. 69048c6f328SShengzhou Liu */ 69148c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 69248c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 69348c6f328SShengzhou Liu #else 69448c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 69548c6f328SShengzhou Liu #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 69648c6f328SShengzhou Liu #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 69748c6f328SShengzhou Liu #endif 69848c6f328SShengzhou Liu #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 69948c6f328SShengzhou Liu #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 70048c6f328SShengzhou Liu #endif /* CONFIG_NOBQFMAN */ 70148c6f328SShengzhou Liu 70248c6f328SShengzhou Liu #ifdef CONFIG_SYS_DPAA_FMAN 70348c6f328SShengzhou Liu #define CONFIG_FMAN_ENET 70448c6f328SShengzhou Liu #define CONFIG_PHY_REALTEK 705960286b6SYork Sun #if defined(CONFIG_TARGET_T1024RDB) 70648c6f328SShengzhou Liu #define RGMII_PHY1_ADDR 0x2 70748c6f328SShengzhou Liu #define RGMII_PHY2_ADDR 0x6 708e8a7f1c3SShengzhou Liu #define SGMII_AQR_PHY_ADDR 0x2 70948c6f328SShengzhou Liu #define FM1_10GEC1_PHY_ADDR 0x1 7109082405dSYork Sun #elif defined(CONFIG_TARGET_T1023RDB) 711e8a7f1c3SShengzhou Liu #define RGMII_PHY1_ADDR 0x1 712e8a7f1c3SShengzhou Liu #define SGMII_RTK_PHY_ADDR 0x3 713e8a7f1c3SShengzhou Liu #define SGMII_AQR_PHY_ADDR 0x2 714e8a7f1c3SShengzhou Liu #endif 71548c6f328SShengzhou Liu #endif 71648c6f328SShengzhou Liu 71748c6f328SShengzhou Liu #ifdef CONFIG_FMAN_ENET 71848c6f328SShengzhou Liu #define CONFIG_ETHPRIME "FM1@DTSEC4" 71948c6f328SShengzhou Liu #endif 72048c6f328SShengzhou Liu 72148c6f328SShengzhou Liu /* 72248c6f328SShengzhou Liu * Dynamic MTD Partition support with mtdparts 72348c6f328SShengzhou Liu */ 72448c6f328SShengzhou Liu 72548c6f328SShengzhou Liu /* 72648c6f328SShengzhou Liu * Environment 72748c6f328SShengzhou Liu */ 72848c6f328SShengzhou Liu #define CONFIG_LOADS_ECHO /* echo on for serial download */ 72948c6f328SShengzhou Liu #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 73048c6f328SShengzhou Liu 73148c6f328SShengzhou Liu /* 73248c6f328SShengzhou Liu * Miscellaneous configurable options 73348c6f328SShengzhou Liu */ 73448c6f328SShengzhou Liu #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 73548c6f328SShengzhou Liu 73648c6f328SShengzhou Liu /* 73748c6f328SShengzhou Liu * For booting Linux, the board info and command line data 73848c6f328SShengzhou Liu * have to be in the first 64 MB of memory, since this is 73948c6f328SShengzhou Liu * the maximum mapped by the Linux kernel during initialization. 74048c6f328SShengzhou Liu */ 74148c6f328SShengzhou Liu #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 74248c6f328SShengzhou Liu #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 74348c6f328SShengzhou Liu 74448c6f328SShengzhou Liu #ifdef CONFIG_CMD_KGDB 74548c6f328SShengzhou Liu #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 74648c6f328SShengzhou Liu #endif 74748c6f328SShengzhou Liu 74848c6f328SShengzhou Liu /* 74948c6f328SShengzhou Liu * Environment Configuration 75048c6f328SShengzhou Liu */ 75148c6f328SShengzhou Liu #define CONFIG_ROOTPATH "/opt/nfsroot" 75248c6f328SShengzhou Liu #define CONFIG_BOOTFILE "uImage" 753e8a7f1c3SShengzhou Liu #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 75448c6f328SShengzhou Liu #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 75548c6f328SShengzhou Liu #define __USB_PHY_TYPE utmi 75648c6f328SShengzhou Liu 757e5d5f5a8SYork Sun #ifdef CONFIG_ARCH_T1024 758e8a7f1c3SShengzhou Liu #define CONFIG_BOARDNAME t1024rdb 759e8a7f1c3SShengzhou Liu #define BANK_INTLV cs0_cs1 76048c6f328SShengzhou Liu #else 761e8a7f1c3SShengzhou Liu #define CONFIG_BOARDNAME t1023rdb 762e8a7f1c3SShengzhou Liu #define BANK_INTLV null 76348c6f328SShengzhou Liu #endif 76448c6f328SShengzhou Liu 76548c6f328SShengzhou Liu #define CONFIG_EXTRA_ENV_SETTINGS \ 76648c6f328SShengzhou Liu "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 767e8a7f1c3SShengzhou Liu "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 76848c6f328SShengzhou Liu "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 76948c6f328SShengzhou Liu "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 77048c6f328SShengzhou Liu "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 77148c6f328SShengzhou Liu __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 77248c6f328SShengzhou Liu "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 77348c6f328SShengzhou Liu "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 77448c6f328SShengzhou Liu "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 77548c6f328SShengzhou Liu "netdev=eth0\0" \ 77648c6f328SShengzhou Liu "tftpflash=tftpboot $loadaddr $uboot && " \ 77748c6f328SShengzhou Liu "protect off $ubootaddr +$filesize && " \ 77848c6f328SShengzhou Liu "erase $ubootaddr +$filesize && " \ 77948c6f328SShengzhou Liu "cp.b $loadaddr $ubootaddr $filesize && " \ 78048c6f328SShengzhou Liu "protect on $ubootaddr +$filesize && " \ 78148c6f328SShengzhou Liu "cmp.b $loadaddr $ubootaddr $filesize\0" \ 78248c6f328SShengzhou Liu "consoledev=ttyS0\0" \ 78348c6f328SShengzhou Liu "ramdiskaddr=2000000\0" \ 784b24a4f62SScott Wood "fdtaddr=1e00000\0" \ 78548c6f328SShengzhou Liu "bdev=sda3\0" 78648c6f328SShengzhou Liu 78748c6f328SShengzhou Liu #define CONFIG_LINUX \ 78848c6f328SShengzhou Liu "setenv bootargs root=/dev/ram rw " \ 78948c6f328SShengzhou Liu "console=$consoledev,$baudrate $othbootargs;" \ 79048c6f328SShengzhou Liu "setenv ramdiskaddr 0x02000000;" \ 79148c6f328SShengzhou Liu "setenv fdtaddr 0x00c00000;" \ 79248c6f328SShengzhou Liu "setenv loadaddr 0x1000000;" \ 79348c6f328SShengzhou Liu "bootm $loadaddr $ramdiskaddr $fdtaddr" 79448c6f328SShengzhou Liu 79548c6f328SShengzhou Liu #define CONFIG_NFSBOOTCOMMAND \ 79648c6f328SShengzhou Liu "setenv bootargs root=/dev/nfs rw " \ 79748c6f328SShengzhou Liu "nfsroot=$serverip:$rootpath " \ 79848c6f328SShengzhou Liu "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 79948c6f328SShengzhou Liu "console=$consoledev,$baudrate $othbootargs;" \ 80048c6f328SShengzhou Liu "tftp $loadaddr $bootfile;" \ 80148c6f328SShengzhou Liu "tftp $fdtaddr $fdtfile;" \ 80248c6f328SShengzhou Liu "bootm $loadaddr - $fdtaddr" 80348c6f328SShengzhou Liu 80448c6f328SShengzhou Liu #define CONFIG_BOOTCOMMAND CONFIG_LINUX 80548c6f328SShengzhou Liu 80648c6f328SShengzhou Liu #include <asm/fsl_secure_boot.h> 807ef6c55a2SAneesh Bansal 80848c6f328SShengzhou Liu #endif /* __T1024RDB_H */ 809