Lines Matching +full:0 +full:xfdd00000
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
53 #define CONFIG_SYS_MMC_ENV_DEV 0
54 #define CONFIG_ENV_SIZE 0x2000
68 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
80 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
81 #define CONFIG_SYS_MEMTEST_END 0x00400000
88 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
96 #define CONFIG_SYS_DCSRBAR 0xf0000000
97 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
113 #define SPD_EEPROM_ADDRESS1 0x51
114 #define SPD_EEPROM_ADDRESS2 0x52
121 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
123 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
128 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
130 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
143 #define CONFIG_SYS_OR0_PRELIM 0xfff00010
144 #define CONFIG_SYS_OR1_PRELIM 0xfff00010
157 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
167 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
170 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
184 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
191 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
192 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
200 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
201 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
203 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
204 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
206 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
207 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
209 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
210 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
214 #define CONFIG_SYS_EEPROM_BUS_NUM 0
216 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
220 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
221 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
222 #define CONFIG_SYS_I2C_MAC2_BUS 0
223 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
224 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
228 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f
236 * Memory space is mapped 1-1, but I/O space must start from 0.
240 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
242 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
243 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
245 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
246 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
248 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
249 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
250 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
252 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
254 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
256 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
259 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
261 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
262 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
264 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
265 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
267 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
268 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
269 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
271 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
273 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
275 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
278 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
280 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
281 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
283 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
284 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
286 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
287 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
288 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
290 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
292 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
294 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
297 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
298 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
299 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
300 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
301 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
302 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
306 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
308 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
312 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
313 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
314 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
320 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
322 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
324 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
328 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
329 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
330 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
336 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
341 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
343 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
348 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
349 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
406 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
436 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
437 "netdev=eth0\0" \
438 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
439 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
440 "consoledev=ttyS0\0" \
441 "ramdiskaddr=2000000\0" \
442 "fdtaddr=1e00000\0" \
443 "bdev=sda3\0"