1724ba675SRob Herring// SPDX-License-Identifier: BSD-3-Clause 2724ba675SRob Herring/* 3724ba675SRob Herring * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4724ba675SRob Herring */ 5724ba675SRob Herring 6724ba675SRob Herring/dts-v1/; 7724ba675SRob Herring 8724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 9724ba675SRob Herring#include <dt-bindings/clock/qcom,gcc-msm8974.h> 10724ba675SRob Herring#include <dt-bindings/clock/qcom,mmcc-msm8974.h> 11724ba675SRob Herring#include <dt-bindings/clock/qcom,rpmcc.h> 12724ba675SRob Herring#include <dt-bindings/gpio/gpio.h> 13724ba675SRob Herring#include <dt-bindings/power/qcom-rpmpd.h> 14724ba675SRob Herring#include <dt-bindings/reset/qcom,gcc-msm8974.h> 15724ba675SRob Herring 16724ba675SRob Herring/ { 17724ba675SRob Herring #address-cells = <1>; 18724ba675SRob Herring #size-cells = <1>; 19724ba675SRob Herring interrupt-parent = <&intc>; 20724ba675SRob Herring 21724ba675SRob Herring chosen { }; 22724ba675SRob Herring 23724ba675SRob Herring memory@0 { 24724ba675SRob Herring device_type = "memory"; 25724ba675SRob Herring reg = <0x0 0x0>; 26724ba675SRob Herring }; 27724ba675SRob Herring 28724ba675SRob Herring clocks { 29724ba675SRob Herring xo_board: xo_board { 30724ba675SRob Herring compatible = "fixed-clock"; 31724ba675SRob Herring #clock-cells = <0>; 32724ba675SRob Herring clock-frequency = <19200000>; 33724ba675SRob Herring }; 34724ba675SRob Herring 35724ba675SRob Herring sleep_clk: sleep_clk { 36724ba675SRob Herring compatible = "fixed-clock"; 37724ba675SRob Herring #clock-cells = <0>; 38724ba675SRob Herring clock-frequency = <32768>; 39724ba675SRob Herring }; 40724ba675SRob Herring }; 41724ba675SRob Herring 42724ba675SRob Herring firmware { 43724ba675SRob Herring scm { 44724ba675SRob Herring compatible = "qcom,scm-msm8226", "qcom,scm"; 45724ba675SRob Herring clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; 46724ba675SRob Herring clock-names = "core", "bus", "iface"; 47724ba675SRob Herring }; 48724ba675SRob Herring }; 49724ba675SRob Herring 50724ba675SRob Herring pmu { 51724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 52724ba675SRob Herring interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 53724ba675SRob Herring IRQ_TYPE_LEVEL_HIGH)>; 54724ba675SRob Herring }; 55724ba675SRob Herring 56b471a1bcSStephan Gerhold rpm: remoteproc { 57b471a1bcSStephan Gerhold compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; 58724ba675SRob Herring 59b471a1bcSStephan Gerhold smd-edge { 60724ba675SRob Herring interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 61724ba675SRob Herring qcom,ipc = <&apcs 8 0>; 62724ba675SRob Herring qcom,smd-edge = <15>; 63724ba675SRob Herring 64724ba675SRob Herring rpm_requests: rpm-requests { 65724ba675SRob Herring compatible = "qcom,rpm-msm8226"; 66724ba675SRob Herring qcom,smd-channels = "rpm_requests"; 67724ba675SRob Herring 68724ba675SRob Herring rpmcc: clock-controller { 69724ba675SRob Herring compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; 70724ba675SRob Herring #clock-cells = <1>; 71724ba675SRob Herring clocks = <&xo_board>; 72724ba675SRob Herring clock-names = "xo"; 73724ba675SRob Herring }; 74724ba675SRob Herring 75724ba675SRob Herring rpmpd: power-controller { 76724ba675SRob Herring compatible = "qcom,msm8226-rpmpd"; 77724ba675SRob Herring #power-domain-cells = <1>; 78724ba675SRob Herring operating-points-v2 = <&rpmpd_opp_table>; 79724ba675SRob Herring 80724ba675SRob Herring rpmpd_opp_table: opp-table { 81724ba675SRob Herring compatible = "operating-points-v2"; 82724ba675SRob Herring 83724ba675SRob Herring rpmpd_opp_ret: opp1 { 84724ba675SRob Herring opp-level = <1>; 85724ba675SRob Herring }; 86724ba675SRob Herring rpmpd_opp_svs_krait: opp2 { 87724ba675SRob Herring opp-level = <2>; 88724ba675SRob Herring }; 89724ba675SRob Herring rpmpd_opp_svs_soc: opp3 { 90724ba675SRob Herring opp-level = <3>; 91724ba675SRob Herring }; 92724ba675SRob Herring rpmpd_opp_nom: opp4 { 93724ba675SRob Herring opp-level = <4>; 94724ba675SRob Herring }; 95724ba675SRob Herring rpmpd_opp_turbo: opp5 { 96724ba675SRob Herring opp-level = <5>; 97724ba675SRob Herring }; 98724ba675SRob Herring rpmpd_opp_super_turbo: opp6 { 99724ba675SRob Herring opp-level = <6>; 100724ba675SRob Herring }; 101724ba675SRob Herring }; 102724ba675SRob Herring }; 103724ba675SRob Herring }; 104724ba675SRob Herring }; 105724ba675SRob Herring }; 106724ba675SRob Herring 107b471a1bcSStephan Gerhold reserved-memory { 108b471a1bcSStephan Gerhold #address-cells = <1>; 109b471a1bcSStephan Gerhold #size-cells = <1>; 110b471a1bcSStephan Gerhold ranges; 111b471a1bcSStephan Gerhold 112b471a1bcSStephan Gerhold smem_region: smem@3000000 { 113b471a1bcSStephan Gerhold reg = <0x3000000 0x100000>; 114b471a1bcSStephan Gerhold no-map; 115b471a1bcSStephan Gerhold }; 116b471a1bcSStephan Gerhold 117b471a1bcSStephan Gerhold adsp_region: adsp@dc00000 { 118b471a1bcSStephan Gerhold reg = <0x0dc00000 0x1900000>; 119b471a1bcSStephan Gerhold no-map; 120b471a1bcSStephan Gerhold }; 121b471a1bcSStephan Gerhold }; 122b471a1bcSStephan Gerhold 123724ba675SRob Herring smem { 124724ba675SRob Herring compatible = "qcom,smem"; 125724ba675SRob Herring 126724ba675SRob Herring memory-region = <&smem_region>; 127724ba675SRob Herring qcom,rpm-msg-ram = <&rpm_msg_ram>; 128724ba675SRob Herring 129724ba675SRob Herring hwlocks = <&tcsr_mutex 3>; 130724ba675SRob Herring }; 131724ba675SRob Herring 132724ba675SRob Herring smp2p-adsp { 133724ba675SRob Herring compatible = "qcom,smp2p"; 134724ba675SRob Herring qcom,smem = <443>, <429>; 135724ba675SRob Herring 136724ba675SRob Herring interrupt-parent = <&intc>; 137724ba675SRob Herring interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 138724ba675SRob Herring 139724ba675SRob Herring qcom,ipc = <&apcs 8 10>; 140724ba675SRob Herring 141724ba675SRob Herring qcom,local-pid = <0>; 142724ba675SRob Herring qcom,remote-pid = <2>; 143724ba675SRob Herring 144724ba675SRob Herring adsp_smp2p_out: master-kernel { 145724ba675SRob Herring qcom,entry-name = "master-kernel"; 146724ba675SRob Herring #qcom,smem-state-cells = <1>; 147724ba675SRob Herring }; 148724ba675SRob Herring 149724ba675SRob Herring adsp_smp2p_in: slave-kernel { 150724ba675SRob Herring qcom,entry-name = "slave-kernel"; 151724ba675SRob Herring 152724ba675SRob Herring interrupt-controller; 153724ba675SRob Herring #interrupt-cells = <2>; 154724ba675SRob Herring }; 155724ba675SRob Herring }; 156724ba675SRob Herring 157724ba675SRob Herring soc: soc { 158724ba675SRob Herring compatible = "simple-bus"; 159724ba675SRob Herring #address-cells = <1>; 160724ba675SRob Herring #size-cells = <1>; 161724ba675SRob Herring ranges; 162724ba675SRob Herring 163724ba675SRob Herring intc: interrupt-controller@f9000000 { 164724ba675SRob Herring compatible = "qcom,msm-qgic2"; 165724ba675SRob Herring reg = <0xf9000000 0x1000>, 166724ba675SRob Herring <0xf9002000 0x1000>; 167724ba675SRob Herring interrupt-controller; 168724ba675SRob Herring #interrupt-cells = <3>; 169724ba675SRob Herring }; 170724ba675SRob Herring 171724ba675SRob Herring apcs: syscon@f9011000 { 172724ba675SRob Herring compatible = "syscon"; 173724ba675SRob Herring reg = <0xf9011000 0x1000>; 174724ba675SRob Herring }; 175724ba675SRob Herring 176724ba675SRob Herring sdhc_1: mmc@f9824900 { 177724ba675SRob Herring compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 178724ba675SRob Herring reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 179724ba675SRob Herring reg-names = "hc", "core"; 180724ba675SRob Herring interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 181724ba675SRob Herring <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 182724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 183724ba675SRob Herring clocks = <&gcc GCC_SDCC1_AHB_CLK>, 184724ba675SRob Herring <&gcc GCC_SDCC1_APPS_CLK>, 185724ba675SRob Herring <&rpmcc RPM_SMD_XO_CLK_SRC>; 186724ba675SRob Herring clock-names = "iface", "core", "xo"; 187724ba675SRob Herring pinctrl-names = "default"; 188724ba675SRob Herring pinctrl-0 = <&sdhc1_default_state>; 189724ba675SRob Herring status = "disabled"; 190724ba675SRob Herring }; 191724ba675SRob Herring 192724ba675SRob Herring sdhc_2: mmc@f98a4900 { 193724ba675SRob Herring compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 194724ba675SRob Herring reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 195724ba675SRob Herring reg-names = "hc", "core"; 196724ba675SRob Herring interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 197724ba675SRob Herring <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 198724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 199724ba675SRob Herring clocks = <&gcc GCC_SDCC2_AHB_CLK>, 200724ba675SRob Herring <&gcc GCC_SDCC2_APPS_CLK>, 201724ba675SRob Herring <&rpmcc RPM_SMD_XO_CLK_SRC>; 202724ba675SRob Herring clock-names = "iface", "core", "xo"; 203724ba675SRob Herring pinctrl-names = "default"; 204724ba675SRob Herring pinctrl-0 = <&sdhc2_default_state>; 205724ba675SRob Herring status = "disabled"; 206724ba675SRob Herring }; 207724ba675SRob Herring 208724ba675SRob Herring sdhc_3: mmc@f9864900 { 209724ba675SRob Herring compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 210724ba675SRob Herring reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 211724ba675SRob Herring reg-names = "hc", "core"; 212724ba675SRob Herring interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 213724ba675SRob Herring <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 214724ba675SRob Herring interrupt-names = "hc_irq", "pwr_irq"; 215724ba675SRob Herring clocks = <&gcc GCC_SDCC3_AHB_CLK>, 216724ba675SRob Herring <&gcc GCC_SDCC3_APPS_CLK>, 217724ba675SRob Herring <&rpmcc RPM_SMD_XO_CLK_SRC>; 218724ba675SRob Herring clock-names = "iface", "core", "xo"; 219724ba675SRob Herring pinctrl-names = "default"; 220724ba675SRob Herring pinctrl-0 = <&sdhc3_default_state>; 221724ba675SRob Herring status = "disabled"; 222724ba675SRob Herring }; 223724ba675SRob Herring 224724ba675SRob Herring blsp1_uart1: serial@f991d000 { 225724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 226724ba675SRob Herring reg = <0xf991d000 0x1000>; 227724ba675SRob Herring interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 228724ba675SRob Herring clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 229724ba675SRob Herring clock-names = "core", "iface"; 230724ba675SRob Herring status = "disabled"; 231724ba675SRob Herring }; 232724ba675SRob Herring 233724ba675SRob Herring blsp1_uart3: serial@f991f000 { 234724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 235724ba675SRob Herring reg = <0xf991f000 0x1000>; 236724ba675SRob Herring interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 237724ba675SRob Herring clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 238724ba675SRob Herring clock-names = "core", "iface"; 239724ba675SRob Herring status = "disabled"; 240724ba675SRob Herring }; 241724ba675SRob Herring 242724ba675SRob Herring blsp1_uart4: serial@f9920000 { 243724ba675SRob Herring compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 244724ba675SRob Herring reg = <0xf9920000 0x1000>; 245724ba675SRob Herring interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 246724ba675SRob Herring clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 247724ba675SRob Herring clock-names = "core", "iface"; 248724ba675SRob Herring status = "disabled"; 249724ba675SRob Herring }; 250724ba675SRob Herring 251724ba675SRob Herring blsp1_i2c1: i2c@f9923000 { 252724ba675SRob Herring status = "disabled"; 253724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 254724ba675SRob Herring reg = <0xf9923000 0x1000>; 255724ba675SRob Herring interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 256724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 257724ba675SRob Herring clock-names = "core", "iface"; 258724ba675SRob Herring pinctrl-names = "default"; 259724ba675SRob Herring pinctrl-0 = <&blsp1_i2c1_pins>; 260724ba675SRob Herring #address-cells = <1>; 261724ba675SRob Herring #size-cells = <0>; 262724ba675SRob Herring }; 263724ba675SRob Herring 264724ba675SRob Herring blsp1_i2c2: i2c@f9924000 { 265724ba675SRob Herring status = "disabled"; 266724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 267724ba675SRob Herring reg = <0xf9924000 0x1000>; 268724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 269724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 270724ba675SRob Herring clock-names = "core", "iface"; 271724ba675SRob Herring pinctrl-names = "default"; 272724ba675SRob Herring pinctrl-0 = <&blsp1_i2c2_pins>; 273724ba675SRob Herring #address-cells = <1>; 274724ba675SRob Herring #size-cells = <0>; 275724ba675SRob Herring }; 276724ba675SRob Herring 277724ba675SRob Herring blsp1_i2c3: i2c@f9925000 { 278724ba675SRob Herring status = "disabled"; 279724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 280724ba675SRob Herring reg = <0xf9925000 0x1000>; 281724ba675SRob Herring interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 282724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 283724ba675SRob Herring clock-names = "core", "iface"; 284724ba675SRob Herring pinctrl-names = "default"; 285724ba675SRob Herring pinctrl-0 = <&blsp1_i2c3_pins>; 286724ba675SRob Herring #address-cells = <1>; 287724ba675SRob Herring #size-cells = <0>; 288724ba675SRob Herring }; 289724ba675SRob Herring 290724ba675SRob Herring blsp1_i2c4: i2c@f9926000 { 291724ba675SRob Herring status = "disabled"; 292724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 293724ba675SRob Herring reg = <0xf9926000 0x1000>; 294724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 295724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 296724ba675SRob Herring clock-names = "core", "iface"; 297724ba675SRob Herring pinctrl-names = "default"; 298724ba675SRob Herring pinctrl-0 = <&blsp1_i2c4_pins>; 299724ba675SRob Herring #address-cells = <1>; 300724ba675SRob Herring #size-cells = <0>; 301724ba675SRob Herring }; 302724ba675SRob Herring 303724ba675SRob Herring blsp1_i2c5: i2c@f9927000 { 304724ba675SRob Herring status = "disabled"; 305724ba675SRob Herring compatible = "qcom,i2c-qup-v2.1.1"; 306724ba675SRob Herring reg = <0xf9927000 0x1000>; 307724ba675SRob Herring interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 308724ba675SRob Herring clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 309724ba675SRob Herring clock-names = "core", "iface"; 310724ba675SRob Herring pinctrl-names = "default"; 311724ba675SRob Herring pinctrl-0 = <&blsp1_i2c5_pins>; 312724ba675SRob Herring #address-cells = <1>; 313724ba675SRob Herring #size-cells = <0>; 314724ba675SRob Herring }; 315724ba675SRob Herring 316724ba675SRob Herring cci: cci@fda0c000 { 317724ba675SRob Herring compatible = "qcom,msm8226-cci"; 318724ba675SRob Herring #address-cells = <1>; 319724ba675SRob Herring #size-cells = <0>; 320724ba675SRob Herring reg = <0xfda0c000 0x1000>; 321724ba675SRob Herring interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 322724ba675SRob Herring clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 323724ba675SRob Herring <&mmcc CAMSS_CCI_CCI_AHB_CLK>, 324724ba675SRob Herring <&mmcc CAMSS_CCI_CCI_CLK>; 325724ba675SRob Herring clock-names = "camss_top_ahb", 326724ba675SRob Herring "cci_ahb", 327724ba675SRob Herring "cci"; 328724ba675SRob Herring 329724ba675SRob Herring pinctrl-names = "default", "sleep"; 330724ba675SRob Herring pinctrl-0 = <&cci_default>; 331724ba675SRob Herring pinctrl-1 = <&cci_sleep>; 332724ba675SRob Herring 333724ba675SRob Herring status = "disabled"; 334724ba675SRob Herring 335724ba675SRob Herring cci_i2c0: i2c-bus@0 { 336724ba675SRob Herring reg = <0>; 337724ba675SRob Herring clock-frequency = <400000>; 338724ba675SRob Herring #address-cells = <1>; 339724ba675SRob Herring #size-cells = <0>; 340724ba675SRob Herring }; 341724ba675SRob Herring }; 342724ba675SRob Herring 343724ba675SRob Herring usb: usb@f9a55000 { 344724ba675SRob Herring compatible = "qcom,ci-hdrc"; 345724ba675SRob Herring reg = <0xf9a55000 0x200>, 346724ba675SRob Herring <0xf9a55200 0x200>; 347724ba675SRob Herring interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 348724ba675SRob Herring clocks = <&gcc GCC_USB_HS_AHB_CLK>, 349724ba675SRob Herring <&gcc GCC_USB_HS_SYSTEM_CLK>; 350724ba675SRob Herring clock-names = "iface", "core"; 351724ba675SRob Herring assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 352724ba675SRob Herring assigned-clock-rates = <75000000>; 353724ba675SRob Herring resets = <&gcc GCC_USB_HS_BCR>; 354724ba675SRob Herring reset-names = "core"; 355724ba675SRob Herring phy_type = "ulpi"; 356724ba675SRob Herring dr_mode = "otg"; 357724ba675SRob Herring hnp-disable; 358724ba675SRob Herring srp-disable; 359724ba675SRob Herring adp-disable; 360724ba675SRob Herring ahb-burst-config = <0>; 361724ba675SRob Herring phy-names = "usb-phy"; 362724ba675SRob Herring phys = <&usb_hs_phy>; 363724ba675SRob Herring status = "disabled"; 364724ba675SRob Herring #reset-cells = <1>; 365724ba675SRob Herring 366724ba675SRob Herring ulpi { 367724ba675SRob Herring usb_hs_phy: phy { 368724ba675SRob Herring compatible = "qcom,usb-hs-phy-msm8226", 369724ba675SRob Herring "qcom,usb-hs-phy"; 370724ba675SRob Herring #phy-cells = <0>; 371724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 372724ba675SRob Herring <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 373724ba675SRob Herring clock-names = "ref", "sleep"; 374724ba675SRob Herring resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 375724ba675SRob Herring reset-names = "phy", "por"; 376724ba675SRob Herring qcom,init-seq = /bits/ 8 <0x0 0x44 377724ba675SRob Herring 0x1 0x68 0x2 0x24 0x3 0x13>; 378724ba675SRob Herring }; 379724ba675SRob Herring }; 380724ba675SRob Herring }; 381724ba675SRob Herring 382724ba675SRob Herring gcc: clock-controller@fc400000 { 383724ba675SRob Herring compatible = "qcom,gcc-msm8226"; 384724ba675SRob Herring reg = <0xfc400000 0x4000>; 385724ba675SRob Herring #clock-cells = <1>; 386724ba675SRob Herring #reset-cells = <1>; 387724ba675SRob Herring #power-domain-cells = <1>; 388724ba675SRob Herring 389724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 390724ba675SRob Herring <&sleep_clk>; 391724ba675SRob Herring clock-names = "xo", 392724ba675SRob Herring "sleep_clk"; 393724ba675SRob Herring }; 394724ba675SRob Herring 395724ba675SRob Herring mmcc: clock-controller@fd8c0000 { 396724ba675SRob Herring compatible = "qcom,mmcc-msm8226"; 397724ba675SRob Herring reg = <0xfd8c0000 0x6000>; 398724ba675SRob Herring #clock-cells = <1>; 399724ba675SRob Herring #reset-cells = <1>; 400724ba675SRob Herring #power-domain-cells = <1>; 401724ba675SRob Herring 402724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 403724ba675SRob Herring <&gcc GCC_MMSS_GPLL0_CLK_SRC>, 404724ba675SRob Herring <&gcc GPLL0_VOTE>, 405724ba675SRob Herring <&gcc GPLL1_VOTE>, 406724ba675SRob Herring <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 407*ddcb3b44SLuca Weiss <&mdss_dsi0_phy 1>, 408*ddcb3b44SLuca Weiss <&mdss_dsi0_phy 0>; 409724ba675SRob Herring clock-names = "xo", 410724ba675SRob Herring "mmss_gpll0_vote", 411724ba675SRob Herring "gpll0_vote", 412724ba675SRob Herring "gpll1_vote", 413724ba675SRob Herring "gfx3d_clk_src", 414724ba675SRob Herring "dsi0pll", 415724ba675SRob Herring "dsi0pllbyte"; 416724ba675SRob Herring }; 417724ba675SRob Herring 418724ba675SRob Herring tlmm: pinctrl@fd510000 { 419724ba675SRob Herring compatible = "qcom,msm8226-pinctrl"; 420724ba675SRob Herring reg = <0xfd510000 0x4000>; 421724ba675SRob Herring gpio-controller; 422724ba675SRob Herring #gpio-cells = <2>; 423724ba675SRob Herring gpio-ranges = <&tlmm 0 0 117>; 424724ba675SRob Herring interrupt-controller; 425724ba675SRob Herring #interrupt-cells = <2>; 426724ba675SRob Herring interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 427724ba675SRob Herring 428724ba675SRob Herring blsp1_i2c1_pins: blsp1-i2c1-state { 429724ba675SRob Herring pins = "gpio2", "gpio3"; 430724ba675SRob Herring function = "blsp_i2c1"; 431724ba675SRob Herring drive-strength = <2>; 432724ba675SRob Herring bias-disable; 433724ba675SRob Herring }; 434724ba675SRob Herring 435724ba675SRob Herring blsp1_i2c2_pins: blsp1-i2c2-state { 436724ba675SRob Herring pins = "gpio6", "gpio7"; 437724ba675SRob Herring function = "blsp_i2c2"; 438724ba675SRob Herring drive-strength = <2>; 439724ba675SRob Herring bias-disable; 440724ba675SRob Herring }; 441724ba675SRob Herring 442724ba675SRob Herring blsp1_i2c3_pins: blsp1-i2c3-state { 443724ba675SRob Herring pins = "gpio10", "gpio11"; 444724ba675SRob Herring function = "blsp_i2c3"; 445724ba675SRob Herring drive-strength = <2>; 446724ba675SRob Herring bias-disable; 447724ba675SRob Herring }; 448724ba675SRob Herring 449724ba675SRob Herring blsp1_i2c4_pins: blsp1-i2c4-state { 450724ba675SRob Herring pins = "gpio14", "gpio15"; 451724ba675SRob Herring function = "blsp_i2c4"; 452724ba675SRob Herring drive-strength = <2>; 453724ba675SRob Herring bias-disable; 454724ba675SRob Herring }; 455724ba675SRob Herring 456724ba675SRob Herring blsp1_i2c5_pins: blsp1-i2c5-state { 457724ba675SRob Herring pins = "gpio18", "gpio19"; 458724ba675SRob Herring function = "blsp_i2c5"; 459724ba675SRob Herring drive-strength = <2>; 460724ba675SRob Herring bias-disable; 461724ba675SRob Herring }; 462724ba675SRob Herring 463724ba675SRob Herring cci_default: cci-default-state { 464724ba675SRob Herring pins = "gpio29", "gpio30"; 465724ba675SRob Herring function = "cci_i2c0"; 466724ba675SRob Herring 467724ba675SRob Herring drive-strength = <2>; 468724ba675SRob Herring bias-disable; 469724ba675SRob Herring }; 470724ba675SRob Herring 471724ba675SRob Herring cci_sleep: cci-sleep-state { 472724ba675SRob Herring pins = "gpio29", "gpio30"; 473724ba675SRob Herring function = "gpio"; 474724ba675SRob Herring 475724ba675SRob Herring drive-strength = <2>; 476724ba675SRob Herring bias-disable; 477724ba675SRob Herring }; 478724ba675SRob Herring 479724ba675SRob Herring sdhc1_default_state: sdhc1-default-state { 480724ba675SRob Herring clk-pins { 481724ba675SRob Herring pins = "sdc1_clk"; 482724ba675SRob Herring drive-strength = <10>; 483724ba675SRob Herring bias-disable; 484724ba675SRob Herring }; 485724ba675SRob Herring 486724ba675SRob Herring cmd-data-pins { 487724ba675SRob Herring pins = "sdc1_cmd", "sdc1_data"; 488724ba675SRob Herring drive-strength = <10>; 489724ba675SRob Herring bias-pull-up; 490724ba675SRob Herring }; 491724ba675SRob Herring }; 492724ba675SRob Herring 493724ba675SRob Herring sdhc2_default_state: sdhc2-default-state { 494724ba675SRob Herring clk-pins { 495724ba675SRob Herring pins = "sdc2_clk"; 496724ba675SRob Herring drive-strength = <10>; 497724ba675SRob Herring bias-disable; 498724ba675SRob Herring }; 499724ba675SRob Herring 500724ba675SRob Herring cmd-data-pins { 501724ba675SRob Herring pins = "sdc2_cmd", "sdc2_data"; 502724ba675SRob Herring drive-strength = <10>; 503724ba675SRob Herring bias-pull-up; 504724ba675SRob Herring }; 505724ba675SRob Herring }; 506724ba675SRob Herring 507724ba675SRob Herring sdhc3_default_state: sdhc3-default-state { 508724ba675SRob Herring clk-pins { 509724ba675SRob Herring pins = "gpio44"; 510724ba675SRob Herring function = "sdc3"; 511724ba675SRob Herring drive-strength = <8>; 512724ba675SRob Herring bias-disable; 513724ba675SRob Herring }; 514724ba675SRob Herring 515724ba675SRob Herring cmd-pins { 516724ba675SRob Herring pins = "gpio43"; 517724ba675SRob Herring function = "sdc3"; 518724ba675SRob Herring drive-strength = <8>; 519724ba675SRob Herring bias-pull-up; 520724ba675SRob Herring }; 521724ba675SRob Herring 522724ba675SRob Herring data-pins { 523724ba675SRob Herring pins = "gpio39", "gpio40", "gpio41", "gpio42"; 524724ba675SRob Herring function = "sdc3"; 525724ba675SRob Herring drive-strength = <8>; 526724ba675SRob Herring bias-pull-up; 527724ba675SRob Herring }; 528724ba675SRob Herring }; 529724ba675SRob Herring }; 530724ba675SRob Herring 531724ba675SRob Herring tsens: thermal-sensor@fc4a9000 { 532724ba675SRob Herring compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1"; 533724ba675SRob Herring reg = <0xfc4a9000 0x1000>, /* TM */ 534724ba675SRob Herring <0xfc4a8000 0x1000>; /* SROT */ 535724ba675SRob Herring nvmem-cells = <&tsens_mode>, 536724ba675SRob Herring <&tsens_base1>, <&tsens_base2>, 537724ba675SRob Herring <&tsens_s0_p1>, <&tsens_s0_p2>, 538724ba675SRob Herring <&tsens_s1_p1>, <&tsens_s1_p2>, 539724ba675SRob Herring <&tsens_s2_p1>, <&tsens_s2_p2>, 540724ba675SRob Herring <&tsens_s3_p1>, <&tsens_s3_p2>, 541724ba675SRob Herring <&tsens_s4_p1>, <&tsens_s4_p2>, 542724ba675SRob Herring <&tsens_s5_p1>, <&tsens_s5_p2>, 543724ba675SRob Herring <&tsens_s6_p1>, <&tsens_s6_p2>; 544724ba675SRob Herring nvmem-cell-names = "mode", 545724ba675SRob Herring "base1", "base2", 546724ba675SRob Herring "s0_p1", "s0_p2", 547724ba675SRob Herring "s1_p1", "s1_p2", 548724ba675SRob Herring "s2_p1", "s2_p2", 549724ba675SRob Herring "s3_p1", "s3_p2", 550724ba675SRob Herring "s4_p1", "s4_p2", 551724ba675SRob Herring "s5_p1", "s5_p2", 552724ba675SRob Herring "s6_p1", "s6_p2"; 553724ba675SRob Herring #qcom,sensors = <6>; 554724ba675SRob Herring interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 555724ba675SRob Herring interrupt-names = "uplow"; 556724ba675SRob Herring #thermal-sensor-cells = <1>; 557724ba675SRob Herring }; 558724ba675SRob Herring 559724ba675SRob Herring restart@fc4ab000 { 560724ba675SRob Herring compatible = "qcom,pshold"; 561724ba675SRob Herring reg = <0xfc4ab000 0x4>; 562724ba675SRob Herring }; 563724ba675SRob Herring 564724ba675SRob Herring qfprom: qfprom@fc4bc000 { 565724ba675SRob Herring compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; 566724ba675SRob Herring reg = <0xfc4bc000 0x1000>; 567724ba675SRob Herring #address-cells = <1>; 568724ba675SRob Herring #size-cells = <1>; 569724ba675SRob Herring 570724ba675SRob Herring tsens_base1: base1@1c1 { 571724ba675SRob Herring reg = <0x1c1 0x2>; 572724ba675SRob Herring bits = <5 8>; 573724ba675SRob Herring }; 574724ba675SRob Herring 575724ba675SRob Herring tsens_s0_p1: s0-p1@1c2 { 576724ba675SRob Herring reg = <0x1c2 0x2>; 577724ba675SRob Herring bits = <5 6>; 578724ba675SRob Herring }; 579724ba675SRob Herring 580724ba675SRob Herring tsens_s1_p1: s1-p1@1c4 { 581724ba675SRob Herring reg = <0x1c4 0x1>; 582724ba675SRob Herring bits = <0 6>; 583724ba675SRob Herring }; 584724ba675SRob Herring 585724ba675SRob Herring tsens_s2_p1: s2-p1@1c4 { 586724ba675SRob Herring reg = <0x1c4 0x2>; 587724ba675SRob Herring bits = <6 6>; 588724ba675SRob Herring }; 589724ba675SRob Herring 590724ba675SRob Herring tsens_s3_p1: s3-p1@1c5 { 591724ba675SRob Herring reg = <0x1c5 0x2>; 592724ba675SRob Herring bits = <4 6>; 593724ba675SRob Herring }; 594724ba675SRob Herring 595724ba675SRob Herring tsens_s4_p1: s4-p1@1c6 { 596724ba675SRob Herring reg = <0x1c6 0x1>; 597724ba675SRob Herring bits = <2 6>; 598724ba675SRob Herring }; 599724ba675SRob Herring 600724ba675SRob Herring tsens_s5_p1: s5-p1@1c7 { 601724ba675SRob Herring reg = <0x1c7 0x1>; 602724ba675SRob Herring bits = <0 6>; 603724ba675SRob Herring }; 604724ba675SRob Herring 605724ba675SRob Herring tsens_s6_p1: s6-p1@1ca { 606724ba675SRob Herring reg = <0x1ca 0x2>; 607724ba675SRob Herring bits = <4 6>; 608724ba675SRob Herring }; 609724ba675SRob Herring 610724ba675SRob Herring tsens_base2: base2@1cc { 611724ba675SRob Herring reg = <0x1cc 0x1>; 612724ba675SRob Herring bits = <0 8>; 613724ba675SRob Herring }; 614724ba675SRob Herring 615724ba675SRob Herring tsens_s0_p2: s0-p2@1cd { 616724ba675SRob Herring reg = <0x1cd 0x1>; 617724ba675SRob Herring bits = <0 6>; 618724ba675SRob Herring }; 619724ba675SRob Herring 620724ba675SRob Herring tsens_s1_p2: s1-p2@1cd { 621724ba675SRob Herring reg = <0x1cd 0x2>; 622724ba675SRob Herring bits = <6 6>; 623724ba675SRob Herring }; 624724ba675SRob Herring 625724ba675SRob Herring tsens_s2_p2: s2-p2@1ce { 626724ba675SRob Herring reg = <0x1ce 0x2>; 627724ba675SRob Herring bits = <4 6>; 628724ba675SRob Herring }; 629724ba675SRob Herring 630724ba675SRob Herring tsens_s3_p2: s3-p2@1cf { 631724ba675SRob Herring reg = <0x1cf 0x1>; 632724ba675SRob Herring bits = <2 6>; 633724ba675SRob Herring }; 634724ba675SRob Herring 635724ba675SRob Herring tsens_s4_p2: s4-p2@446 { 636724ba675SRob Herring reg = <0x446 0x2>; 637724ba675SRob Herring bits = <4 6>; 638724ba675SRob Herring }; 639724ba675SRob Herring 640724ba675SRob Herring tsens_s5_p2: s5-p2@447 { 641724ba675SRob Herring reg = <0x447 0x1>; 642724ba675SRob Herring bits = <2 6>; 643724ba675SRob Herring }; 644724ba675SRob Herring 645724ba675SRob Herring tsens_s6_p2: s6-p2@44e { 646724ba675SRob Herring reg = <0x44e 0x1>; 647724ba675SRob Herring bits = <1 6>; 648724ba675SRob Herring }; 649724ba675SRob Herring 650724ba675SRob Herring tsens_mode: mode@44f { 651724ba675SRob Herring reg = <0x44f 0x1>; 652724ba675SRob Herring bits = <5 3>; 653724ba675SRob Herring }; 654724ba675SRob Herring }; 655724ba675SRob Herring 656724ba675SRob Herring spmi_bus: spmi@fc4cf000 { 657724ba675SRob Herring compatible = "qcom,spmi-pmic-arb"; 658724ba675SRob Herring reg-names = "core", "intr", "cnfg"; 659724ba675SRob Herring reg = <0xfc4cf000 0x1000>, 660724ba675SRob Herring <0xfc4cb000 0x1000>, 661724ba675SRob Herring <0xfc4ca000 0x1000>; 662724ba675SRob Herring interrupt-names = "periph_irq"; 663724ba675SRob Herring interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 664724ba675SRob Herring qcom,ee = <0>; 665724ba675SRob Herring qcom,channel = <0>; 666724ba675SRob Herring #address-cells = <2>; 667724ba675SRob Herring #size-cells = <0>; 668724ba675SRob Herring interrupt-controller; 669724ba675SRob Herring #interrupt-cells = <4>; 670724ba675SRob Herring }; 671724ba675SRob Herring 672724ba675SRob Herring rng@f9bff000 { 673724ba675SRob Herring compatible = "qcom,prng"; 674724ba675SRob Herring reg = <0xf9bff000 0x200>; 675724ba675SRob Herring clocks = <&gcc GCC_PRNG_AHB_CLK>; 676724ba675SRob Herring clock-names = "core"; 677724ba675SRob Herring }; 678724ba675SRob Herring 679724ba675SRob Herring timer@f9020000 { 680724ba675SRob Herring compatible = "arm,armv7-timer-mem"; 681724ba675SRob Herring reg = <0xf9020000 0x1000>; 682724ba675SRob Herring #address-cells = <1>; 683724ba675SRob Herring #size-cells = <1>; 684724ba675SRob Herring ranges; 685724ba675SRob Herring 686724ba675SRob Herring frame@f9021000 { 687724ba675SRob Herring frame-number = <0>; 688724ba675SRob Herring interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 689724ba675SRob Herring <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 690724ba675SRob Herring reg = <0xf9021000 0x1000>, 691724ba675SRob Herring <0xf9022000 0x1000>; 692724ba675SRob Herring }; 693724ba675SRob Herring 694724ba675SRob Herring frame@f9023000 { 695724ba675SRob Herring frame-number = <1>; 696724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 697724ba675SRob Herring reg = <0xf9023000 0x1000>; 698724ba675SRob Herring status = "disabled"; 699724ba675SRob Herring }; 700724ba675SRob Herring 701724ba675SRob Herring frame@f9024000 { 702724ba675SRob Herring frame-number = <2>; 703724ba675SRob Herring interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 704724ba675SRob Herring reg = <0xf9024000 0x1000>; 705724ba675SRob Herring status = "disabled"; 706724ba675SRob Herring }; 707724ba675SRob Herring 708724ba675SRob Herring frame@f9025000 { 709724ba675SRob Herring frame-number = <3>; 710724ba675SRob Herring interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 711724ba675SRob Herring reg = <0xf9025000 0x1000>; 712724ba675SRob Herring status = "disabled"; 713724ba675SRob Herring }; 714724ba675SRob Herring 715724ba675SRob Herring frame@f9026000 { 716724ba675SRob Herring frame-number = <4>; 717724ba675SRob Herring interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 718724ba675SRob Herring reg = <0xf9026000 0x1000>; 719724ba675SRob Herring status = "disabled"; 720724ba675SRob Herring }; 721724ba675SRob Herring 722724ba675SRob Herring frame@f9027000 { 723724ba675SRob Herring frame-number = <5>; 724724ba675SRob Herring interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 725724ba675SRob Herring reg = <0xf9027000 0x1000>; 726724ba675SRob Herring status = "disabled"; 727724ba675SRob Herring }; 728724ba675SRob Herring 729724ba675SRob Herring frame@f9028000 { 730724ba675SRob Herring frame-number = <6>; 731724ba675SRob Herring interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 732724ba675SRob Herring reg = <0xf9028000 0x1000>; 733724ba675SRob Herring status = "disabled"; 734724ba675SRob Herring }; 735724ba675SRob Herring }; 736724ba675SRob Herring 737724ba675SRob Herring sram@fc190000 { 738724ba675SRob Herring compatible = "qcom,msm8226-rpm-stats"; 739724ba675SRob Herring reg = <0xfc190000 0x10000>; 740724ba675SRob Herring }; 741724ba675SRob Herring 742724ba675SRob Herring rpm_msg_ram: sram@fc428000 { 743724ba675SRob Herring compatible = "qcom,rpm-msg-ram"; 744724ba675SRob Herring reg = <0xfc428000 0x4000>; 745724ba675SRob Herring }; 746724ba675SRob Herring 747724ba675SRob Herring tcsr_mutex: hwlock@fd484000 { 748724ba675SRob Herring compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex"; 749724ba675SRob Herring reg = <0xfd484000 0x1000>; 750724ba675SRob Herring #hwlock-cells = <1>; 751724ba675SRob Herring }; 752724ba675SRob Herring 753724ba675SRob Herring adsp: remoteproc@fe200000 { 754724ba675SRob Herring compatible = "qcom,msm8226-adsp-pil"; 755724ba675SRob Herring reg = <0xfe200000 0x100>; 756724ba675SRob Herring 757724ba675SRob Herring interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 758724ba675SRob Herring <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 759724ba675SRob Herring <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 760724ba675SRob Herring <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 761724ba675SRob Herring <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 762724ba675SRob Herring interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 763724ba675SRob Herring 764724ba675SRob Herring power-domains = <&rpmpd MSM8226_VDDCX>; 765724ba675SRob Herring power-domain-names = "cx"; 766724ba675SRob Herring 767724ba675SRob Herring clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 768724ba675SRob Herring clock-names = "xo"; 769724ba675SRob Herring 770724ba675SRob Herring memory-region = <&adsp_region>; 771724ba675SRob Herring 772724ba675SRob Herring qcom,smem-states = <&adsp_smp2p_out 0>; 773724ba675SRob Herring qcom,smem-state-names = "stop"; 774724ba675SRob Herring 775724ba675SRob Herring status = "disabled"; 776724ba675SRob Herring 777724ba675SRob Herring smd-edge { 778724ba675SRob Herring interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 779724ba675SRob Herring 780724ba675SRob Herring qcom,ipc = <&apcs 8 8>; 781724ba675SRob Herring qcom,smd-edge = <1>; 782724ba675SRob Herring 783724ba675SRob Herring label = "lpass"; 784724ba675SRob Herring }; 785724ba675SRob Herring }; 786724ba675SRob Herring 7874bad24d7SLuca Weiss sram@fdd00000 { 7884bad24d7SLuca Weiss compatible = "qcom,msm8226-ocmem"; 7894bad24d7SLuca Weiss reg = <0xfdd00000 0x2000>, 7904bad24d7SLuca Weiss <0xfec00000 0x20000>; 7914bad24d7SLuca Weiss reg-names = "ctrl", "mem"; 7924bad24d7SLuca Weiss ranges = <0 0xfec00000 0x20000>; 7934bad24d7SLuca Weiss clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; 7944bad24d7SLuca Weiss clock-names = "core"; 7954bad24d7SLuca Weiss 7964bad24d7SLuca Weiss #address-cells = <1>; 7974bad24d7SLuca Weiss #size-cells = <1>; 7984bad24d7SLuca Weiss 7994bad24d7SLuca Weiss gmu_sram: gmu-sram@0 { 8004bad24d7SLuca Weiss reg = <0x0 0x20000>; 8014bad24d7SLuca Weiss }; 8024bad24d7SLuca Weiss }; 8034bad24d7SLuca Weiss 804724ba675SRob Herring sram@fe805000 { 805724ba675SRob Herring compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; 806724ba675SRob Herring reg = <0xfe805000 0x1000>; 807724ba675SRob Herring 808724ba675SRob Herring reboot-mode { 809724ba675SRob Herring compatible = "syscon-reboot-mode"; 810724ba675SRob Herring offset = <0x65c>; 811724ba675SRob Herring 812724ba675SRob Herring mode-bootloader = <0x77665500>; 813724ba675SRob Herring mode-normal = <0x77665501>; 814724ba675SRob Herring mode-recovery = <0x77665502>; 815724ba675SRob Herring }; 816724ba675SRob Herring }; 817d5fb01adSLuca Weiss 818d5fb01adSLuca Weiss mdss: display-subsystem@fd900000 { 819d5fb01adSLuca Weiss compatible = "qcom,mdss"; 820d5fb01adSLuca Weiss reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; 821d5fb01adSLuca Weiss reg-names = "mdss_phys", "vbif_phys"; 822d5fb01adSLuca Weiss 823d5fb01adSLuca Weiss power-domains = <&mmcc MDSS_GDSC>; 824d5fb01adSLuca Weiss 825d5fb01adSLuca Weiss clocks = <&mmcc MDSS_AHB_CLK>, 826d5fb01adSLuca Weiss <&mmcc MDSS_AXI_CLK>, 827d5fb01adSLuca Weiss <&mmcc MDSS_VSYNC_CLK>; 828d5fb01adSLuca Weiss clock-names = "iface", 829d5fb01adSLuca Weiss "bus", 830d5fb01adSLuca Weiss "vsync"; 831d5fb01adSLuca Weiss 832d5fb01adSLuca Weiss interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 833d5fb01adSLuca Weiss 834d5fb01adSLuca Weiss interrupt-controller; 835d5fb01adSLuca Weiss #interrupt-cells = <1>; 836d5fb01adSLuca Weiss 837d5fb01adSLuca Weiss #address-cells = <1>; 838d5fb01adSLuca Weiss #size-cells = <1>; 839d5fb01adSLuca Weiss ranges; 840d5fb01adSLuca Weiss 841d5fb01adSLuca Weiss status = "disabled"; 842d5fb01adSLuca Weiss 843d5fb01adSLuca Weiss mdss_mdp: display-controller@fd900000 { 844d5fb01adSLuca Weiss compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; 845d5fb01adSLuca Weiss reg = <0xfd900100 0x22000>; 846d5fb01adSLuca Weiss reg-names = "mdp_phys"; 847d5fb01adSLuca Weiss 848d5fb01adSLuca Weiss interrupt-parent = <&mdss>; 849d5fb01adSLuca Weiss interrupts = <0>; 850d5fb01adSLuca Weiss 851d5fb01adSLuca Weiss clocks = <&mmcc MDSS_AHB_CLK>, 852d5fb01adSLuca Weiss <&mmcc MDSS_AXI_CLK>, 853d5fb01adSLuca Weiss <&mmcc MDSS_MDP_CLK>, 854d5fb01adSLuca Weiss <&mmcc MDSS_VSYNC_CLK>; 855d5fb01adSLuca Weiss clock-names = "iface", 856d5fb01adSLuca Weiss "bus", 857d5fb01adSLuca Weiss "core", 858d5fb01adSLuca Weiss "vsync"; 859d5fb01adSLuca Weiss 860d5fb01adSLuca Weiss ports { 861d5fb01adSLuca Weiss #address-cells = <1>; 862d5fb01adSLuca Weiss #size-cells = <0>; 863d5fb01adSLuca Weiss 864d5fb01adSLuca Weiss port@0 { 865d5fb01adSLuca Weiss reg = <0>; 866d5fb01adSLuca Weiss mdss_mdp_intf1_out: endpoint { 867d5fb01adSLuca Weiss remote-endpoint = <&mdss_dsi0_in>; 868d5fb01adSLuca Weiss }; 869d5fb01adSLuca Weiss }; 870d5fb01adSLuca Weiss }; 871d5fb01adSLuca Weiss }; 872d5fb01adSLuca Weiss 873d5fb01adSLuca Weiss mdss_dsi0: dsi@fd922800 { 874d5fb01adSLuca Weiss compatible = "qcom,msm8226-dsi-ctrl", 875d5fb01adSLuca Weiss "qcom,mdss-dsi-ctrl"; 876d5fb01adSLuca Weiss reg = <0xfd922800 0x1f8>; 877d5fb01adSLuca Weiss reg-names = "dsi_ctrl"; 878d5fb01adSLuca Weiss 879d5fb01adSLuca Weiss interrupt-parent = <&mdss>; 880d5fb01adSLuca Weiss interrupts = <4>; 881d5fb01adSLuca Weiss 882d5fb01adSLuca Weiss assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 883d5fb01adSLuca Weiss <&mmcc PCLK0_CLK_SRC>; 884d5fb01adSLuca Weiss assigned-clock-parents = <&mdss_dsi0_phy 0>, 885d5fb01adSLuca Weiss <&mdss_dsi0_phy 1>; 886d5fb01adSLuca Weiss 887d5fb01adSLuca Weiss clocks = <&mmcc MDSS_MDP_CLK>, 888d5fb01adSLuca Weiss <&mmcc MDSS_AHB_CLK>, 889d5fb01adSLuca Weiss <&mmcc MDSS_AXI_CLK>, 890d5fb01adSLuca Weiss <&mmcc MDSS_BYTE0_CLK>, 891d5fb01adSLuca Weiss <&mmcc MDSS_PCLK0_CLK>, 892d5fb01adSLuca Weiss <&mmcc MDSS_ESC0_CLK>, 893d5fb01adSLuca Weiss <&mmcc MMSS_MISC_AHB_CLK>; 894d5fb01adSLuca Weiss clock-names = "mdp_core", 895d5fb01adSLuca Weiss "iface", 896d5fb01adSLuca Weiss "bus", 897d5fb01adSLuca Weiss "byte", 898d5fb01adSLuca Weiss "pixel", 899d5fb01adSLuca Weiss "core", 900d5fb01adSLuca Weiss "core_mmss"; 901d5fb01adSLuca Weiss 902d5fb01adSLuca Weiss phys = <&mdss_dsi0_phy>; 903d5fb01adSLuca Weiss 904d5fb01adSLuca Weiss #address-cells = <1>; 905d5fb01adSLuca Weiss #size-cells = <0>; 906d5fb01adSLuca Weiss 907d5fb01adSLuca Weiss ports { 908d5fb01adSLuca Weiss #address-cells = <1>; 909d5fb01adSLuca Weiss #size-cells = <0>; 910d5fb01adSLuca Weiss 911d5fb01adSLuca Weiss port@0 { 912d5fb01adSLuca Weiss reg = <0>; 913d5fb01adSLuca Weiss mdss_dsi0_in: endpoint { 914d5fb01adSLuca Weiss remote-endpoint = <&mdss_mdp_intf1_out>; 915d5fb01adSLuca Weiss }; 916d5fb01adSLuca Weiss }; 917d5fb01adSLuca Weiss 918d5fb01adSLuca Weiss port@1 { 919d5fb01adSLuca Weiss reg = <1>; 920d5fb01adSLuca Weiss mdss_dsi0_out: endpoint { 921d5fb01adSLuca Weiss }; 922d5fb01adSLuca Weiss }; 923d5fb01adSLuca Weiss }; 924d5fb01adSLuca Weiss }; 925d5fb01adSLuca Weiss 926d5fb01adSLuca Weiss mdss_dsi0_phy: phy@fd922a00 { 927d5fb01adSLuca Weiss compatible = "qcom,dsi-phy-28nm-8226"; 928d5fb01adSLuca Weiss reg = <0xfd922a00 0xd4>, 929d5fb01adSLuca Weiss <0xfd922b00 0x280>, 930d5fb01adSLuca Weiss <0xfd922d80 0x30>; 931d5fb01adSLuca Weiss reg-names = "dsi_pll", 932d5fb01adSLuca Weiss "dsi_phy", 933d5fb01adSLuca Weiss "dsi_phy_regulator"; 934d5fb01adSLuca Weiss 935d5fb01adSLuca Weiss #clock-cells = <1>; 936d5fb01adSLuca Weiss #phy-cells = <0>; 937d5fb01adSLuca Weiss 938d5fb01adSLuca Weiss clocks = <&mmcc MDSS_AHB_CLK>, 939d5fb01adSLuca Weiss <&rpmcc RPM_SMD_XO_CLK_SRC>; 940d5fb01adSLuca Weiss clock-names = "iface", 941d5fb01adSLuca Weiss "ref"; 942d5fb01adSLuca Weiss }; 943d5fb01adSLuca Weiss }; 944724ba675SRob Herring }; 945724ba675SRob Herring 946724ba675SRob Herring thermal-zones { 947724ba675SRob Herring cpu0-thermal { 948724ba675SRob Herring polling-delay-passive = <250>; 949724ba675SRob Herring polling-delay = <1000>; 950724ba675SRob Herring 951724ba675SRob Herring thermal-sensors = <&tsens 5>; 952724ba675SRob Herring 953724ba675SRob Herring trips { 954724ba675SRob Herring cpu_alert0: trip0 { 955724ba675SRob Herring temperature = <75000>; 956724ba675SRob Herring hysteresis = <2000>; 957724ba675SRob Herring type = "passive"; 958724ba675SRob Herring }; 959724ba675SRob Herring 960724ba675SRob Herring cpu_crit0: trip1 { 961724ba675SRob Herring temperature = <110000>; 962724ba675SRob Herring hysteresis = <2000>; 963724ba675SRob Herring type = "critical"; 964724ba675SRob Herring }; 965724ba675SRob Herring }; 966724ba675SRob Herring }; 967724ba675SRob Herring 968724ba675SRob Herring cpu1-thermal { 969724ba675SRob Herring polling-delay-passive = <250>; 970724ba675SRob Herring polling-delay = <1000>; 971724ba675SRob Herring 972724ba675SRob Herring thermal-sensors = <&tsens 2>; 973724ba675SRob Herring 974724ba675SRob Herring trips { 975724ba675SRob Herring cpu_alert1: trip0 { 976724ba675SRob Herring temperature = <75000>; 977724ba675SRob Herring hysteresis = <2000>; 978724ba675SRob Herring type = "passive"; 979724ba675SRob Herring }; 980724ba675SRob Herring 981724ba675SRob Herring cpu_crit1: trip1 { 982724ba675SRob Herring temperature = <110000>; 983724ba675SRob Herring hysteresis = <2000>; 984724ba675SRob Herring type = "critical"; 985724ba675SRob Herring }; 986724ba675SRob Herring }; 987724ba675SRob Herring }; 988724ba675SRob Herring }; 989724ba675SRob Herring 990724ba675SRob Herring timer { 991724ba675SRob Herring compatible = "arm,armv7-timer"; 992724ba675SRob Herring interrupts = <GIC_PPI 2 993724ba675SRob Herring (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 994724ba675SRob Herring <GIC_PPI 3 995724ba675SRob Herring (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 996724ba675SRob Herring <GIC_PPI 4 997724ba675SRob Herring (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>, 998724ba675SRob Herring <GIC_PPI 1 999724ba675SRob Herring (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>; 1000724ba675SRob Herring }; 1001724ba675SRob Herring}; 1002