Lines Matching +full:0 +full:xfdd00000
33 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
34 #define CONFIG_SPL_PAD_TO 0x40000
35 #define CONFIG_SPL_MAX_SIZE 0x28000
36 #define RESET_VECTOR_OFFSET 0x27FFC
37 #define BOOT_PAGE_OFFSET 0x27000
46 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
47 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
55 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
59 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
70 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
72 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
73 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
88 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
90 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
91 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
95 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
106 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
109 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
110 #define CONFIG_SYS_MEMTEST_END 0x00400000
113 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
114 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
115 #define CONFIG_ENV_SECT_SIZE 0x10000
117 #define CONFIG_SYS_MMC_ENV_DEV 0
118 #define CONFIG_ENV_SIZE 0x2000
119 #define CONFIG_ENV_OFFSET (512 * 0x800)
121 #define CONFIG_ENV_SIZE 0x2000
124 #define CONFIG_ENV_ADDR 0xffe20000
125 #define CONFIG_ENV_SIZE 0x2000
127 #define CONFIG_ENV_SIZE 0x2000
130 #define CONFIG_ENV_SIZE 0x2000
131 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
145 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
155 #define CONFIG_SYS_DCSRBAR 0xf0000000
156 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
161 #define CONFIG_SYS_EEPROM_BUS_NUM 0
162 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
169 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
174 #define CONFIG_SYS_SPD_BUS_NUM 0
176 #define SPD_EEPROM_ADDRESS1 0x51
177 #define SPD_EEPROM_ADDRESS2 0x52
184 #define CONFIG_SYS_FLASH_BASE 0xe8000000
185 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
186 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
196 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
197 FTIM0_NOR_TEADC(0x5) | \
198 FTIM0_NOR_TEAHC(0x5))
199 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
200 FTIM1_NOR_TRAD_NOR(0x1A) |\
201 FTIM1_NOR_TSEQRAD_NOR(0x13))
202 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
203 FTIM2_NOR_TCH(0x4) | \
204 FTIM2_NOR_TWPH(0x0E) | \
205 FTIM2_NOR_TWP(0x1c))
206 #define CONFIG_SYS_NOR_FTIM3 0x0
219 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
220 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
221 #define CONFIG_SYS_CSPR2_EXT (0xf)
227 #define CONFIG_SYS_CSOR2 0x0
230 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
231 FTIM0_GPCM_TEADC(0x0e) | \
232 FTIM0_GPCM_TEAHC(0x0e))
233 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
234 FTIM1_GPCM_TRAD(0x1f))
235 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
236 FTIM2_GPCM_TCH(0x8) | \
237 FTIM2_GPCM_TWP(0x1f))
238 #define CONFIG_SYS_CS2_FTIM3 0x0
242 #define CONFIG_SYS_NAND_BASE 0xff800000
243 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
245 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
263 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
264 FTIM0_NAND_TWP(0x18) | \
265 FTIM0_NAND_TWCHT(0x07) | \
266 FTIM0_NAND_TWH(0x0a))
267 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
268 FTIM1_NAND_TWBE(0x39) | \
269 FTIM1_NAND_TRR(0x0e) | \
270 FTIM1_NAND_TRP(0x18))
271 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
272 FTIM2_NAND_TREH(0x0a) | \
273 FTIM2_NAND_TWHRE(0x1e))
274 #define CONFIG_SYS_NAND_FTIM3 0x0
332 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
333 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
334 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
339 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
351 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
354 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
355 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
356 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
357 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
364 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
365 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
366 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
367 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
368 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
369 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
370 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
371 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
376 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
377 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
378 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
379 #define I2C_MUX_CH_DEFAULT 0x8
381 #define I2C_MUX_CH_VOL_MONITOR 0xa
396 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
397 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
398 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
399 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
400 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
401 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
406 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
407 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
408 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
409 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
414 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
415 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
416 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
419 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
420 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
426 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
428 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
437 * Memory space is mapped 1-1, but I/O space must start from 0.
446 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
447 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
448 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
449 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
450 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
451 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
453 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
456 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
457 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
458 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
459 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
460 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
461 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
462 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
463 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
466 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
467 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
468 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
469 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
470 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
471 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
472 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
473 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
476 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
477 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
478 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
479 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
480 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
481 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
482 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
493 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
494 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
495 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
496 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
497 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
503 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
505 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
506 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
507 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
508 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
509 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
515 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
527 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
528 * env, so we got 0x110000.
532 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
533 #define CONFIG_CORTINA_FW_ADDR 0x120000
537 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
539 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
543 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
544 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
561 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
562 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
566 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
567 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
569 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
570 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
577 #define CONFIG_CORTINA_FW_LENGTH 0x40000
578 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
579 #define RGMII_PHY2_ADDR 0x02
580 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
581 #define CORTINA_PHY_ADDR2 0x0d
582 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
583 #define FM1_10GEC4_PHY_ADDR 0x01
633 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
663 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
664 "netdev=eth0\0" \
665 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
666 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
672 "cmp.b $loadaddr $ubootaddr $filesize\0" \
673 "consoledev=ttyS0\0" \
674 "ramdiskaddr=2000000\0" \
675 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
676 "fdtaddr=1e00000\0" \
677 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
678 "bdev=sda3\0"
687 "cpu 1 release 0x29000000 - - -;" \
688 "cpu 2 release 0x29000000 - - -;" \
689 "cpu 3 release 0x29000000 - - -;" \
690 "cpu 4 release 0x29000000 - - -;" \
691 "cpu 5 release 0x29000000 - - -;" \
692 "cpu 6 release 0x29000000 - - -;" \
693 "cpu 7 release 0x29000000 - - -;" \
694 "go 0x29000000"
697 "setenv bootargs config-addr=0x60000000; " \
698 "bootm 0x01000000 - 0x00f00000"
703 "cpu 1 release 0x01000000 - - -;" \
704 "cpu 2 release 0x01000000 - - -;" \
705 "cpu 3 release 0x01000000 - - -;" \
706 "cpu 4 release 0x01000000 - - -;" \
707 "cpu 5 release 0x01000000 - - -;" \
708 "cpu 6 release 0x01000000 - - -;" \
709 "cpu 7 release 0x01000000 - - -;" \
710 "go 0x01000000"
715 "setenv ramdiskaddr 0x02000000;" \
716 "setenv fdtaddr 0x00c00000;" \
717 "setenv loadaddr 0x1000000;" \