arm64: tegra: Fix flag for 64-bit resources in 'ranges' property

Fix flag in PCIe controllers device-tree nodes 'ranges' property to correctly
represent 64-bit resources.

Fixes:

arm64: tegra: Fix flag for 64-bit resources in 'ranges' property

Fix flag in PCIe controllers device-tree nodes 'ranges' property to correctly
represent 64-bit resources.

Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add XUDC node on Tegra194

Tegra194 has one XUSB device mode controller which can be operated in HS
and SS modes. Add a DT node for this XUSB device mode controller.

arm64: tegra: Add XUDC node on Tegra194

Tegra194 has one XUSB device mode controller which can be operated in HS
and SS modes. Add a DT node for this XUSB device mode controller.

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194

Add endpoint mode controllers nodes for the dual mode PCIe controllers
present in Tegra194 SoC.

Signed-off-by: Vid

arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194

Add endpoint mode controllers nodes for the dual mode PCIe controllers
present in Tegra194 SoC.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add XUSB and pad controller on Tegra194

Adds the XUSB pad and XUSB controllers on Tegra194.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding

arm64: tegra: Add XUSB and pad controller on Tegra194

Adds the XUSB pad and XUSB controllers on Tegra194.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix Tegra194 PCIe compatible string

If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled
then this can cause the kernel to incorrectly probe the generic

arm64: tegra: Fix Tegra194 PCIe compatible string

If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled
then this can cause the kernel to incorrectly probe the generic
designware PCIe platform driver instead of the Tegra194 designware PCIe
driver. This causes a boot failure on Tegra194 because the necessary
configuration to access the hardware is not performed.

The order in which the compatible strings are populated in Device-Tree
is not relevant in this case, because the kernel will attempt to probe
the device as soon as a driver is loaded and if the generic designware
PCIe driver is loaded first, then this driver will be probed first.
Therefore, to fix this problem, remove the "snps,dw-pcie" string from
the compatible string as we never want this driver to be probe on
Tegra194.

Fixes: 2602c32f15e7 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add fuse/apbmisc node on Tegra194

This commit adds Tegra194 fuse and apbmisc device nodes.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <

arm64: tegra: Add fuse/apbmisc node on Tegra194

This commit adds Tegra194 fuse and apbmisc device nodes.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add the memory subsystem on Tegra194

The memory subsystem on Tegra194 encompasses both the memory and
external memory controllers. The EMC is represented as a subnode of th

arm64: tegra: Add the memory subsystem on Tegra194

The memory subsystem on Tegra194 encompasses both the memory and
external memory controllers. The EMC is represented as a subnode of the
MC and a ranges property is used to describe the register ranges.

A dma-ranges property is also added to describe that all memory clients
can address up to 39 bits using the memory controller client interface
(MCCIF), unless otherwise limited by the DMA engines of the hardware. A
memory client can technically use 40 bits of addresses, but the memory
controller on Tegra194 uses bit 39 to determine the XBAR format used to
access memory. Use of this bit needs to be explicitly controlled by the
operating system drivers for devices that can use this on-the-fly format
conversion. Using the dma-ranges property prevents the operating system
from using the bit implicitly, for example in I/O virtual address
mappings.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Assume no CLKREQ presence by default

Although Tegra194 has support for CLKREQ sideband signal and P2972
has routing of the same till the slot, it is the case most of the ti

arm64: tegra: Assume no CLKREQ presence by default

Although Tegra194 has support for CLKREQ sideband signal and P2972
has routing of the same till the slot, it is the case most of the time
that the connected device doesn't have CLKREQ support. Hence, it makes
sense to assume that there is no CLKREQ support by default and it can
be enabled on need basis when a card with CLKREQ support is connected.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix compatible string for EQOS on Tegra194

The EQOS Ethernet controller found on Tegra194 is compatible with its
predecessor or Tegra186. However, it is an established prac

arm64: tegra: Fix compatible string for EQOS on Tegra194

The EQOS Ethernet controller found on Tegra194 is compatible with its
predecessor or Tegra186. However, it is an established practice to add
a compatible string for the most recent generation of the SoC as well,
just in case some incompatibilities or bugs are later discovered.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Fix base address for SOR1 on Tegra194

The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg prope

arm64: tegra: Fix base address for SOR1 on Tegra194

The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add unit-address for ACONNECT on Tegra194

The ACONNECT complex starts at physical address 0x2900000, so give it a
unit-address to comply with standard naming practices chec

arm64: tegra: Add unit-address for ACONNECT on Tegra194

The ACONNECT complex starts at physical address 0x2900000, so give it a
unit-address to comply with standard naming practices checked for by the
device tree compiler.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add unit-address for CBB on Tegra194

The control back-bone (CBB) starts at physical address 0, so give it a
unit-address to comply with standard naming practices checked fo

arm64: tegra: Add unit-address for CBB on Tegra194

The control back-bone (CBB) starts at physical address 0, so give it a
unit-address to comply with standard naming practices checked for by the
device tree compiler.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CPU and cache topology for Tegra194

Tegra194 has four CPU clusters, each with their own cache hierarchy.
This patch creates the CPU map for these clusters and adds the

arm64: tegra: Add CPU and cache topology for Tegra194

Tegra194 has four CPU clusters, each with their own cache hierarchy.
This patch creates the CPU map for these clusters and adds the second-
and third-level caches and associates them with the CPUs.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add configuration for PCIe C5 sideband signals

Add support to configure PCIe C5's sideband signals PERST# and CLKREQ#
as output and bi-directional signals respectively whic

arm64: tegra: Add configuration for PCIe C5 sideband signals

Add support to configure PCIe C5's sideband signals PERST# and CLKREQ#
as output and bi-directional signals respectively which unlike other
PCIe controllers sideband signals are not configured by default.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>

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arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT

Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty

arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT

Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
and NVIDIA High Speed (NVHS-8 P2Us) respectively.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add ACONNECT, ADMA and AGIC nodes

Add device tree nodes for the ACONNECT, ADMA and AGIC devices on
Tegra186 and Tegra194.

Signed-off-by: Sameer Pujar <spujar@nvidi

arm64: tegra: Add ACONNECT, ADMA and AGIC nodes

Add device tree nodes for the ACONNECT, ADMA and AGIC devices on
Tegra186 and Tegra194.

Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Mark architected timer as always on

The architected timer on Tegra186 and Tegra194 is in an always on power
partition and its reference clock will always run, so mark the t

arm64: tegra: Mark architected timer as always on

The architected timer on Tegra186 and Tegra194 is in an always on power
partition and its reference clock will always run, so mark the timer as
always on.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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Merge tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.1-rc1

This contains a couple of

Merge tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.1-rc1

This contains a couple of fixes to existing device trees, enables CPU
frequency scaling on various Tegra210 boards, enables the TCU as debug
serial port on Jetson Xavier, adds various improvements for SDMMC on
Tegra210, Tegra186 and Tegra194 boards and finally adds initial support
for the NVIDIA Shield TV.

* tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits)
arm64: tegra: Update compatible for Tegra186 I2C
arm64: tegra: Update compatible for Tegra210 I2C
arm64: tegra: Support 200 MHz for SDMMC on Tegra194
arm64: tegra: Add CQE Support for SDMMC4
arm64: tegra: Add SDMMC auto-calibration settings
arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888
arm64: tegra: Add nodes for TCU on Tegra194
arm64: tegra: Enable DFLL clock on Smaug
arm64: tegra: Add CPU power rail regulator on Smaug
arm64: tegra: Enable DFLL clock on Jetson TX1
arm64: tegra: Add pinmux for PWM-based DFLL support on P2597
arm64: tegra: Add CPU clocks on Tegra210
arm64: tegra: Add DFLL clock on Tegra210
arm64: tegra: p2771-0000: Use TEGRA186_ prefix for GPIO names
arm64: tegra: p3310: Use TEGRA186_ prefix for GPIO names
arm64: tegra: p2597: Sort nodes by unit-address
arm64: tegra: p2972: Sort nodes properly
arm64: tegra: Add regulators for Tegra210 Darcy
arm64: tegra: Add pinmux for Darcy board
arm64: tegra: Add gpio-keys nodes for Darcy
...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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arm64: tegra: Support 200 MHz for SDMMC on Tegra194

Change the SDMMC clock source to support a maximum frequency of 200 MHz
on Tegra194.

Signed-off-by: Sowjanya Komatineni <skom

arm64: tegra: Support 200 MHz for SDMMC on Tegra194

Change the SDMMC clock source to support a maximum frequency of 200 MHz
on Tegra194.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CQE Support for SDMMC4

Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: T

arm64: tegra: Add CQE Support for SDMMC4

Add CQE Support for Tegra186 and Tegra194 SDMMC4 controller

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add SDMMC auto-calibration settings

Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegr

arm64: tegra: Add SDMMC auto-calibration settings

Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegra194 which are used when calibration timeouts.

Fixed drive strengths are based on Pre SI Analysis of the pads.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add nodes for TCU on Tegra194

Add nodes required for communication through the Tegra Combined UART.
This includes the AON HSP instance, addition of shared interrupts
fo

arm64: tegra: Add nodes for TCU on Tegra194

Add nodes required for communication through the Tegra Combined UART.
This includes the AON HSP instance, addition of shared interrupts
for the TOP0 HSP instance, and finally the TCU node itself. Also
mark the HSP instances as compatible to tegra194-hsp, as the hardware
is not identical but is compatible to tegra186-hsp.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently u

arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Chanho Min <chanho.min@lge.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
Acked-by: Robert Richter <rrichter@cavium.com>
Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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arm64: tegra: Set reg property for display-hub on Tegra194

Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the di

arm64: tegra: Set reg property for display-hub on Tegra194

Technically the display-hub driver could access registers via the
specified region, though it practice it will do so via the display
controllers' register regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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arm64: tegra: Add CEC controller on Tegra194

The CEC controller found on Tegra194 can be used to control consumer
devices using the HDMI CEC pin.

Signed-off-by: Thierry Reding <

arm64: tegra: Add CEC controller on Tegra194

The CEC controller found on Tegra194 can be used to control consumer
devices using the HDMI CEC pin.

Signed-off-by: Thierry Reding <treding@nvidia.com>

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