1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra.h> 7#include <dt-bindings/power/tegra194-powergate.h> 8#include <dt-bindings/reset/tegra194-reset.h> 9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 10#include <dt-bindings/memory/tegra194-mc.h> 11 12/ { 13 compatible = "nvidia,tegra194"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* control backbone */ 19 cbb@0 { 20 compatible = "simple-bus"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 ranges = <0x0 0x0 0x0 0x40000000>; 24 25 gpio: gpio@2200000 { 26 compatible = "nvidia,tegra194-gpio"; 27 reg-names = "security", "gpio"; 28 reg = <0x2200000 0x10000>, 29 <0x2210000 0x10000>; 30 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 36 #interrupt-cells = <2>; 37 interrupt-controller; 38 #gpio-cells = <2>; 39 gpio-controller; 40 }; 41 42 ethernet@2490000 { 43 compatible = "nvidia,tegra194-eqos", 44 "nvidia,tegra186-eqos", 45 "snps,dwc-qos-ethernet-4.10"; 46 reg = <0x02490000 0x10000>; 47 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 48 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 49 <&bpmp TEGRA194_CLK_EQOS_AXI>, 50 <&bpmp TEGRA194_CLK_EQOS_RX>, 51 <&bpmp TEGRA194_CLK_EQOS_TX>, 52 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 53 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 54 resets = <&bpmp TEGRA194_RESET_EQOS>; 55 reset-names = "eqos"; 56 status = "disabled"; 57 58 snps,write-requests = <1>; 59 snps,read-requests = <3>; 60 snps,burst-map = <0x7>; 61 snps,txpbl = <16>; 62 snps,rxpbl = <8>; 63 }; 64 65 aconnect@2900000 { 66 compatible = "nvidia,tegra194-aconnect", 67 "nvidia,tegra210-aconnect"; 68 clocks = <&bpmp TEGRA194_CLK_APE>, 69 <&bpmp TEGRA194_CLK_APB2APE>; 70 clock-names = "ape", "apb2ape"; 71 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges = <0x02900000 0x02900000 0x200000>; 75 status = "disabled"; 76 77 dma-controller@2930000 { 78 compatible = "nvidia,tegra194-adma", 79 "nvidia,tegra186-adma"; 80 reg = <0x02930000 0x20000>; 81 interrupt-parent = <&agic>; 82 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 114 #dma-cells = <1>; 115 clocks = <&bpmp TEGRA194_CLK_AHUB>; 116 clock-names = "d_audio"; 117 status = "disabled"; 118 }; 119 120 agic: interrupt-controller@2a40000 { 121 compatible = "nvidia,tegra194-agic", 122 "nvidia,tegra210-agic"; 123 #interrupt-cells = <3>; 124 interrupt-controller; 125 reg = <0x02a41000 0x1000>, 126 <0x02a42000 0x2000>; 127 interrupts = <GIC_SPI 145 128 (GIC_CPU_MASK_SIMPLE(4) | 129 IRQ_TYPE_LEVEL_HIGH)>; 130 clocks = <&bpmp TEGRA194_CLK_APE>; 131 clock-names = "clk"; 132 status = "disabled"; 133 }; 134 }; 135 136 pinmux: pinmux@2430000 { 137 compatible = "nvidia,tegra194-pinmux"; 138 reg = <0x2430000 0x17000 139 0xc300000 0x4000>; 140 141 status = "okay"; 142 143 pex_rst_c5_out_state: pex_rst_c5_out { 144 pex_rst { 145 nvidia,pins = "pex_l5_rst_n_pgg1"; 146 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 147 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 148 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 149 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 150 nvidia,tristate = <TEGRA_PIN_DISABLE>; 151 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 152 }; 153 }; 154 155 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 156 clkreq { 157 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 158 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 159 nvidia,lpdr = <TEGRA_PIN_ENABLE>; 160 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 161 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>; 162 nvidia,tristate = <TEGRA_PIN_DISABLE>; 163 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 164 }; 165 }; 166 }; 167 168 mc: memory-controller@2c00000 { 169 compatible = "nvidia,tegra194-mc"; 170 reg = <0x02c00000 0x100000>, 171 <0x02b80000 0x040000>, 172 <0x01700000 0x100000>; 173 status = "disabled"; 174 175 #address-cells = <2>; 176 #size-cells = <2>; 177 178 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 179 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 180 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 181 182 /* 183 * Bit 39 of addresses passing through the memory 184 * controller selects the XBAR format used when memory 185 * is accessed. This is used to transparently access 186 * memory in the XBAR format used by the discrete GPU 187 * (bit 39 set) or Tegra (bit 39 clear). 188 * 189 * As a consequence, the operating system must ensure 190 * that bit 39 is never used implicitly, for example 191 * via an I/O virtual address mapping of an IOMMU. If 192 * devices require access to the XBAR switch, their 193 * drivers must set this bit explicitly. 194 * 195 * Limit the DMA range for memory clients to [38:0]. 196 */ 197 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 198 199 emc: external-memory-controller@2c60000 { 200 compatible = "nvidia,tegra194-emc"; 201 reg = <0x0 0x02c60000 0x0 0x90000>, 202 <0x0 0x01780000 0x0 0x80000>; 203 clocks = <&bpmp TEGRA194_CLK_EMC>; 204 clock-names = "emc"; 205 206 nvidia,bpmp = <&bpmp>; 207 }; 208 }; 209 210 uarta: serial@3100000 { 211 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 212 reg = <0x03100000 0x40>; 213 reg-shift = <2>; 214 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&bpmp TEGRA194_CLK_UARTA>; 216 clock-names = "serial"; 217 resets = <&bpmp TEGRA194_RESET_UARTA>; 218 reset-names = "serial"; 219 status = "disabled"; 220 }; 221 222 uartb: serial@3110000 { 223 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 224 reg = <0x03110000 0x40>; 225 reg-shift = <2>; 226 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&bpmp TEGRA194_CLK_UARTB>; 228 clock-names = "serial"; 229 resets = <&bpmp TEGRA194_RESET_UARTB>; 230 reset-names = "serial"; 231 status = "disabled"; 232 }; 233 234 uartd: serial@3130000 { 235 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 236 reg = <0x03130000 0x40>; 237 reg-shift = <2>; 238 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&bpmp TEGRA194_CLK_UARTD>; 240 clock-names = "serial"; 241 resets = <&bpmp TEGRA194_RESET_UARTD>; 242 reset-names = "serial"; 243 status = "disabled"; 244 }; 245 246 uarte: serial@3140000 { 247 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 248 reg = <0x03140000 0x40>; 249 reg-shift = <2>; 250 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&bpmp TEGRA194_CLK_UARTE>; 252 clock-names = "serial"; 253 resets = <&bpmp TEGRA194_RESET_UARTE>; 254 reset-names = "serial"; 255 status = "disabled"; 256 }; 257 258 uartf: serial@3150000 { 259 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 260 reg = <0x03150000 0x40>; 261 reg-shift = <2>; 262 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&bpmp TEGRA194_CLK_UARTF>; 264 clock-names = "serial"; 265 resets = <&bpmp TEGRA194_RESET_UARTF>; 266 reset-names = "serial"; 267 status = "disabled"; 268 }; 269 270 gen1_i2c: i2c@3160000 { 271 compatible = "nvidia,tegra194-i2c"; 272 reg = <0x03160000 0x10000>; 273 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 clocks = <&bpmp TEGRA194_CLK_I2C1>; 277 clock-names = "div-clk"; 278 resets = <&bpmp TEGRA194_RESET_I2C1>; 279 reset-names = "i2c"; 280 status = "disabled"; 281 }; 282 283 uarth: serial@3170000 { 284 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 285 reg = <0x03170000 0x40>; 286 reg-shift = <2>; 287 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&bpmp TEGRA194_CLK_UARTH>; 289 clock-names = "serial"; 290 resets = <&bpmp TEGRA194_RESET_UARTH>; 291 reset-names = "serial"; 292 status = "disabled"; 293 }; 294 295 cam_i2c: i2c@3180000 { 296 compatible = "nvidia,tegra194-i2c"; 297 reg = <0x03180000 0x10000>; 298 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 clocks = <&bpmp TEGRA194_CLK_I2C3>; 302 clock-names = "div-clk"; 303 resets = <&bpmp TEGRA194_RESET_I2C3>; 304 reset-names = "i2c"; 305 status = "disabled"; 306 }; 307 308 /* shares pads with dpaux1 */ 309 dp_aux_ch1_i2c: i2c@3190000 { 310 compatible = "nvidia,tegra194-i2c"; 311 reg = <0x03190000 0x10000>; 312 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 clocks = <&bpmp TEGRA194_CLK_I2C4>; 316 clock-names = "div-clk"; 317 resets = <&bpmp TEGRA194_RESET_I2C4>; 318 reset-names = "i2c"; 319 status = "disabled"; 320 }; 321 322 /* shares pads with dpaux0 */ 323 dp_aux_ch0_i2c: i2c@31b0000 { 324 compatible = "nvidia,tegra194-i2c"; 325 reg = <0x031b0000 0x10000>; 326 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 clocks = <&bpmp TEGRA194_CLK_I2C6>; 330 clock-names = "div-clk"; 331 resets = <&bpmp TEGRA194_RESET_I2C6>; 332 reset-names = "i2c"; 333 status = "disabled"; 334 }; 335 336 gen7_i2c: i2c@31c0000 { 337 compatible = "nvidia,tegra194-i2c"; 338 reg = <0x031c0000 0x10000>; 339 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 clocks = <&bpmp TEGRA194_CLK_I2C7>; 343 clock-names = "div-clk"; 344 resets = <&bpmp TEGRA194_RESET_I2C7>; 345 reset-names = "i2c"; 346 status = "disabled"; 347 }; 348 349 gen9_i2c: i2c@31e0000 { 350 compatible = "nvidia,tegra194-i2c"; 351 reg = <0x031e0000 0x10000>; 352 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 clocks = <&bpmp TEGRA194_CLK_I2C9>; 356 clock-names = "div-clk"; 357 resets = <&bpmp TEGRA194_RESET_I2C9>; 358 reset-names = "i2c"; 359 status = "disabled"; 360 }; 361 362 pwm1: pwm@3280000 { 363 compatible = "nvidia,tegra194-pwm", 364 "nvidia,tegra186-pwm"; 365 reg = <0x3280000 0x10000>; 366 clocks = <&bpmp TEGRA194_CLK_PWM1>; 367 clock-names = "pwm"; 368 resets = <&bpmp TEGRA194_RESET_PWM1>; 369 reset-names = "pwm"; 370 status = "disabled"; 371 #pwm-cells = <2>; 372 }; 373 374 pwm2: pwm@3290000 { 375 compatible = "nvidia,tegra194-pwm", 376 "nvidia,tegra186-pwm"; 377 reg = <0x3290000 0x10000>; 378 clocks = <&bpmp TEGRA194_CLK_PWM2>; 379 clock-names = "pwm"; 380 resets = <&bpmp TEGRA194_RESET_PWM2>; 381 reset-names = "pwm"; 382 status = "disabled"; 383 #pwm-cells = <2>; 384 }; 385 386 pwm3: pwm@32a0000 { 387 compatible = "nvidia,tegra194-pwm", 388 "nvidia,tegra186-pwm"; 389 reg = <0x32a0000 0x10000>; 390 clocks = <&bpmp TEGRA194_CLK_PWM3>; 391 clock-names = "pwm"; 392 resets = <&bpmp TEGRA194_RESET_PWM3>; 393 reset-names = "pwm"; 394 status = "disabled"; 395 #pwm-cells = <2>; 396 }; 397 398 pwm5: pwm@32c0000 { 399 compatible = "nvidia,tegra194-pwm", 400 "nvidia,tegra186-pwm"; 401 reg = <0x32c0000 0x10000>; 402 clocks = <&bpmp TEGRA194_CLK_PWM5>; 403 clock-names = "pwm"; 404 resets = <&bpmp TEGRA194_RESET_PWM5>; 405 reset-names = "pwm"; 406 status = "disabled"; 407 #pwm-cells = <2>; 408 }; 409 410 pwm6: pwm@32d0000 { 411 compatible = "nvidia,tegra194-pwm", 412 "nvidia,tegra186-pwm"; 413 reg = <0x32d0000 0x10000>; 414 clocks = <&bpmp TEGRA194_CLK_PWM6>; 415 clock-names = "pwm"; 416 resets = <&bpmp TEGRA194_RESET_PWM6>; 417 reset-names = "pwm"; 418 status = "disabled"; 419 #pwm-cells = <2>; 420 }; 421 422 pwm7: pwm@32e0000 { 423 compatible = "nvidia,tegra194-pwm", 424 "nvidia,tegra186-pwm"; 425 reg = <0x32e0000 0x10000>; 426 clocks = <&bpmp TEGRA194_CLK_PWM7>; 427 clock-names = "pwm"; 428 resets = <&bpmp TEGRA194_RESET_PWM7>; 429 reset-names = "pwm"; 430 status = "disabled"; 431 #pwm-cells = <2>; 432 }; 433 434 pwm8: pwm@32f0000 { 435 compatible = "nvidia,tegra194-pwm", 436 "nvidia,tegra186-pwm"; 437 reg = <0x32f0000 0x10000>; 438 clocks = <&bpmp TEGRA194_CLK_PWM8>; 439 clock-names = "pwm"; 440 resets = <&bpmp TEGRA194_RESET_PWM8>; 441 reset-names = "pwm"; 442 status = "disabled"; 443 #pwm-cells = <2>; 444 }; 445 446 sdmmc1: sdhci@3400000 { 447 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 448 reg = <0x03400000 0x10000>; 449 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&bpmp TEGRA194_CLK_SDMMC1>; 451 clock-names = "sdhci"; 452 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 453 reset-names = "sdhci"; 454 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 455 <0x07>; 456 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 457 <0x07>; 458 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 459 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 460 <0x07>; 461 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 462 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 463 nvidia,default-tap = <0x9>; 464 nvidia,default-trim = <0x5>; 465 status = "disabled"; 466 }; 467 468 sdmmc3: sdhci@3440000 { 469 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 470 reg = <0x03440000 0x10000>; 471 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&bpmp TEGRA194_CLK_SDMMC3>; 473 clock-names = "sdhci"; 474 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 475 reset-names = "sdhci"; 476 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 477 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 478 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 479 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 480 <0x07>; 481 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 482 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 483 <0x07>; 484 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 485 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 486 nvidia,default-tap = <0x9>; 487 nvidia,default-trim = <0x5>; 488 status = "disabled"; 489 }; 490 491 sdmmc4: sdhci@3460000 { 492 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci"; 493 reg = <0x03460000 0x10000>; 494 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&bpmp TEGRA194_CLK_SDMMC4>; 496 clock-names = "sdhci"; 497 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 498 <&bpmp TEGRA194_CLK_PLLC4>; 499 assigned-clock-parents = 500 <&bpmp TEGRA194_CLK_PLLC4>; 501 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 502 reset-names = "sdhci"; 503 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 504 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 505 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 506 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 507 <0x0a>; 508 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 509 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 510 <0x0a>; 511 nvidia,default-tap = <0x8>; 512 nvidia,default-trim = <0x14>; 513 nvidia,dqs-trim = <40>; 514 supports-cqe; 515 status = "disabled"; 516 }; 517 518 hda@3510000 { 519 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 520 reg = <0x3510000 0x10000>; 521 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&bpmp TEGRA194_CLK_HDA>, 523 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>, 524 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>; 525 clock-names = "hda", "hda2codec_2x", "hda2hdmi"; 526 resets = <&bpmp TEGRA194_RESET_HDA>, 527 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>, 528 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 529 reset-names = "hda", "hda2codec_2x", "hda2hdmi"; 530 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 531 status = "disabled"; 532 }; 533 534 gic: interrupt-controller@3881000 { 535 compatible = "arm,gic-400"; 536 #interrupt-cells = <3>; 537 interrupt-controller; 538 reg = <0x03881000 0x1000>, 539 <0x03882000 0x2000>, 540 <0x03884000 0x2000>, 541 <0x03886000 0x2000>; 542 interrupts = <GIC_PPI 9 543 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 544 interrupt-parent = <&gic>; 545 }; 546 547 cec@3960000 { 548 compatible = "nvidia,tegra194-cec"; 549 reg = <0x03960000 0x10000>; 550 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&bpmp TEGRA194_CLK_CEC>; 552 clock-names = "cec"; 553 status = "disabled"; 554 }; 555 556 hsp_top0: hsp@3c00000 { 557 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 558 reg = <0x03c00000 0xa0000>; 559 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 568 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 569 "shared3", "shared4", "shared5", "shared6", 570 "shared7"; 571 #mbox-cells = <2>; 572 }; 573 574 p2u_hsio_0: phy@3e10000 { 575 compatible = "nvidia,tegra194-p2u"; 576 reg = <0x03e10000 0x10000>; 577 reg-names = "ctl"; 578 579 #phy-cells = <0>; 580 }; 581 582 p2u_hsio_1: phy@3e20000 { 583 compatible = "nvidia,tegra194-p2u"; 584 reg = <0x03e20000 0x10000>; 585 reg-names = "ctl"; 586 587 #phy-cells = <0>; 588 }; 589 590 p2u_hsio_2: phy@3e30000 { 591 compatible = "nvidia,tegra194-p2u"; 592 reg = <0x03e30000 0x10000>; 593 reg-names = "ctl"; 594 595 #phy-cells = <0>; 596 }; 597 598 p2u_hsio_3: phy@3e40000 { 599 compatible = "nvidia,tegra194-p2u"; 600 reg = <0x03e40000 0x10000>; 601 reg-names = "ctl"; 602 603 #phy-cells = <0>; 604 }; 605 606 p2u_hsio_4: phy@3e50000 { 607 compatible = "nvidia,tegra194-p2u"; 608 reg = <0x03e50000 0x10000>; 609 reg-names = "ctl"; 610 611 #phy-cells = <0>; 612 }; 613 614 p2u_hsio_5: phy@3e60000 { 615 compatible = "nvidia,tegra194-p2u"; 616 reg = <0x03e60000 0x10000>; 617 reg-names = "ctl"; 618 619 #phy-cells = <0>; 620 }; 621 622 p2u_hsio_6: phy@3e70000 { 623 compatible = "nvidia,tegra194-p2u"; 624 reg = <0x03e70000 0x10000>; 625 reg-names = "ctl"; 626 627 #phy-cells = <0>; 628 }; 629 630 p2u_hsio_7: phy@3e80000 { 631 compatible = "nvidia,tegra194-p2u"; 632 reg = <0x03e80000 0x10000>; 633 reg-names = "ctl"; 634 635 #phy-cells = <0>; 636 }; 637 638 p2u_hsio_8: phy@3e90000 { 639 compatible = "nvidia,tegra194-p2u"; 640 reg = <0x03e90000 0x10000>; 641 reg-names = "ctl"; 642 643 #phy-cells = <0>; 644 }; 645 646 p2u_hsio_9: phy@3ea0000 { 647 compatible = "nvidia,tegra194-p2u"; 648 reg = <0x03ea0000 0x10000>; 649 reg-names = "ctl"; 650 651 #phy-cells = <0>; 652 }; 653 654 p2u_nvhs_0: phy@3eb0000 { 655 compatible = "nvidia,tegra194-p2u"; 656 reg = <0x03eb0000 0x10000>; 657 reg-names = "ctl"; 658 659 #phy-cells = <0>; 660 }; 661 662 p2u_nvhs_1: phy@3ec0000 { 663 compatible = "nvidia,tegra194-p2u"; 664 reg = <0x03ec0000 0x10000>; 665 reg-names = "ctl"; 666 667 #phy-cells = <0>; 668 }; 669 670 p2u_nvhs_2: phy@3ed0000 { 671 compatible = "nvidia,tegra194-p2u"; 672 reg = <0x03ed0000 0x10000>; 673 reg-names = "ctl"; 674 675 #phy-cells = <0>; 676 }; 677 678 p2u_nvhs_3: phy@3ee0000 { 679 compatible = "nvidia,tegra194-p2u"; 680 reg = <0x03ee0000 0x10000>; 681 reg-names = "ctl"; 682 683 #phy-cells = <0>; 684 }; 685 686 p2u_nvhs_4: phy@3ef0000 { 687 compatible = "nvidia,tegra194-p2u"; 688 reg = <0x03ef0000 0x10000>; 689 reg-names = "ctl"; 690 691 #phy-cells = <0>; 692 }; 693 694 p2u_nvhs_5: phy@3f00000 { 695 compatible = "nvidia,tegra194-p2u"; 696 reg = <0x03f00000 0x10000>; 697 reg-names = "ctl"; 698 699 #phy-cells = <0>; 700 }; 701 702 p2u_nvhs_6: phy@3f10000 { 703 compatible = "nvidia,tegra194-p2u"; 704 reg = <0x03f10000 0x10000>; 705 reg-names = "ctl"; 706 707 #phy-cells = <0>; 708 }; 709 710 p2u_nvhs_7: phy@3f20000 { 711 compatible = "nvidia,tegra194-p2u"; 712 reg = <0x03f20000 0x10000>; 713 reg-names = "ctl"; 714 715 #phy-cells = <0>; 716 }; 717 718 p2u_hsio_10: phy@3f30000 { 719 compatible = "nvidia,tegra194-p2u"; 720 reg = <0x03f30000 0x10000>; 721 reg-names = "ctl"; 722 723 #phy-cells = <0>; 724 }; 725 726 p2u_hsio_11: phy@3f40000 { 727 compatible = "nvidia,tegra194-p2u"; 728 reg = <0x03f40000 0x10000>; 729 reg-names = "ctl"; 730 731 #phy-cells = <0>; 732 }; 733 734 hsp_aon: hsp@c150000 { 735 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"; 736 reg = <0x0c150000 0xa0000>; 737 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 741 /* 742 * Shared interrupt 0 is routed only to AON/SPE, so 743 * we only have 4 shared interrupts for the CCPLEX. 744 */ 745 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 746 #mbox-cells = <2>; 747 }; 748 749 gen2_i2c: i2c@c240000 { 750 compatible = "nvidia,tegra194-i2c"; 751 reg = <0x0c240000 0x10000>; 752 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 clocks = <&bpmp TEGRA194_CLK_I2C2>; 756 clock-names = "div-clk"; 757 resets = <&bpmp TEGRA194_RESET_I2C2>; 758 reset-names = "i2c"; 759 status = "disabled"; 760 }; 761 762 gen8_i2c: i2c@c250000 { 763 compatible = "nvidia,tegra194-i2c"; 764 reg = <0x0c250000 0x10000>; 765 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 clocks = <&bpmp TEGRA194_CLK_I2C8>; 769 clock-names = "div-clk"; 770 resets = <&bpmp TEGRA194_RESET_I2C8>; 771 reset-names = "i2c"; 772 status = "disabled"; 773 }; 774 775 uartc: serial@c280000 { 776 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 777 reg = <0x0c280000 0x40>; 778 reg-shift = <2>; 779 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&bpmp TEGRA194_CLK_UARTC>; 781 clock-names = "serial"; 782 resets = <&bpmp TEGRA194_RESET_UARTC>; 783 reset-names = "serial"; 784 status = "disabled"; 785 }; 786 787 uartg: serial@c290000 { 788 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 789 reg = <0x0c290000 0x40>; 790 reg-shift = <2>; 791 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&bpmp TEGRA194_CLK_UARTG>; 793 clock-names = "serial"; 794 resets = <&bpmp TEGRA194_RESET_UARTG>; 795 reset-names = "serial"; 796 status = "disabled"; 797 }; 798 799 rtc: rtc@c2a0000 { 800 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 801 reg = <0x0c2a0000 0x10000>; 802 interrupt-parent = <&pmc>; 803 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 805 clock-names = "rtc"; 806 status = "disabled"; 807 }; 808 809 gpio_aon: gpio@c2f0000 { 810 compatible = "nvidia,tegra194-gpio-aon"; 811 reg-names = "security", "gpio"; 812 reg = <0xc2f0000 0x1000>, 813 <0xc2f1000 0x1000>; 814 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 818 gpio-controller; 819 #gpio-cells = <2>; 820 interrupt-controller; 821 #interrupt-cells = <2>; 822 }; 823 824 pwm4: pwm@c340000 { 825 compatible = "nvidia,tegra194-pwm", 826 "nvidia,tegra186-pwm"; 827 reg = <0xc340000 0x10000>; 828 clocks = <&bpmp TEGRA194_CLK_PWM4>; 829 clock-names = "pwm"; 830 resets = <&bpmp TEGRA194_RESET_PWM4>; 831 reset-names = "pwm"; 832 status = "disabled"; 833 #pwm-cells = <2>; 834 }; 835 836 pmc: pmc@c360000 { 837 compatible = "nvidia,tegra194-pmc"; 838 reg = <0x0c360000 0x10000>, 839 <0x0c370000 0x10000>, 840 <0x0c380000 0x10000>, 841 <0x0c390000 0x10000>, 842 <0x0c3a0000 0x10000>; 843 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 844 845 #interrupt-cells = <2>; 846 interrupt-controller; 847 }; 848 849 host1x@13e00000 { 850 compatible = "nvidia,tegra194-host1x", "simple-bus"; 851 reg = <0x13e00000 0x10000>, 852 <0x13e10000 0x10000>; 853 reg-names = "hypervisor", "vm"; 854 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 856 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 857 clock-names = "host1x"; 858 resets = <&bpmp TEGRA194_RESET_HOST1X>; 859 reset-names = "host1x"; 860 861 #address-cells = <1>; 862 #size-cells = <1>; 863 864 ranges = <0x15000000 0x15000000 0x01000000>; 865 866 display-hub@15200000 { 867 compatible = "nvidia,tegra194-display", "simple-bus"; 868 reg = <0x15200000 0x00040000>; 869 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 870 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 871 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 872 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 873 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 874 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 875 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 876 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 877 "wgrp3", "wgrp4", "wgrp5"; 878 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 879 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 880 clock-names = "disp", "hub"; 881 status = "disabled"; 882 883 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 884 885 #address-cells = <1>; 886 #size-cells = <1>; 887 888 ranges = <0x15200000 0x15200000 0x40000>; 889 890 display@15200000 { 891 compatible = "nvidia,tegra194-dc"; 892 reg = <0x15200000 0x10000>; 893 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 895 clock-names = "dc"; 896 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 897 reset-names = "dc"; 898 899 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 900 901 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 902 nvidia,head = <0>; 903 }; 904 905 display@15210000 { 906 compatible = "nvidia,tegra194-dc"; 907 reg = <0x15210000 0x10000>; 908 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 910 clock-names = "dc"; 911 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 912 reset-names = "dc"; 913 914 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 915 916 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 917 nvidia,head = <1>; 918 }; 919 920 display@15220000 { 921 compatible = "nvidia,tegra194-dc"; 922 reg = <0x15220000 0x10000>; 923 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 925 clock-names = "dc"; 926 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 927 reset-names = "dc"; 928 929 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 930 931 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 932 nvidia,head = <2>; 933 }; 934 935 display@15230000 { 936 compatible = "nvidia,tegra194-dc"; 937 reg = <0x15230000 0x10000>; 938 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 940 clock-names = "dc"; 941 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 942 reset-names = "dc"; 943 944 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 945 946 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 947 nvidia,head = <3>; 948 }; 949 }; 950 951 vic@15340000 { 952 compatible = "nvidia,tegra194-vic"; 953 reg = <0x15340000 0x00040000>; 954 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&bpmp TEGRA194_CLK_VIC>; 956 clock-names = "vic"; 957 resets = <&bpmp TEGRA194_RESET_VIC>; 958 reset-names = "vic"; 959 960 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 961 }; 962 963 dpaux0: dpaux@155c0000 { 964 compatible = "nvidia,tegra194-dpaux"; 965 reg = <0x155c0000 0x10000>; 966 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 968 <&bpmp TEGRA194_CLK_PLLDP>; 969 clock-names = "dpaux", "parent"; 970 resets = <&bpmp TEGRA194_RESET_DPAUX>; 971 reset-names = "dpaux"; 972 status = "disabled"; 973 974 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 975 976 state_dpaux0_aux: pinmux-aux { 977 groups = "dpaux-io"; 978 function = "aux"; 979 }; 980 981 state_dpaux0_i2c: pinmux-i2c { 982 groups = "dpaux-io"; 983 function = "i2c"; 984 }; 985 986 state_dpaux0_off: pinmux-off { 987 groups = "dpaux-io"; 988 function = "off"; 989 }; 990 991 i2c-bus { 992 #address-cells = <1>; 993 #size-cells = <0>; 994 }; 995 }; 996 997 dpaux1: dpaux@155d0000 { 998 compatible = "nvidia,tegra194-dpaux"; 999 reg = <0x155d0000 0x10000>; 1000 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 1002 <&bpmp TEGRA194_CLK_PLLDP>; 1003 clock-names = "dpaux", "parent"; 1004 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 1005 reset-names = "dpaux"; 1006 status = "disabled"; 1007 1008 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1009 1010 state_dpaux1_aux: pinmux-aux { 1011 groups = "dpaux-io"; 1012 function = "aux"; 1013 }; 1014 1015 state_dpaux1_i2c: pinmux-i2c { 1016 groups = "dpaux-io"; 1017 function = "i2c"; 1018 }; 1019 1020 state_dpaux1_off: pinmux-off { 1021 groups = "dpaux-io"; 1022 function = "off"; 1023 }; 1024 1025 i2c-bus { 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 }; 1029 }; 1030 1031 dpaux2: dpaux@155e0000 { 1032 compatible = "nvidia,tegra194-dpaux"; 1033 reg = <0x155e0000 0x10000>; 1034 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 1036 <&bpmp TEGRA194_CLK_PLLDP>; 1037 clock-names = "dpaux", "parent"; 1038 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 1039 reset-names = "dpaux"; 1040 status = "disabled"; 1041 1042 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1043 1044 state_dpaux2_aux: pinmux-aux { 1045 groups = "dpaux-io"; 1046 function = "aux"; 1047 }; 1048 1049 state_dpaux2_i2c: pinmux-i2c { 1050 groups = "dpaux-io"; 1051 function = "i2c"; 1052 }; 1053 1054 state_dpaux2_off: pinmux-off { 1055 groups = "dpaux-io"; 1056 function = "off"; 1057 }; 1058 1059 i2c-bus { 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 }; 1063 }; 1064 1065 dpaux3: dpaux@155f0000 { 1066 compatible = "nvidia,tegra194-dpaux"; 1067 reg = <0x155f0000 0x10000>; 1068 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 1070 <&bpmp TEGRA194_CLK_PLLDP>; 1071 clock-names = "dpaux", "parent"; 1072 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 1073 reset-names = "dpaux"; 1074 status = "disabled"; 1075 1076 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1077 1078 state_dpaux3_aux: pinmux-aux { 1079 groups = "dpaux-io"; 1080 function = "aux"; 1081 }; 1082 1083 state_dpaux3_i2c: pinmux-i2c { 1084 groups = "dpaux-io"; 1085 function = "i2c"; 1086 }; 1087 1088 state_dpaux3_off: pinmux-off { 1089 groups = "dpaux-io"; 1090 function = "off"; 1091 }; 1092 1093 i2c-bus { 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 }; 1097 }; 1098 1099 sor0: sor@15b00000 { 1100 compatible = "nvidia,tegra194-sor"; 1101 reg = <0x15b00000 0x40000>; 1102 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 1104 <&bpmp TEGRA194_CLK_SOR0_OUT>, 1105 <&bpmp TEGRA194_CLK_PLLD>, 1106 <&bpmp TEGRA194_CLK_PLLDP>, 1107 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1108 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 1109 clock-names = "sor", "out", "parent", "dp", "safe", 1110 "pad"; 1111 resets = <&bpmp TEGRA194_RESET_SOR0>; 1112 reset-names = "sor"; 1113 pinctrl-0 = <&state_dpaux0_aux>; 1114 pinctrl-1 = <&state_dpaux0_i2c>; 1115 pinctrl-2 = <&state_dpaux0_off>; 1116 pinctrl-names = "aux", "i2c", "off"; 1117 status = "disabled"; 1118 1119 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1120 nvidia,interface = <0>; 1121 }; 1122 1123 sor1: sor@15b40000 { 1124 compatible = "nvidia,tegra194-sor"; 1125 reg = <0x15b40000 0x40000>; 1126 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 1128 <&bpmp TEGRA194_CLK_SOR1_OUT>, 1129 <&bpmp TEGRA194_CLK_PLLD2>, 1130 <&bpmp TEGRA194_CLK_PLLDP>, 1131 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1132 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 1133 clock-names = "sor", "out", "parent", "dp", "safe", 1134 "pad"; 1135 resets = <&bpmp TEGRA194_RESET_SOR1>; 1136 reset-names = "sor"; 1137 pinctrl-0 = <&state_dpaux1_aux>; 1138 pinctrl-1 = <&state_dpaux1_i2c>; 1139 pinctrl-2 = <&state_dpaux1_off>; 1140 pinctrl-names = "aux", "i2c", "off"; 1141 status = "disabled"; 1142 1143 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1144 nvidia,interface = <1>; 1145 }; 1146 1147 sor2: sor@15b80000 { 1148 compatible = "nvidia,tegra194-sor"; 1149 reg = <0x15b80000 0x40000>; 1150 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 1152 <&bpmp TEGRA194_CLK_SOR2_OUT>, 1153 <&bpmp TEGRA194_CLK_PLLD3>, 1154 <&bpmp TEGRA194_CLK_PLLDP>, 1155 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1156 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 1157 clock-names = "sor", "out", "parent", "dp", "safe", 1158 "pad"; 1159 resets = <&bpmp TEGRA194_RESET_SOR2>; 1160 reset-names = "sor"; 1161 pinctrl-0 = <&state_dpaux2_aux>; 1162 pinctrl-1 = <&state_dpaux2_i2c>; 1163 pinctrl-2 = <&state_dpaux2_off>; 1164 pinctrl-names = "aux", "i2c", "off"; 1165 status = "disabled"; 1166 1167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1168 nvidia,interface = <2>; 1169 }; 1170 1171 sor3: sor@15bc0000 { 1172 compatible = "nvidia,tegra194-sor"; 1173 reg = <0x15bc0000 0x40000>; 1174 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 1176 <&bpmp TEGRA194_CLK_SOR3_OUT>, 1177 <&bpmp TEGRA194_CLK_PLLD4>, 1178 <&bpmp TEGRA194_CLK_PLLDP>, 1179 <&bpmp TEGRA194_CLK_SOR_SAFE>, 1180 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 1181 clock-names = "sor", "out", "parent", "dp", "safe", 1182 "pad"; 1183 resets = <&bpmp TEGRA194_RESET_SOR3>; 1184 reset-names = "sor"; 1185 pinctrl-0 = <&state_dpaux3_aux>; 1186 pinctrl-1 = <&state_dpaux3_i2c>; 1187 pinctrl-2 = <&state_dpaux3_off>; 1188 pinctrl-names = "aux", "i2c", "off"; 1189 status = "disabled"; 1190 1191 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1192 nvidia,interface = <3>; 1193 }; 1194 }; 1195 }; 1196 1197 pcie@14100000 { 1198 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1199 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1200 reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */ 1201 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */ 1202 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1203 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1204 reg-names = "appl", "config", "atu_dma", "dbi"; 1205 1206 status = "disabled"; 1207 1208 #address-cells = <3>; 1209 #size-cells = <2>; 1210 device_type = "pci"; 1211 num-lanes = <1>; 1212 num-viewport = <8>; 1213 linux,pci-domain = <1>; 1214 1215 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 1216 clock-names = "core"; 1217 1218 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 1219 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 1220 reset-names = "apb", "core"; 1221 1222 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1223 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1224 interrupt-names = "intr", "msi"; 1225 1226 #interrupt-cells = <1>; 1227 interrupt-map-mask = <0 0 0 0>; 1228 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1229 1230 nvidia,bpmp = <&bpmp 1>; 1231 1232 nvidia,aspm-cmrt-us = <60>; 1233 nvidia,aspm-pwr-on-t-us = <20>; 1234 nvidia,aspm-l0s-entrance-latency-us = <3>; 1235 1236 bus-range = <0x0 0xff>; 1237 ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1238 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1239 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1240 }; 1241 1242 pcie@14120000 { 1243 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1244 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1245 reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */ 1246 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */ 1247 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1248 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1249 reg-names = "appl", "config", "atu_dma", "dbi"; 1250 1251 status = "disabled"; 1252 1253 #address-cells = <3>; 1254 #size-cells = <2>; 1255 device_type = "pci"; 1256 num-lanes = <1>; 1257 num-viewport = <8>; 1258 linux,pci-domain = <2>; 1259 1260 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 1261 clock-names = "core"; 1262 1263 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 1264 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 1265 reset-names = "apb", "core"; 1266 1267 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1268 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1269 interrupt-names = "intr", "msi"; 1270 1271 #interrupt-cells = <1>; 1272 interrupt-map-mask = <0 0 0 0>; 1273 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1274 1275 nvidia,bpmp = <&bpmp 2>; 1276 1277 nvidia,aspm-cmrt-us = <60>; 1278 nvidia,aspm-pwr-on-t-us = <20>; 1279 nvidia,aspm-l0s-entrance-latency-us = <3>; 1280 1281 bus-range = <0x0 0xff>; 1282 ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1283 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1284 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1285 }; 1286 1287 pcie@14140000 { 1288 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1289 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 1290 reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */ 1291 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */ 1292 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1293 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1294 reg-names = "appl", "config", "atu_dma", "dbi"; 1295 1296 status = "disabled"; 1297 1298 #address-cells = <3>; 1299 #size-cells = <2>; 1300 device_type = "pci"; 1301 num-lanes = <1>; 1302 num-viewport = <8>; 1303 linux,pci-domain = <3>; 1304 1305 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 1306 clock-names = "core"; 1307 1308 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 1309 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 1310 reset-names = "apb", "core"; 1311 1312 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1313 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1314 interrupt-names = "intr", "msi"; 1315 1316 #interrupt-cells = <1>; 1317 interrupt-map-mask = <0 0 0 0>; 1318 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1319 1320 nvidia,bpmp = <&bpmp 3>; 1321 1322 nvidia,aspm-cmrt-us = <60>; 1323 nvidia,aspm-pwr-on-t-us = <20>; 1324 nvidia,aspm-l0s-entrance-latency-us = <3>; 1325 1326 bus-range = <0x0 0xff>; 1327 ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1328 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 1329 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ 1330 }; 1331 1332 pcie@14160000 { 1333 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1334 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 1335 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 1336 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */ 1337 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1338 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1339 reg-names = "appl", "config", "atu_dma", "dbi"; 1340 1341 status = "disabled"; 1342 1343 #address-cells = <3>; 1344 #size-cells = <2>; 1345 device_type = "pci"; 1346 num-lanes = <4>; 1347 num-viewport = <8>; 1348 linux,pci-domain = <4>; 1349 1350 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 1351 clock-names = "core"; 1352 1353 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 1354 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 1355 reset-names = "apb", "core"; 1356 1357 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1358 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1359 interrupt-names = "intr", "msi"; 1360 1361 #interrupt-cells = <1>; 1362 interrupt-map-mask = <0 0 0 0>; 1363 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1364 1365 nvidia,bpmp = <&bpmp 4>; 1366 1367 nvidia,aspm-cmrt-us = <60>; 1368 nvidia,aspm-pwr-on-t-us = <20>; 1369 nvidia,aspm-l0s-entrance-latency-us = <3>; 1370 1371 bus-range = <0x0 0xff>; 1372 ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1373 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1374 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1375 }; 1376 1377 pcie@14180000 { 1378 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1379 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 1380 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 1381 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 1382 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1383 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1384 reg-names = "appl", "config", "atu_dma", "dbi"; 1385 1386 status = "disabled"; 1387 1388 #address-cells = <3>; 1389 #size-cells = <2>; 1390 device_type = "pci"; 1391 num-lanes = <8>; 1392 num-viewport = <8>; 1393 linux,pci-domain = <0>; 1394 1395 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 1396 clock-names = "core"; 1397 1398 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 1399 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 1400 reset-names = "apb", "core"; 1401 1402 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1403 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1404 interrupt-names = "intr", "msi"; 1405 1406 #interrupt-cells = <1>; 1407 interrupt-map-mask = <0 0 0 0>; 1408 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1409 1410 nvidia,bpmp = <&bpmp 0>; 1411 1412 nvidia,aspm-cmrt-us = <60>; 1413 nvidia,aspm-pwr-on-t-us = <20>; 1414 nvidia,aspm-l0s-entrance-latency-us = <3>; 1415 1416 bus-range = <0x0 0xff>; 1417 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1418 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1419 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1420 }; 1421 1422 pcie@141a0000 { 1423 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie"; 1424 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 1425 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 1426 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ 1427 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 1428 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 1429 reg-names = "appl", "config", "atu_dma", "dbi"; 1430 1431 status = "disabled"; 1432 1433 #address-cells = <3>; 1434 #size-cells = <2>; 1435 device_type = "pci"; 1436 num-lanes = <8>; 1437 num-viewport = <8>; 1438 linux,pci-domain = <5>; 1439 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 1442 1443 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>, 1444 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>; 1445 clock-names = "core", "core_m"; 1446 1447 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 1448 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 1449 reset-names = "apb", "core"; 1450 1451 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 1452 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 1453 interrupt-names = "intr", "msi"; 1454 1455 nvidia,bpmp = <&bpmp 5>; 1456 1457 #interrupt-cells = <1>; 1458 interrupt-map-mask = <0 0 0 0>; 1459 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1460 1461 nvidia,aspm-cmrt-us = <60>; 1462 nvidia,aspm-pwr-on-t-us = <20>; 1463 nvidia,aspm-l0s-entrance-latency-us = <3>; 1464 1465 bus-range = <0x0 0xff>; 1466 ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ 1467 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 1468 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ 1469 }; 1470 1471 sysram@40000000 { 1472 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 1473 reg = <0x0 0x40000000 0x0 0x50000>; 1474 #address-cells = <1>; 1475 #size-cells = <1>; 1476 ranges = <0x0 0x0 0x40000000 0x50000>; 1477 1478 cpu_bpmp_tx: shmem@4e000 { 1479 compatible = "nvidia,tegra194-bpmp-shmem"; 1480 reg = <0x4e000 0x1000>; 1481 label = "cpu-bpmp-tx"; 1482 pool; 1483 }; 1484 1485 cpu_bpmp_rx: shmem@4f000 { 1486 compatible = "nvidia,tegra194-bpmp-shmem"; 1487 reg = <0x4f000 0x1000>; 1488 label = "cpu-bpmp-rx"; 1489 pool; 1490 }; 1491 }; 1492 1493 bpmp: bpmp { 1494 compatible = "nvidia,tegra186-bpmp"; 1495 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1496 TEGRA_HSP_DB_MASTER_BPMP>; 1497 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 1498 #clock-cells = <1>; 1499 #reset-cells = <1>; 1500 #power-domain-cells = <1>; 1501 1502 bpmp_i2c: i2c { 1503 compatible = "nvidia,tegra186-bpmp-i2c"; 1504 nvidia,bpmp-bus-id = <5>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 }; 1508 1509 bpmp_thermal: thermal { 1510 compatible = "nvidia,tegra186-bpmp-thermal"; 1511 #thermal-sensor-cells = <1>; 1512 }; 1513 }; 1514 1515 cpus { 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 1519 cpu0_0: cpu@0 { 1520 compatible = "nvidia,tegra194-carmel"; 1521 device_type = "cpu"; 1522 reg = <0x000>; 1523 enable-method = "psci"; 1524 i-cache-size = <131072>; 1525 i-cache-line-size = <64>; 1526 i-cache-sets = <512>; 1527 d-cache-size = <65536>; 1528 d-cache-line-size = <64>; 1529 d-cache-sets = <256>; 1530 next-level-cache = <&l2c_0>; 1531 }; 1532 1533 cpu0_1: cpu@1 { 1534 compatible = "nvidia,tegra194-carmel"; 1535 device_type = "cpu"; 1536 reg = <0x001>; 1537 enable-method = "psci"; 1538 i-cache-size = <131072>; 1539 i-cache-line-size = <64>; 1540 i-cache-sets = <512>; 1541 d-cache-size = <65536>; 1542 d-cache-line-size = <64>; 1543 d-cache-sets = <256>; 1544 next-level-cache = <&l2c_0>; 1545 }; 1546 1547 cpu1_0: cpu@100 { 1548 compatible = "nvidia,tegra194-carmel"; 1549 device_type = "cpu"; 1550 reg = <0x100>; 1551 enable-method = "psci"; 1552 i-cache-size = <131072>; 1553 i-cache-line-size = <64>; 1554 i-cache-sets = <512>; 1555 d-cache-size = <65536>; 1556 d-cache-line-size = <64>; 1557 d-cache-sets = <256>; 1558 next-level-cache = <&l2c_1>; 1559 }; 1560 1561 cpu1_1: cpu@101 { 1562 compatible = "nvidia,tegra194-carmel"; 1563 device_type = "cpu"; 1564 reg = <0x101>; 1565 enable-method = "psci"; 1566 i-cache-size = <131072>; 1567 i-cache-line-size = <64>; 1568 i-cache-sets = <512>; 1569 d-cache-size = <65536>; 1570 d-cache-line-size = <64>; 1571 d-cache-sets = <256>; 1572 next-level-cache = <&l2c_1>; 1573 }; 1574 1575 cpu2_0: cpu@200 { 1576 compatible = "nvidia,tegra194-carmel"; 1577 device_type = "cpu"; 1578 reg = <0x200>; 1579 enable-method = "psci"; 1580 i-cache-size = <131072>; 1581 i-cache-line-size = <64>; 1582 i-cache-sets = <512>; 1583 d-cache-size = <65536>; 1584 d-cache-line-size = <64>; 1585 d-cache-sets = <256>; 1586 next-level-cache = <&l2c_2>; 1587 }; 1588 1589 cpu2_1: cpu@201 { 1590 compatible = "nvidia,tegra194-carmel"; 1591 device_type = "cpu"; 1592 reg = <0x201>; 1593 enable-method = "psci"; 1594 i-cache-size = <131072>; 1595 i-cache-line-size = <64>; 1596 i-cache-sets = <512>; 1597 d-cache-size = <65536>; 1598 d-cache-line-size = <64>; 1599 d-cache-sets = <256>; 1600 next-level-cache = <&l2c_2>; 1601 }; 1602 1603 cpu3_0: cpu@300 { 1604 compatible = "nvidia,tegra194-carmel"; 1605 device_type = "cpu"; 1606 reg = <0x300>; 1607 enable-method = "psci"; 1608 i-cache-size = <131072>; 1609 i-cache-line-size = <64>; 1610 i-cache-sets = <512>; 1611 d-cache-size = <65536>; 1612 d-cache-line-size = <64>; 1613 d-cache-sets = <256>; 1614 next-level-cache = <&l2c_3>; 1615 }; 1616 1617 cpu3_1: cpu@301 { 1618 compatible = "nvidia,tegra194-carmel"; 1619 device_type = "cpu"; 1620 reg = <0x301>; 1621 enable-method = "psci"; 1622 i-cache-size = <131072>; 1623 i-cache-line-size = <64>; 1624 i-cache-sets = <512>; 1625 d-cache-size = <65536>; 1626 d-cache-line-size = <64>; 1627 d-cache-sets = <256>; 1628 next-level-cache = <&l2c_3>; 1629 }; 1630 1631 cpu-map { 1632 cluster0 { 1633 core0 { 1634 cpu = <&cpu0_0>; 1635 }; 1636 1637 core1 { 1638 cpu = <&cpu0_1>; 1639 }; 1640 }; 1641 1642 cluster1 { 1643 core0 { 1644 cpu = <&cpu1_0>; 1645 }; 1646 1647 core1 { 1648 cpu = <&cpu1_1>; 1649 }; 1650 }; 1651 1652 cluster2 { 1653 core0 { 1654 cpu = <&cpu2_0>; 1655 }; 1656 1657 core1 { 1658 cpu = <&cpu2_1>; 1659 }; 1660 }; 1661 1662 cluster3 { 1663 core0 { 1664 cpu = <&cpu3_0>; 1665 }; 1666 1667 core1 { 1668 cpu = <&cpu3_1>; 1669 }; 1670 }; 1671 }; 1672 1673 l2c_0: l2-cache0 { 1674 cache-size = <2097152>; 1675 cache-line-size = <64>; 1676 cache-sets = <2048>; 1677 next-level-cache = <&l3c>; 1678 }; 1679 1680 l2c_1: l2-cache1 { 1681 cache-size = <2097152>; 1682 cache-line-size = <64>; 1683 cache-sets = <2048>; 1684 next-level-cache = <&l3c>; 1685 }; 1686 1687 l2c_2: l2-cache2 { 1688 cache-size = <2097152>; 1689 cache-line-size = <64>; 1690 cache-sets = <2048>; 1691 next-level-cache = <&l3c>; 1692 }; 1693 1694 l2c_3: l2-cache3 { 1695 cache-size = <2097152>; 1696 cache-line-size = <64>; 1697 cache-sets = <2048>; 1698 next-level-cache = <&l3c>; 1699 }; 1700 1701 l3c: l3-cache { 1702 cache-size = <4194304>; 1703 cache-line-size = <64>; 1704 cache-sets = <4096>; 1705 }; 1706 }; 1707 1708 psci { 1709 compatible = "arm,psci-1.0"; 1710 status = "okay"; 1711 method = "smc"; 1712 }; 1713 1714 tcu: tcu { 1715 compatible = "nvidia,tegra194-tcu"; 1716 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1717 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1718 mbox-names = "rx", "tx"; 1719 }; 1720 1721 thermal-zones { 1722 cpu { 1723 thermal-sensors = <&{/bpmp/thermal} 1724 TEGRA194_BPMP_THERMAL_ZONE_CPU>; 1725 status = "disabled"; 1726 }; 1727 1728 gpu { 1729 thermal-sensors = <&{/bpmp/thermal} 1730 TEGRA194_BPMP_THERMAL_ZONE_GPU>; 1731 status = "disabled"; 1732 }; 1733 1734 aux { 1735 thermal-sensors = <&{/bpmp/thermal} 1736 TEGRA194_BPMP_THERMAL_ZONE_AUX>; 1737 status = "disabled"; 1738 }; 1739 1740 pllx { 1741 thermal-sensors = <&{/bpmp/thermal} 1742 TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 1743 status = "disabled"; 1744 }; 1745 1746 ao { 1747 thermal-sensors = <&{/bpmp/thermal} 1748 TEGRA194_BPMP_THERMAL_ZONE_AO>; 1749 status = "disabled"; 1750 }; 1751 1752 tj { 1753 thermal-sensors = <&{/bpmp/thermal} 1754 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 1755 status = "disabled"; 1756 }; 1757 }; 1758 1759 timer { 1760 compatible = "arm,armv8-timer"; 1761 interrupts = <GIC_PPI 13 1762 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1763 <GIC_PPI 14 1764 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1765 <GIC_PPI 11 1766 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1767 <GIC_PPI 10 1768 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1769 interrupt-parent = <&gic>; 1770 always-on; 1771 }; 1772}; 1773