1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra194-clock.h>
3#include <dt-bindings/gpio/tegra194-gpio.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/mailbox/tegra186-hsp.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra.h>
7#include <dt-bindings/power/tegra194-powergate.h>
8#include <dt-bindings/reset/tegra194-reset.h>
9#include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10#include <dt-bindings/memory/tegra194-mc.h>
11
12/ {
13	compatible = "nvidia,tegra194";
14	interrupt-parent = <&gic>;
15	#address-cells = <2>;
16	#size-cells = <2>;
17
18	/* control backbone */
19	cbb@0 {
20		compatible = "simple-bus";
21		#address-cells = <1>;
22		#size-cells = <1>;
23		ranges = <0x0 0x0 0x0 0x40000000>;
24
25		misc@100000 {
26			compatible = "nvidia,tegra194-misc";
27			reg = <0x00100000 0xf000>,
28			      <0x0010f000 0x1000>;
29		};
30
31		gpio: gpio@2200000 {
32			compatible = "nvidia,tegra194-gpio";
33			reg-names = "security", "gpio";
34			reg = <0x2200000 0x10000>,
35			      <0x2210000 0x10000>;
36			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
37				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
38				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
39				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
40				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
41				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
42			#interrupt-cells = <2>;
43			interrupt-controller;
44			#gpio-cells = <2>;
45			gpio-controller;
46		};
47
48		ethernet@2490000 {
49			compatible = "nvidia,tegra194-eqos",
50				     "nvidia,tegra186-eqos",
51				     "snps,dwc-qos-ethernet-4.10";
52			reg = <0x02490000 0x10000>;
53			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
54			clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
55				 <&bpmp TEGRA194_CLK_EQOS_AXI>,
56				 <&bpmp TEGRA194_CLK_EQOS_RX>,
57				 <&bpmp TEGRA194_CLK_EQOS_TX>,
58				 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
59			clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
60			resets = <&bpmp TEGRA194_RESET_EQOS>;
61			reset-names = "eqos";
62			status = "disabled";
63
64			snps,write-requests = <1>;
65			snps,read-requests = <3>;
66			snps,burst-map = <0x7>;
67			snps,txpbl = <16>;
68			snps,rxpbl = <8>;
69		};
70
71		aconnect@2900000 {
72			compatible = "nvidia,tegra194-aconnect",
73				     "nvidia,tegra210-aconnect";
74			clocks = <&bpmp TEGRA194_CLK_APE>,
75				 <&bpmp TEGRA194_CLK_APB2APE>;
76			clock-names = "ape", "apb2ape";
77			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
78			#address-cells = <1>;
79			#size-cells = <1>;
80			ranges = <0x02900000 0x02900000 0x200000>;
81			status = "disabled";
82
83			dma-controller@2930000 {
84				compatible = "nvidia,tegra194-adma",
85					     "nvidia,tegra186-adma";
86				reg = <0x02930000 0x20000>;
87				interrupt-parent = <&agic>;
88				interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
89					      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
90					      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91					      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
92					      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
93					      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
94					      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
95					      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
96					      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
97					      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
98					      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
99					      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
100					      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
101					      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
102					      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
103					      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
104					      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
105					      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
106					      <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
107					      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
108					      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
109					      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
110					      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
111					      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
112					      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
113					      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
114					      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
115					      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
116					      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
117					      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
118					      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
119					      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
120				#dma-cells = <1>;
121				clocks = <&bpmp TEGRA194_CLK_AHUB>;
122				clock-names = "d_audio";
123				status = "disabled";
124			};
125
126			agic: interrupt-controller@2a40000 {
127				compatible = "nvidia,tegra194-agic",
128					     "nvidia,tegra210-agic";
129				#interrupt-cells = <3>;
130				interrupt-controller;
131				reg = <0x02a41000 0x1000>,
132				      <0x02a42000 0x2000>;
133				interrupts = <GIC_SPI 145
134					      (GIC_CPU_MASK_SIMPLE(4) |
135					       IRQ_TYPE_LEVEL_HIGH)>;
136				clocks = <&bpmp TEGRA194_CLK_APE>;
137				clock-names = "clk";
138				status = "disabled";
139			};
140		};
141
142		pinmux: pinmux@2430000 {
143			compatible = "nvidia,tegra194-pinmux";
144			reg = <0x2430000 0x17000
145			       0xc300000 0x4000>;
146
147			status = "okay";
148
149			pex_rst_c5_out_state: pex_rst_c5_out {
150				pex_rst {
151					nvidia,pins = "pex_l5_rst_n_pgg1";
152					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
153					nvidia,lpdr = <TEGRA_PIN_ENABLE>;
154					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
155					nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
156					nvidia,tristate = <TEGRA_PIN_DISABLE>;
157					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158				};
159			};
160
161			clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
162				clkreq {
163					nvidia,pins = "pex_l5_clkreq_n_pgg0";
164					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
165					nvidia,lpdr = <TEGRA_PIN_ENABLE>;
166					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
167					nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
168					nvidia,tristate = <TEGRA_PIN_DISABLE>;
169					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
170				};
171			};
172		};
173
174		mc: memory-controller@2c00000 {
175			compatible = "nvidia,tegra194-mc";
176			reg = <0x02c00000 0x100000>,
177			      <0x02b80000 0x040000>,
178			      <0x01700000 0x100000>;
179			status = "disabled";
180
181			#address-cells = <2>;
182			#size-cells = <2>;
183
184			ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
185				 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
186				 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
187
188			/*
189			 * Bit 39 of addresses passing through the memory
190			 * controller selects the XBAR format used when memory
191			 * is accessed. This is used to transparently access
192			 * memory in the XBAR format used by the discrete GPU
193			 * (bit 39 set) or Tegra (bit 39 clear).
194			 *
195			 * As a consequence, the operating system must ensure
196			 * that bit 39 is never used implicitly, for example
197			 * via an I/O virtual address mapping of an IOMMU. If
198			 * devices require access to the XBAR switch, their
199			 * drivers must set this bit explicitly.
200			 *
201			 * Limit the DMA range for memory clients to [38:0].
202			 */
203			dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
204
205			emc: external-memory-controller@2c60000 {
206				compatible = "nvidia,tegra194-emc";
207				reg = <0x0 0x02c60000 0x0 0x90000>,
208				      <0x0 0x01780000 0x0 0x80000>;
209				clocks = <&bpmp TEGRA194_CLK_EMC>;
210				clock-names = "emc";
211
212				nvidia,bpmp = <&bpmp>;
213			};
214		};
215
216		uarta: serial@3100000 {
217			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
218			reg = <0x03100000 0x40>;
219			reg-shift = <2>;
220			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
221			clocks = <&bpmp TEGRA194_CLK_UARTA>;
222			clock-names = "serial";
223			resets = <&bpmp TEGRA194_RESET_UARTA>;
224			reset-names = "serial";
225			status = "disabled";
226		};
227
228		uartb: serial@3110000 {
229			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
230			reg = <0x03110000 0x40>;
231			reg-shift = <2>;
232			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
233			clocks = <&bpmp TEGRA194_CLK_UARTB>;
234			clock-names = "serial";
235			resets = <&bpmp TEGRA194_RESET_UARTB>;
236			reset-names = "serial";
237			status = "disabled";
238		};
239
240		uartd: serial@3130000 {
241			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
242			reg = <0x03130000 0x40>;
243			reg-shift = <2>;
244			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
245			clocks = <&bpmp TEGRA194_CLK_UARTD>;
246			clock-names = "serial";
247			resets = <&bpmp TEGRA194_RESET_UARTD>;
248			reset-names = "serial";
249			status = "disabled";
250		};
251
252		uarte: serial@3140000 {
253			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
254			reg = <0x03140000 0x40>;
255			reg-shift = <2>;
256			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
257			clocks = <&bpmp TEGRA194_CLK_UARTE>;
258			clock-names = "serial";
259			resets = <&bpmp TEGRA194_RESET_UARTE>;
260			reset-names = "serial";
261			status = "disabled";
262		};
263
264		uartf: serial@3150000 {
265			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
266			reg = <0x03150000 0x40>;
267			reg-shift = <2>;
268			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
269			clocks = <&bpmp TEGRA194_CLK_UARTF>;
270			clock-names = "serial";
271			resets = <&bpmp TEGRA194_RESET_UARTF>;
272			reset-names = "serial";
273			status = "disabled";
274		};
275
276		gen1_i2c: i2c@3160000 {
277			compatible = "nvidia,tegra194-i2c";
278			reg = <0x03160000 0x10000>;
279			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
280			#address-cells = <1>;
281			#size-cells = <0>;
282			clocks = <&bpmp TEGRA194_CLK_I2C1>;
283			clock-names = "div-clk";
284			resets = <&bpmp TEGRA194_RESET_I2C1>;
285			reset-names = "i2c";
286			status = "disabled";
287		};
288
289		uarth: serial@3170000 {
290			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
291			reg = <0x03170000 0x40>;
292			reg-shift = <2>;
293			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
294			clocks = <&bpmp TEGRA194_CLK_UARTH>;
295			clock-names = "serial";
296			resets = <&bpmp TEGRA194_RESET_UARTH>;
297			reset-names = "serial";
298			status = "disabled";
299		};
300
301		cam_i2c: i2c@3180000 {
302			compatible = "nvidia,tegra194-i2c";
303			reg = <0x03180000 0x10000>;
304			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
305			#address-cells = <1>;
306			#size-cells = <0>;
307			clocks = <&bpmp TEGRA194_CLK_I2C3>;
308			clock-names = "div-clk";
309			resets = <&bpmp TEGRA194_RESET_I2C3>;
310			reset-names = "i2c";
311			status = "disabled";
312		};
313
314		/* shares pads with dpaux1 */
315		dp_aux_ch1_i2c: i2c@3190000 {
316			compatible = "nvidia,tegra194-i2c";
317			reg = <0x03190000 0x10000>;
318			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
319			#address-cells = <1>;
320			#size-cells = <0>;
321			clocks = <&bpmp TEGRA194_CLK_I2C4>;
322			clock-names = "div-clk";
323			resets = <&bpmp TEGRA194_RESET_I2C4>;
324			reset-names = "i2c";
325			status = "disabled";
326		};
327
328		/* shares pads with dpaux0 */
329		dp_aux_ch0_i2c: i2c@31b0000 {
330			compatible = "nvidia,tegra194-i2c";
331			reg = <0x031b0000 0x10000>;
332			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
333			#address-cells = <1>;
334			#size-cells = <0>;
335			clocks = <&bpmp TEGRA194_CLK_I2C6>;
336			clock-names = "div-clk";
337			resets = <&bpmp TEGRA194_RESET_I2C6>;
338			reset-names = "i2c";
339			status = "disabled";
340		};
341
342		gen7_i2c: i2c@31c0000 {
343			compatible = "nvidia,tegra194-i2c";
344			reg = <0x031c0000 0x10000>;
345			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
346			#address-cells = <1>;
347			#size-cells = <0>;
348			clocks = <&bpmp TEGRA194_CLK_I2C7>;
349			clock-names = "div-clk";
350			resets = <&bpmp TEGRA194_RESET_I2C7>;
351			reset-names = "i2c";
352			status = "disabled";
353		};
354
355		gen9_i2c: i2c@31e0000 {
356			compatible = "nvidia,tegra194-i2c";
357			reg = <0x031e0000 0x10000>;
358			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
359			#address-cells = <1>;
360			#size-cells = <0>;
361			clocks = <&bpmp TEGRA194_CLK_I2C9>;
362			clock-names = "div-clk";
363			resets = <&bpmp TEGRA194_RESET_I2C9>;
364			reset-names = "i2c";
365			status = "disabled";
366		};
367
368		pwm1: pwm@3280000 {
369			compatible = "nvidia,tegra194-pwm",
370				     "nvidia,tegra186-pwm";
371			reg = <0x3280000 0x10000>;
372			clocks = <&bpmp TEGRA194_CLK_PWM1>;
373			clock-names = "pwm";
374			resets = <&bpmp TEGRA194_RESET_PWM1>;
375			reset-names = "pwm";
376			status = "disabled";
377			#pwm-cells = <2>;
378		};
379
380		pwm2: pwm@3290000 {
381			compatible = "nvidia,tegra194-pwm",
382				     "nvidia,tegra186-pwm";
383			reg = <0x3290000 0x10000>;
384			clocks = <&bpmp TEGRA194_CLK_PWM2>;
385			clock-names = "pwm";
386			resets = <&bpmp TEGRA194_RESET_PWM2>;
387			reset-names = "pwm";
388			status = "disabled";
389			#pwm-cells = <2>;
390		};
391
392		pwm3: pwm@32a0000 {
393			compatible = "nvidia,tegra194-pwm",
394				     "nvidia,tegra186-pwm";
395			reg = <0x32a0000 0x10000>;
396			clocks = <&bpmp TEGRA194_CLK_PWM3>;
397			clock-names = "pwm";
398			resets = <&bpmp TEGRA194_RESET_PWM3>;
399			reset-names = "pwm";
400			status = "disabled";
401			#pwm-cells = <2>;
402		};
403
404		pwm5: pwm@32c0000 {
405			compatible = "nvidia,tegra194-pwm",
406				     "nvidia,tegra186-pwm";
407			reg = <0x32c0000 0x10000>;
408			clocks = <&bpmp TEGRA194_CLK_PWM5>;
409			clock-names = "pwm";
410			resets = <&bpmp TEGRA194_RESET_PWM5>;
411			reset-names = "pwm";
412			status = "disabled";
413			#pwm-cells = <2>;
414		};
415
416		pwm6: pwm@32d0000 {
417			compatible = "nvidia,tegra194-pwm",
418				     "nvidia,tegra186-pwm";
419			reg = <0x32d0000 0x10000>;
420			clocks = <&bpmp TEGRA194_CLK_PWM6>;
421			clock-names = "pwm";
422			resets = <&bpmp TEGRA194_RESET_PWM6>;
423			reset-names = "pwm";
424			status = "disabled";
425			#pwm-cells = <2>;
426		};
427
428		pwm7: pwm@32e0000 {
429			compatible = "nvidia,tegra194-pwm",
430				     "nvidia,tegra186-pwm";
431			reg = <0x32e0000 0x10000>;
432			clocks = <&bpmp TEGRA194_CLK_PWM7>;
433			clock-names = "pwm";
434			resets = <&bpmp TEGRA194_RESET_PWM7>;
435			reset-names = "pwm";
436			status = "disabled";
437			#pwm-cells = <2>;
438		};
439
440		pwm8: pwm@32f0000 {
441			compatible = "nvidia,tegra194-pwm",
442				     "nvidia,tegra186-pwm";
443			reg = <0x32f0000 0x10000>;
444			clocks = <&bpmp TEGRA194_CLK_PWM8>;
445			clock-names = "pwm";
446			resets = <&bpmp TEGRA194_RESET_PWM8>;
447			reset-names = "pwm";
448			status = "disabled";
449			#pwm-cells = <2>;
450		};
451
452		sdmmc1: sdhci@3400000 {
453			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
454			reg = <0x03400000 0x10000>;
455			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
456			clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
457			clock-names = "sdhci";
458			resets = <&bpmp TEGRA194_RESET_SDMMC1>;
459			reset-names = "sdhci";
460			nvidia,pad-autocal-pull-up-offset-3v3-timeout =
461									<0x07>;
462			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
463									<0x07>;
464			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
465			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
466									<0x07>;
467			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
468			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
469			nvidia,default-tap = <0x9>;
470			nvidia,default-trim = <0x5>;
471			status = "disabled";
472		};
473
474		sdmmc3: sdhci@3440000 {
475			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
476			reg = <0x03440000 0x10000>;
477			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
478			clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
479			clock-names = "sdhci";
480			resets = <&bpmp TEGRA194_RESET_SDMMC3>;
481			reset-names = "sdhci";
482			nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
483			nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
484			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
485			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
486									<0x07>;
487			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
488			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
489									<0x07>;
490			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
491			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
492			nvidia,default-tap = <0x9>;
493			nvidia,default-trim = <0x5>;
494			status = "disabled";
495		};
496
497		sdmmc4: sdhci@3460000 {
498			compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
499			reg = <0x03460000 0x10000>;
500			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
501			clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
502			clock-names = "sdhci";
503			assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
504					  <&bpmp TEGRA194_CLK_PLLC4>;
505			assigned-clock-parents =
506					  <&bpmp TEGRA194_CLK_PLLC4>;
507			resets = <&bpmp TEGRA194_RESET_SDMMC4>;
508			reset-names = "sdhci";
509			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
510			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
511			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
512			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
513									<0x0a>;
514			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
515			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
516									<0x0a>;
517			nvidia,default-tap = <0x8>;
518			nvidia,default-trim = <0x14>;
519			nvidia,dqs-trim = <40>;
520			supports-cqe;
521			status = "disabled";
522		};
523
524		hda@3510000 {
525			compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
526			reg = <0x3510000 0x10000>;
527			interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
528			clocks = <&bpmp TEGRA194_CLK_HDA>,
529				 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
530				 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
531			clock-names = "hda", "hda2codec_2x", "hda2hdmi";
532			resets = <&bpmp TEGRA194_RESET_HDA>,
533				 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
534				 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
535			reset-names = "hda", "hda2codec_2x", "hda2hdmi";
536			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
537			status = "disabled";
538		};
539
540		xusb_padctl: padctl@3520000 {
541			compatible = "nvidia,tegra194-xusb-padctl";
542			reg = <0x03520000 0x1000>,
543			      <0x03540000 0x1000>;
544			reg-names = "padctl", "ao";
545
546			resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
547			reset-names = "padctl";
548
549			status = "disabled";
550
551			pads {
552				usb2 {
553					clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
554					clock-names = "trk";
555
556					lanes {
557						usb2-0 {
558							nvidia,function = "xusb";
559							status = "disabled";
560							#phy-cells = <0>;
561						};
562
563						usb2-1 {
564							nvidia,function = "xusb";
565							status = "disabled";
566							#phy-cells = <0>;
567						};
568
569						usb2-2 {
570							nvidia,function = "xusb";
571							status = "disabled";
572							#phy-cells = <0>;
573						};
574
575						usb2-3 {
576							nvidia,function = "xusb";
577							status = "disabled";
578							#phy-cells = <0>;
579						};
580					};
581				};
582
583				usb3 {
584					lanes {
585						usb3-0 {
586							nvidia,function = "xusb";
587							status = "disabled";
588							#phy-cells = <0>;
589						};
590
591						usb3-1 {
592							nvidia,function = "xusb";
593							status = "disabled";
594							#phy-cells = <0>;
595						};
596
597						usb3-2 {
598							nvidia,function = "xusb";
599							status = "disabled";
600							#phy-cells = <0>;
601						};
602
603						usb3-3 {
604							nvidia,function = "xusb";
605							status = "disabled";
606							#phy-cells = <0>;
607						};
608					};
609				};
610			};
611
612			ports {
613				usb2-0 {
614					status = "disabled";
615				};
616
617				usb2-1 {
618					status = "disabled";
619				};
620
621				usb2-2 {
622					status = "disabled";
623				};
624
625				usb2-3 {
626					status = "disabled";
627				};
628
629				usb3-0 {
630					status = "disabled";
631				};
632
633				usb3-1 {
634					status = "disabled";
635				};
636
637				usb3-2 {
638					status = "disabled";
639				};
640
641				usb3-3 {
642					status = "disabled";
643				};
644			};
645		};
646
647		usb@3610000 {
648			compatible = "nvidia,tegra194-xusb";
649			reg = <0x03610000 0x40000>,
650			      <0x03600000 0x10000>;
651			reg-names = "hcd", "fpci";
652
653			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
654				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
655				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
656
657			clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
658				 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
659				 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
660				 <&bpmp TEGRA194_CLK_XUSB_SS>,
661				 <&bpmp TEGRA194_CLK_CLK_M>,
662				 <&bpmp TEGRA194_CLK_XUSB_FS>,
663				 <&bpmp TEGRA194_CLK_UTMIPLL>,
664				 <&bpmp TEGRA194_CLK_CLK_M>,
665				 <&bpmp TEGRA194_CLK_PLLE>;
666			clock-names = "xusb_host", "xusb_falcon_src",
667				      "xusb_ss", "xusb_ss_src", "xusb_hs_src",
668				      "xusb_fs_src", "pll_u_480m", "clk_m",
669				      "pll_e";
670
671			power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
672					<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
673			power-domain-names = "xusb_host", "xusb_ss";
674
675			nvidia,xusb-padctl = <&xusb_padctl>;
676			status = "disabled";
677		};
678
679		fuse@3820000 {
680			compatible = "nvidia,tegra194-efuse";
681			reg = <0x03820000 0x10000>;
682			clocks = <&bpmp TEGRA194_CLK_FUSE>;
683			clock-names = "fuse";
684		};
685
686		gic: interrupt-controller@3881000 {
687			compatible = "arm,gic-400";
688			#interrupt-cells = <3>;
689			interrupt-controller;
690			reg = <0x03881000 0x1000>,
691			      <0x03882000 0x2000>,
692			      <0x03884000 0x2000>,
693			      <0x03886000 0x2000>;
694			interrupts = <GIC_PPI 9
695				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
696			interrupt-parent = <&gic>;
697		};
698
699		cec@3960000 {
700			compatible = "nvidia,tegra194-cec";
701			reg = <0x03960000 0x10000>;
702			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
703			clocks = <&bpmp TEGRA194_CLK_CEC>;
704			clock-names = "cec";
705			status = "disabled";
706		};
707
708		hsp_top0: hsp@3c00000 {
709			compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
710			reg = <0x03c00000 0xa0000>;
711			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
712			             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
713			             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
714			             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
715			             <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
716			             <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
717			             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
718			             <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
719			             <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
720			interrupt-names = "doorbell", "shared0", "shared1", "shared2",
721			                  "shared3", "shared4", "shared5", "shared6",
722			                  "shared7";
723			#mbox-cells = <2>;
724		};
725
726		p2u_hsio_0: phy@3e10000 {
727			compatible = "nvidia,tegra194-p2u";
728			reg = <0x03e10000 0x10000>;
729			reg-names = "ctl";
730
731			#phy-cells = <0>;
732		};
733
734		p2u_hsio_1: phy@3e20000 {
735			compatible = "nvidia,tegra194-p2u";
736			reg = <0x03e20000 0x10000>;
737			reg-names = "ctl";
738
739			#phy-cells = <0>;
740		};
741
742		p2u_hsio_2: phy@3e30000 {
743			compatible = "nvidia,tegra194-p2u";
744			reg = <0x03e30000 0x10000>;
745			reg-names = "ctl";
746
747			#phy-cells = <0>;
748		};
749
750		p2u_hsio_3: phy@3e40000 {
751			compatible = "nvidia,tegra194-p2u";
752			reg = <0x03e40000 0x10000>;
753			reg-names = "ctl";
754
755			#phy-cells = <0>;
756		};
757
758		p2u_hsio_4: phy@3e50000 {
759			compatible = "nvidia,tegra194-p2u";
760			reg = <0x03e50000 0x10000>;
761			reg-names = "ctl";
762
763			#phy-cells = <0>;
764		};
765
766		p2u_hsio_5: phy@3e60000 {
767			compatible = "nvidia,tegra194-p2u";
768			reg = <0x03e60000 0x10000>;
769			reg-names = "ctl";
770
771			#phy-cells = <0>;
772		};
773
774		p2u_hsio_6: phy@3e70000 {
775			compatible = "nvidia,tegra194-p2u";
776			reg = <0x03e70000 0x10000>;
777			reg-names = "ctl";
778
779			#phy-cells = <0>;
780		};
781
782		p2u_hsio_7: phy@3e80000 {
783			compatible = "nvidia,tegra194-p2u";
784			reg = <0x03e80000 0x10000>;
785			reg-names = "ctl";
786
787			#phy-cells = <0>;
788		};
789
790		p2u_hsio_8: phy@3e90000 {
791			compatible = "nvidia,tegra194-p2u";
792			reg = <0x03e90000 0x10000>;
793			reg-names = "ctl";
794
795			#phy-cells = <0>;
796		};
797
798		p2u_hsio_9: phy@3ea0000 {
799			compatible = "nvidia,tegra194-p2u";
800			reg = <0x03ea0000 0x10000>;
801			reg-names = "ctl";
802
803			#phy-cells = <0>;
804		};
805
806		p2u_nvhs_0: phy@3eb0000 {
807			compatible = "nvidia,tegra194-p2u";
808			reg = <0x03eb0000 0x10000>;
809			reg-names = "ctl";
810
811			#phy-cells = <0>;
812		};
813
814		p2u_nvhs_1: phy@3ec0000 {
815			compatible = "nvidia,tegra194-p2u";
816			reg = <0x03ec0000 0x10000>;
817			reg-names = "ctl";
818
819			#phy-cells = <0>;
820		};
821
822		p2u_nvhs_2: phy@3ed0000 {
823			compatible = "nvidia,tegra194-p2u";
824			reg = <0x03ed0000 0x10000>;
825			reg-names = "ctl";
826
827			#phy-cells = <0>;
828		};
829
830		p2u_nvhs_3: phy@3ee0000 {
831			compatible = "nvidia,tegra194-p2u";
832			reg = <0x03ee0000 0x10000>;
833			reg-names = "ctl";
834
835			#phy-cells = <0>;
836		};
837
838		p2u_nvhs_4: phy@3ef0000 {
839			compatible = "nvidia,tegra194-p2u";
840			reg = <0x03ef0000 0x10000>;
841			reg-names = "ctl";
842
843			#phy-cells = <0>;
844		};
845
846		p2u_nvhs_5: phy@3f00000 {
847			compatible = "nvidia,tegra194-p2u";
848			reg = <0x03f00000 0x10000>;
849			reg-names = "ctl";
850
851			#phy-cells = <0>;
852		};
853
854		p2u_nvhs_6: phy@3f10000 {
855			compatible = "nvidia,tegra194-p2u";
856			reg = <0x03f10000 0x10000>;
857			reg-names = "ctl";
858
859			#phy-cells = <0>;
860		};
861
862		p2u_nvhs_7: phy@3f20000 {
863			compatible = "nvidia,tegra194-p2u";
864			reg = <0x03f20000 0x10000>;
865			reg-names = "ctl";
866
867			#phy-cells = <0>;
868		};
869
870		p2u_hsio_10: phy@3f30000 {
871			compatible = "nvidia,tegra194-p2u";
872			reg = <0x03f30000 0x10000>;
873			reg-names = "ctl";
874
875			#phy-cells = <0>;
876		};
877
878		p2u_hsio_11: phy@3f40000 {
879			compatible = "nvidia,tegra194-p2u";
880			reg = <0x03f40000 0x10000>;
881			reg-names = "ctl";
882
883			#phy-cells = <0>;
884		};
885
886		hsp_aon: hsp@c150000 {
887			compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
888			reg = <0x0c150000 0xa0000>;
889			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
890			             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
891			             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
892			             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
893			/*
894			 * Shared interrupt 0 is routed only to AON/SPE, so
895			 * we only have 4 shared interrupts for the CCPLEX.
896			 */
897			interrupt-names = "shared1", "shared2", "shared3", "shared4";
898			#mbox-cells = <2>;
899		};
900
901		gen2_i2c: i2c@c240000 {
902			compatible = "nvidia,tegra194-i2c";
903			reg = <0x0c240000 0x10000>;
904			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
905			#address-cells = <1>;
906			#size-cells = <0>;
907			clocks = <&bpmp TEGRA194_CLK_I2C2>;
908			clock-names = "div-clk";
909			resets = <&bpmp TEGRA194_RESET_I2C2>;
910			reset-names = "i2c";
911			status = "disabled";
912		};
913
914		gen8_i2c: i2c@c250000 {
915			compatible = "nvidia,tegra194-i2c";
916			reg = <0x0c250000 0x10000>;
917			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
918			#address-cells = <1>;
919			#size-cells = <0>;
920			clocks = <&bpmp TEGRA194_CLK_I2C8>;
921			clock-names = "div-clk";
922			resets = <&bpmp TEGRA194_RESET_I2C8>;
923			reset-names = "i2c";
924			status = "disabled";
925		};
926
927		uartc: serial@c280000 {
928			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
929			reg = <0x0c280000 0x40>;
930			reg-shift = <2>;
931			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
932			clocks = <&bpmp TEGRA194_CLK_UARTC>;
933			clock-names = "serial";
934			resets = <&bpmp TEGRA194_RESET_UARTC>;
935			reset-names = "serial";
936			status = "disabled";
937		};
938
939		uartg: serial@c290000 {
940			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
941			reg = <0x0c290000 0x40>;
942			reg-shift = <2>;
943			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
944			clocks = <&bpmp TEGRA194_CLK_UARTG>;
945			clock-names = "serial";
946			resets = <&bpmp TEGRA194_RESET_UARTG>;
947			reset-names = "serial";
948			status = "disabled";
949		};
950
951		rtc: rtc@c2a0000 {
952			compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
953			reg = <0x0c2a0000 0x10000>;
954			interrupt-parent = <&pmc>;
955			interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
956			clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
957			clock-names = "rtc";
958			status = "disabled";
959		};
960
961		gpio_aon: gpio@c2f0000 {
962			compatible = "nvidia,tegra194-gpio-aon";
963			reg-names = "security", "gpio";
964			reg = <0xc2f0000 0x1000>,
965			      <0xc2f1000 0x1000>;
966			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
967				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
968				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
969				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
970			gpio-controller;
971			#gpio-cells = <2>;
972			interrupt-controller;
973			#interrupt-cells = <2>;
974		};
975
976		pwm4: pwm@c340000 {
977			compatible = "nvidia,tegra194-pwm",
978				     "nvidia,tegra186-pwm";
979			reg = <0xc340000 0x10000>;
980			clocks = <&bpmp TEGRA194_CLK_PWM4>;
981			clock-names = "pwm";
982			resets = <&bpmp TEGRA194_RESET_PWM4>;
983			reset-names = "pwm";
984			status = "disabled";
985			#pwm-cells = <2>;
986		};
987
988		pmc: pmc@c360000 {
989			compatible = "nvidia,tegra194-pmc";
990			reg = <0x0c360000 0x10000>,
991			      <0x0c370000 0x10000>,
992			      <0x0c380000 0x10000>,
993			      <0x0c390000 0x10000>,
994			      <0x0c3a0000 0x10000>;
995			reg-names = "pmc", "wake", "aotag", "scratch", "misc";
996
997			#interrupt-cells = <2>;
998			interrupt-controller;
999		};
1000
1001		host1x@13e00000 {
1002			compatible = "nvidia,tegra194-host1x", "simple-bus";
1003			reg = <0x13e00000 0x10000>,
1004			      <0x13e10000 0x10000>;
1005			reg-names = "hypervisor", "vm";
1006			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1007				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1008			clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1009			clock-names = "host1x";
1010			resets = <&bpmp TEGRA194_RESET_HOST1X>;
1011			reset-names = "host1x";
1012
1013			#address-cells = <1>;
1014			#size-cells = <1>;
1015
1016			ranges = <0x15000000 0x15000000 0x01000000>;
1017
1018			display-hub@15200000 {
1019				compatible = "nvidia,tegra194-display", "simple-bus";
1020				reg = <0x15200000 0x00040000>;
1021				resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1022					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1023					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1024					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1025					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1026					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1027					 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1028				reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1029					      "wgrp3", "wgrp4", "wgrp5";
1030				clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1031					 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1032				clock-names = "disp", "hub";
1033				status = "disabled";
1034
1035				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1036
1037				#address-cells = <1>;
1038				#size-cells = <1>;
1039
1040				ranges = <0x15200000 0x15200000 0x40000>;
1041
1042				display@15200000 {
1043					compatible = "nvidia,tegra194-dc";
1044					reg = <0x15200000 0x10000>;
1045					interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1046					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1047					clock-names = "dc";
1048					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1049					reset-names = "dc";
1050
1051					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1052
1053					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1054					nvidia,head = <0>;
1055				};
1056
1057				display@15210000 {
1058					compatible = "nvidia,tegra194-dc";
1059					reg = <0x15210000 0x10000>;
1060					interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1061					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1062					clock-names = "dc";
1063					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1064					reset-names = "dc";
1065
1066					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1067
1068					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1069					nvidia,head = <1>;
1070				};
1071
1072				display@15220000 {
1073					compatible = "nvidia,tegra194-dc";
1074					reg = <0x15220000 0x10000>;
1075					interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1076					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1077					clock-names = "dc";
1078					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1079					reset-names = "dc";
1080
1081					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1082
1083					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1084					nvidia,head = <2>;
1085				};
1086
1087				display@15230000 {
1088					compatible = "nvidia,tegra194-dc";
1089					reg = <0x15230000 0x10000>;
1090					interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1091					clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1092					clock-names = "dc";
1093					resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1094					reset-names = "dc";
1095
1096					power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1097
1098					nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1099					nvidia,head = <3>;
1100				};
1101			};
1102
1103			vic@15340000 {
1104				compatible = "nvidia,tegra194-vic";
1105				reg = <0x15340000 0x00040000>;
1106				interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1107				clocks = <&bpmp TEGRA194_CLK_VIC>;
1108				clock-names = "vic";
1109				resets = <&bpmp TEGRA194_RESET_VIC>;
1110				reset-names = "vic";
1111
1112				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1113			};
1114
1115			dpaux0: dpaux@155c0000 {
1116				compatible = "nvidia,tegra194-dpaux";
1117				reg = <0x155c0000 0x10000>;
1118				interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1119				clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1120					 <&bpmp TEGRA194_CLK_PLLDP>;
1121				clock-names = "dpaux", "parent";
1122				resets = <&bpmp TEGRA194_RESET_DPAUX>;
1123				reset-names = "dpaux";
1124				status = "disabled";
1125
1126				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1127
1128				state_dpaux0_aux: pinmux-aux {
1129					groups = "dpaux-io";
1130					function = "aux";
1131				};
1132
1133				state_dpaux0_i2c: pinmux-i2c {
1134					groups = "dpaux-io";
1135					function = "i2c";
1136				};
1137
1138				state_dpaux0_off: pinmux-off {
1139					groups = "dpaux-io";
1140					function = "off";
1141				};
1142
1143				i2c-bus {
1144					#address-cells = <1>;
1145					#size-cells = <0>;
1146				};
1147			};
1148
1149			dpaux1: dpaux@155d0000 {
1150				compatible = "nvidia,tegra194-dpaux";
1151				reg = <0x155d0000 0x10000>;
1152				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1153				clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1154					 <&bpmp TEGRA194_CLK_PLLDP>;
1155				clock-names = "dpaux", "parent";
1156				resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1157				reset-names = "dpaux";
1158				status = "disabled";
1159
1160				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1161
1162				state_dpaux1_aux: pinmux-aux {
1163					groups = "dpaux-io";
1164					function = "aux";
1165				};
1166
1167				state_dpaux1_i2c: pinmux-i2c {
1168					groups = "dpaux-io";
1169					function = "i2c";
1170				};
1171
1172				state_dpaux1_off: pinmux-off {
1173					groups = "dpaux-io";
1174					function = "off";
1175				};
1176
1177				i2c-bus {
1178					#address-cells = <1>;
1179					#size-cells = <0>;
1180				};
1181			};
1182
1183			dpaux2: dpaux@155e0000 {
1184				compatible = "nvidia,tegra194-dpaux";
1185				reg = <0x155e0000 0x10000>;
1186				interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1187				clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1188					 <&bpmp TEGRA194_CLK_PLLDP>;
1189				clock-names = "dpaux", "parent";
1190				resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1191				reset-names = "dpaux";
1192				status = "disabled";
1193
1194				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1195
1196				state_dpaux2_aux: pinmux-aux {
1197					groups = "dpaux-io";
1198					function = "aux";
1199				};
1200
1201				state_dpaux2_i2c: pinmux-i2c {
1202					groups = "dpaux-io";
1203					function = "i2c";
1204				};
1205
1206				state_dpaux2_off: pinmux-off {
1207					groups = "dpaux-io";
1208					function = "off";
1209				};
1210
1211				i2c-bus {
1212					#address-cells = <1>;
1213					#size-cells = <0>;
1214				};
1215			};
1216
1217			dpaux3: dpaux@155f0000 {
1218				compatible = "nvidia,tegra194-dpaux";
1219				reg = <0x155f0000 0x10000>;
1220				interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1221				clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1222					 <&bpmp TEGRA194_CLK_PLLDP>;
1223				clock-names = "dpaux", "parent";
1224				resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1225				reset-names = "dpaux";
1226				status = "disabled";
1227
1228				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1229
1230				state_dpaux3_aux: pinmux-aux {
1231					groups = "dpaux-io";
1232					function = "aux";
1233				};
1234
1235				state_dpaux3_i2c: pinmux-i2c {
1236					groups = "dpaux-io";
1237					function = "i2c";
1238				};
1239
1240				state_dpaux3_off: pinmux-off {
1241					groups = "dpaux-io";
1242					function = "off";
1243				};
1244
1245				i2c-bus {
1246					#address-cells = <1>;
1247					#size-cells = <0>;
1248				};
1249			};
1250
1251			sor0: sor@15b00000 {
1252				compatible = "nvidia,tegra194-sor";
1253				reg = <0x15b00000 0x40000>;
1254				interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1255				clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1256					 <&bpmp TEGRA194_CLK_SOR0_OUT>,
1257					 <&bpmp TEGRA194_CLK_PLLD>,
1258					 <&bpmp TEGRA194_CLK_PLLDP>,
1259					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1260					 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1261				clock-names = "sor", "out", "parent", "dp", "safe",
1262					      "pad";
1263				resets = <&bpmp TEGRA194_RESET_SOR0>;
1264				reset-names = "sor";
1265				pinctrl-0 = <&state_dpaux0_aux>;
1266				pinctrl-1 = <&state_dpaux0_i2c>;
1267				pinctrl-2 = <&state_dpaux0_off>;
1268				pinctrl-names = "aux", "i2c", "off";
1269				status = "disabled";
1270
1271				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1272				nvidia,interface = <0>;
1273			};
1274
1275			sor1: sor@15b40000 {
1276				compatible = "nvidia,tegra194-sor";
1277				reg = <0x15b40000 0x40000>;
1278				interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1279				clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1280					 <&bpmp TEGRA194_CLK_SOR1_OUT>,
1281					 <&bpmp TEGRA194_CLK_PLLD2>,
1282					 <&bpmp TEGRA194_CLK_PLLDP>,
1283					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1284					 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1285				clock-names = "sor", "out", "parent", "dp", "safe",
1286					      "pad";
1287				resets = <&bpmp TEGRA194_RESET_SOR1>;
1288				reset-names = "sor";
1289				pinctrl-0 = <&state_dpaux1_aux>;
1290				pinctrl-1 = <&state_dpaux1_i2c>;
1291				pinctrl-2 = <&state_dpaux1_off>;
1292				pinctrl-names = "aux", "i2c", "off";
1293				status = "disabled";
1294
1295				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1296				nvidia,interface = <1>;
1297			};
1298
1299			sor2: sor@15b80000 {
1300				compatible = "nvidia,tegra194-sor";
1301				reg = <0x15b80000 0x40000>;
1302				interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1303				clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1304					 <&bpmp TEGRA194_CLK_SOR2_OUT>,
1305					 <&bpmp TEGRA194_CLK_PLLD3>,
1306					 <&bpmp TEGRA194_CLK_PLLDP>,
1307					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1308					 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1309				clock-names = "sor", "out", "parent", "dp", "safe",
1310					      "pad";
1311				resets = <&bpmp TEGRA194_RESET_SOR2>;
1312				reset-names = "sor";
1313				pinctrl-0 = <&state_dpaux2_aux>;
1314				pinctrl-1 = <&state_dpaux2_i2c>;
1315				pinctrl-2 = <&state_dpaux2_off>;
1316				pinctrl-names = "aux", "i2c", "off";
1317				status = "disabled";
1318
1319				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1320				nvidia,interface = <2>;
1321			};
1322
1323			sor3: sor@15bc0000 {
1324				compatible = "nvidia,tegra194-sor";
1325				reg = <0x15bc0000 0x40000>;
1326				interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1327				clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1328					 <&bpmp TEGRA194_CLK_SOR3_OUT>,
1329					 <&bpmp TEGRA194_CLK_PLLD4>,
1330					 <&bpmp TEGRA194_CLK_PLLDP>,
1331					 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1332					 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1333				clock-names = "sor", "out", "parent", "dp", "safe",
1334					      "pad";
1335				resets = <&bpmp TEGRA194_RESET_SOR3>;
1336				reset-names = "sor";
1337				pinctrl-0 = <&state_dpaux3_aux>;
1338				pinctrl-1 = <&state_dpaux3_i2c>;
1339				pinctrl-2 = <&state_dpaux3_off>;
1340				pinctrl-names = "aux", "i2c", "off";
1341				status = "disabled";
1342
1343				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1344				nvidia,interface = <3>;
1345			};
1346		};
1347	};
1348
1349	pcie@14100000 {
1350		compatible = "nvidia,tegra194-pcie";
1351		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1352		reg = <0x00 0x14100000 0x0 0x00020000   /* appl registers (128K)      */
1353		       0x00 0x30000000 0x0 0x00040000   /* configuration space (256K) */
1354		       0x00 0x30040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1355		       0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1356		reg-names = "appl", "config", "atu_dma", "dbi";
1357
1358		status = "disabled";
1359
1360		#address-cells = <3>;
1361		#size-cells = <2>;
1362		device_type = "pci";
1363		num-lanes = <1>;
1364		num-viewport = <8>;
1365		linux,pci-domain = <1>;
1366
1367		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1368		clock-names = "core";
1369
1370		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1371			 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1372		reset-names = "apb", "core";
1373
1374		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,	/* controller interrupt */
1375			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;	/* MSI interrupt */
1376		interrupt-names = "intr", "msi";
1377
1378		#interrupt-cells = <1>;
1379		interrupt-map-mask = <0 0 0 0>;
1380		interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1381
1382		nvidia,bpmp = <&bpmp 1>;
1383
1384		nvidia,aspm-cmrt-us = <60>;
1385		nvidia,aspm-pwr-on-t-us = <20>;
1386		nvidia,aspm-l0s-entrance-latency-us = <3>;
1387
1388		bus-range = <0x0 0xff>;
1389		ranges = <0x81000000 0x0  0x30100000 0x0  0x30100000 0x0 0x00100000   /* downstream I/O (1MB) */
1390			  0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1391			  0x82000000 0x0  0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1392	};
1393
1394	pcie@14120000 {
1395		compatible = "nvidia,tegra194-pcie";
1396		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1397		reg = <0x00 0x14120000 0x0 0x00020000   /* appl registers (128K)      */
1398		       0x00 0x32000000 0x0 0x00040000   /* configuration space (256K) */
1399		       0x00 0x32040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1400		       0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1401		reg-names = "appl", "config", "atu_dma", "dbi";
1402
1403		status = "disabled";
1404
1405		#address-cells = <3>;
1406		#size-cells = <2>;
1407		device_type = "pci";
1408		num-lanes = <1>;
1409		num-viewport = <8>;
1410		linux,pci-domain = <2>;
1411
1412		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1413		clock-names = "core";
1414
1415		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1416			 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1417		reset-names = "apb", "core";
1418
1419		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,	/* controller interrupt */
1420			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;	/* MSI interrupt */
1421		interrupt-names = "intr", "msi";
1422
1423		#interrupt-cells = <1>;
1424		interrupt-map-mask = <0 0 0 0>;
1425		interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1426
1427		nvidia,bpmp = <&bpmp 2>;
1428
1429		nvidia,aspm-cmrt-us = <60>;
1430		nvidia,aspm-pwr-on-t-us = <20>;
1431		nvidia,aspm-l0s-entrance-latency-us = <3>;
1432
1433		bus-range = <0x0 0xff>;
1434		ranges = <0x81000000 0x0  0x32100000 0x0  0x32100000 0x0 0x00100000   /* downstream I/O (1MB) */
1435			  0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1436			  0x82000000 0x0  0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1437	};
1438
1439	pcie@14140000 {
1440		compatible = "nvidia,tegra194-pcie";
1441		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1442		reg = <0x00 0x14140000 0x0 0x00020000   /* appl registers (128K)      */
1443		       0x00 0x34000000 0x0 0x00040000   /* configuration space (256K) */
1444		       0x00 0x34040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1445		       0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1446		reg-names = "appl", "config", "atu_dma", "dbi";
1447
1448		status = "disabled";
1449
1450		#address-cells = <3>;
1451		#size-cells = <2>;
1452		device_type = "pci";
1453		num-lanes = <1>;
1454		num-viewport = <8>;
1455		linux,pci-domain = <3>;
1456
1457		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1458		clock-names = "core";
1459
1460		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1461			 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1462		reset-names = "apb", "core";
1463
1464		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,	/* controller interrupt */
1465			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;	/* MSI interrupt */
1466		interrupt-names = "intr", "msi";
1467
1468		#interrupt-cells = <1>;
1469		interrupt-map-mask = <0 0 0 0>;
1470		interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1471
1472		nvidia,bpmp = <&bpmp 3>;
1473
1474		nvidia,aspm-cmrt-us = <60>;
1475		nvidia,aspm-pwr-on-t-us = <20>;
1476		nvidia,aspm-l0s-entrance-latency-us = <3>;
1477
1478		bus-range = <0x0 0xff>;
1479		ranges = <0x81000000 0x0  0x34100000 0x0  0x34100000 0x0 0x00100000   /* downstream I/O (1MB) */
1480			  0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1481			  0x82000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1482	};
1483
1484	pcie@14160000 {
1485		compatible = "nvidia,tegra194-pcie";
1486		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1487		reg = <0x00 0x14160000 0x0 0x00020000   /* appl registers (128K)      */
1488		       0x00 0x36000000 0x0 0x00040000   /* configuration space (256K) */
1489		       0x00 0x36040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1490		       0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1491		reg-names = "appl", "config", "atu_dma", "dbi";
1492
1493		status = "disabled";
1494
1495		#address-cells = <3>;
1496		#size-cells = <2>;
1497		device_type = "pci";
1498		num-lanes = <4>;
1499		num-viewport = <8>;
1500		linux,pci-domain = <4>;
1501
1502		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1503		clock-names = "core";
1504
1505		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1506			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1507		reset-names = "apb", "core";
1508
1509		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,	/* controller interrupt */
1510			     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;	/* MSI interrupt */
1511		interrupt-names = "intr", "msi";
1512
1513		#interrupt-cells = <1>;
1514		interrupt-map-mask = <0 0 0 0>;
1515		interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1516
1517		nvidia,bpmp = <&bpmp 4>;
1518
1519		nvidia,aspm-cmrt-us = <60>;
1520		nvidia,aspm-pwr-on-t-us = <20>;
1521		nvidia,aspm-l0s-entrance-latency-us = <3>;
1522
1523		bus-range = <0x0 0xff>;
1524		ranges = <0x81000000 0x0  0x36100000 0x0  0x36100000 0x0 0x00100000   /* downstream I/O (1MB) */
1525			  0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1526			  0x82000000 0x0  0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1527	};
1528
1529	pcie@14180000 {
1530		compatible = "nvidia,tegra194-pcie";
1531		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1532		reg = <0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */
1533		       0x00 0x38000000 0x0 0x00040000   /* configuration space (256K) */
1534		       0x00 0x38040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1535		       0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1536		reg-names = "appl", "config", "atu_dma", "dbi";
1537
1538		status = "disabled";
1539
1540		#address-cells = <3>;
1541		#size-cells = <2>;
1542		device_type = "pci";
1543		num-lanes = <8>;
1544		num-viewport = <8>;
1545		linux,pci-domain = <0>;
1546
1547		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1548		clock-names = "core";
1549
1550		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1551			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1552		reset-names = "apb", "core";
1553
1554		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,	/* controller interrupt */
1555			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;	/* MSI interrupt */
1556		interrupt-names = "intr", "msi";
1557
1558		#interrupt-cells = <1>;
1559		interrupt-map-mask = <0 0 0 0>;
1560		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1561
1562		nvidia,bpmp = <&bpmp 0>;
1563
1564		nvidia,aspm-cmrt-us = <60>;
1565		nvidia,aspm-pwr-on-t-us = <20>;
1566		nvidia,aspm-l0s-entrance-latency-us = <3>;
1567
1568		bus-range = <0x0 0xff>;
1569		ranges = <0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000   /* downstream I/O (1MB) */
1570			  0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1571			  0x82000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1572	};
1573
1574	pcie@141a0000 {
1575		compatible = "nvidia,tegra194-pcie";
1576		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1577		reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
1578		       0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */
1579		       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1580		       0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1581		reg-names = "appl", "config", "atu_dma", "dbi";
1582
1583		status = "disabled";
1584
1585		#address-cells = <3>;
1586		#size-cells = <2>;
1587		device_type = "pci";
1588		num-lanes = <8>;
1589		num-viewport = <8>;
1590		linux,pci-domain = <5>;
1591
1592		pinctrl-names = "default";
1593		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1594
1595		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
1596			<&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
1597		clock-names = "core", "core_m";
1598
1599		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1600			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1601		reset-names = "apb", "core";
1602
1603		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,	/* controller interrupt */
1604			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;	/* MSI interrupt */
1605		interrupt-names = "intr", "msi";
1606
1607		nvidia,bpmp = <&bpmp 5>;
1608
1609		#interrupt-cells = <1>;
1610		interrupt-map-mask = <0 0 0 0>;
1611		interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1612
1613		nvidia,aspm-cmrt-us = <60>;
1614		nvidia,aspm-pwr-on-t-us = <20>;
1615		nvidia,aspm-l0s-entrance-latency-us = <3>;
1616
1617		bus-range = <0x0 0xff>;
1618		ranges = <0x81000000 0x0  0x3a100000 0x0  0x3a100000 0x0 0x00100000   /* downstream I/O (1MB) */
1619			  0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1620			  0x82000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1621	};
1622
1623	pcie_ep@14160000 {
1624		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1625		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1626		reg = <0x00 0x14160000 0x0 0x00020000   /* appl registers (128K)      */
1627		       0x00 0x36040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1628		       0x00 0x36080000 0x0 0x00040000   /* DBI reg space (256K)       */
1629		       0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1630		reg-names = "appl", "atu_dma", "dbi", "addr_space";
1631
1632		status = "disabled";
1633
1634		num-lanes = <4>;
1635		num-ib-windows = <2>;
1636		num-ob-windows = <8>;
1637
1638		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1639		clock-names = "core";
1640
1641		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1642			 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1643		reset-names = "apb", "core";
1644
1645		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
1646		interrupt-names = "intr";
1647
1648		nvidia,bpmp = <&bpmp 4>;
1649
1650		nvidia,aspm-cmrt-us = <60>;
1651		nvidia,aspm-pwr-on-t-us = <20>;
1652		nvidia,aspm-l0s-entrance-latency-us = <3>;
1653	};
1654
1655	pcie_ep@14180000 {
1656		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1657		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1658		reg = <0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */
1659		       0x00 0x38040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1660		       0x00 0x38080000 0x0 0x00040000   /* DBI reg space (256K)       */
1661		       0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1662		reg-names = "appl", "atu_dma", "dbi", "addr_space";
1663
1664		status = "disabled";
1665
1666		num-lanes = <8>;
1667		num-ib-windows = <2>;
1668		num-ob-windows = <8>;
1669
1670		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1671		clock-names = "core";
1672
1673		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1674			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1675		reset-names = "apb", "core";
1676
1677		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
1678		interrupt-names = "intr";
1679
1680		nvidia,bpmp = <&bpmp 0>;
1681
1682		nvidia,aspm-cmrt-us = <60>;
1683		nvidia,aspm-pwr-on-t-us = <20>;
1684		nvidia,aspm-l0s-entrance-latency-us = <3>;
1685	};
1686
1687	pcie_ep@141a0000 {
1688		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1689		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1690		reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
1691		       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1692		       0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */
1693		       0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
1694		reg-names = "appl", "atu_dma", "dbi", "addr_space";
1695
1696		status = "disabled";
1697
1698		num-lanes = <8>;
1699		num-ib-windows = <2>;
1700		num-ob-windows = <8>;
1701
1702		pinctrl-names = "default";
1703		pinctrl-0 = <&clkreq_c5_bi_dir_state>;
1704
1705		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
1706		clock-names = "core";
1707
1708		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1709			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1710		reset-names = "apb", "core";
1711
1712		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
1713		interrupt-names = "intr";
1714
1715		nvidia,bpmp = <&bpmp 5>;
1716
1717		nvidia,aspm-cmrt-us = <60>;
1718		nvidia,aspm-pwr-on-t-us = <20>;
1719		nvidia,aspm-l0s-entrance-latency-us = <3>;
1720	};
1721
1722	sysram@40000000 {
1723		compatible = "nvidia,tegra194-sysram", "mmio-sram";
1724		reg = <0x0 0x40000000 0x0 0x50000>;
1725		#address-cells = <1>;
1726		#size-cells = <1>;
1727		ranges = <0x0 0x0 0x40000000 0x50000>;
1728
1729		cpu_bpmp_tx: shmem@4e000 {
1730			compatible = "nvidia,tegra194-bpmp-shmem";
1731			reg = <0x4e000 0x1000>;
1732			label = "cpu-bpmp-tx";
1733			pool;
1734		};
1735
1736		cpu_bpmp_rx: shmem@4f000 {
1737			compatible = "nvidia,tegra194-bpmp-shmem";
1738			reg = <0x4f000 0x1000>;
1739			label = "cpu-bpmp-rx";
1740			pool;
1741		};
1742	};
1743
1744	bpmp: bpmp {
1745		compatible = "nvidia,tegra186-bpmp";
1746		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1747				    TEGRA_HSP_DB_MASTER_BPMP>;
1748		shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1749		#clock-cells = <1>;
1750		#reset-cells = <1>;
1751		#power-domain-cells = <1>;
1752
1753		bpmp_i2c: i2c {
1754			compatible = "nvidia,tegra186-bpmp-i2c";
1755			nvidia,bpmp-bus-id = <5>;
1756			#address-cells = <1>;
1757			#size-cells = <0>;
1758		};
1759
1760		bpmp_thermal: thermal {
1761			compatible = "nvidia,tegra186-bpmp-thermal";
1762			#thermal-sensor-cells = <1>;
1763		};
1764	};
1765
1766	cpus {
1767		#address-cells = <1>;
1768		#size-cells = <0>;
1769
1770		cpu0_0: cpu@0 {
1771			compatible = "nvidia,tegra194-carmel";
1772			device_type = "cpu";
1773			reg = <0x000>;
1774			enable-method = "psci";
1775			i-cache-size = <131072>;
1776			i-cache-line-size = <64>;
1777			i-cache-sets = <512>;
1778			d-cache-size = <65536>;
1779			d-cache-line-size = <64>;
1780			d-cache-sets = <256>;
1781			next-level-cache = <&l2c_0>;
1782		};
1783
1784		cpu0_1: cpu@1 {
1785			compatible = "nvidia,tegra194-carmel";
1786			device_type = "cpu";
1787			reg = <0x001>;
1788			enable-method = "psci";
1789			i-cache-size = <131072>;
1790			i-cache-line-size = <64>;
1791			i-cache-sets = <512>;
1792			d-cache-size = <65536>;
1793			d-cache-line-size = <64>;
1794			d-cache-sets = <256>;
1795			next-level-cache = <&l2c_0>;
1796		};
1797
1798		cpu1_0: cpu@100 {
1799			compatible = "nvidia,tegra194-carmel";
1800			device_type = "cpu";
1801			reg = <0x100>;
1802			enable-method = "psci";
1803			i-cache-size = <131072>;
1804			i-cache-line-size = <64>;
1805			i-cache-sets = <512>;
1806			d-cache-size = <65536>;
1807			d-cache-line-size = <64>;
1808			d-cache-sets = <256>;
1809			next-level-cache = <&l2c_1>;
1810		};
1811
1812		cpu1_1: cpu@101 {
1813			compatible = "nvidia,tegra194-carmel";
1814			device_type = "cpu";
1815			reg = <0x101>;
1816			enable-method = "psci";
1817			i-cache-size = <131072>;
1818			i-cache-line-size = <64>;
1819			i-cache-sets = <512>;
1820			d-cache-size = <65536>;
1821			d-cache-line-size = <64>;
1822			d-cache-sets = <256>;
1823			next-level-cache = <&l2c_1>;
1824		};
1825
1826		cpu2_0: cpu@200 {
1827			compatible = "nvidia,tegra194-carmel";
1828			device_type = "cpu";
1829			reg = <0x200>;
1830			enable-method = "psci";
1831			i-cache-size = <131072>;
1832			i-cache-line-size = <64>;
1833			i-cache-sets = <512>;
1834			d-cache-size = <65536>;
1835			d-cache-line-size = <64>;
1836			d-cache-sets = <256>;
1837			next-level-cache = <&l2c_2>;
1838		};
1839
1840		cpu2_1: cpu@201 {
1841			compatible = "nvidia,tegra194-carmel";
1842			device_type = "cpu";
1843			reg = <0x201>;
1844			enable-method = "psci";
1845			i-cache-size = <131072>;
1846			i-cache-line-size = <64>;
1847			i-cache-sets = <512>;
1848			d-cache-size = <65536>;
1849			d-cache-line-size = <64>;
1850			d-cache-sets = <256>;
1851			next-level-cache = <&l2c_2>;
1852		};
1853
1854		cpu3_0: cpu@300 {
1855			compatible = "nvidia,tegra194-carmel";
1856			device_type = "cpu";
1857			reg = <0x300>;
1858			enable-method = "psci";
1859			i-cache-size = <131072>;
1860			i-cache-line-size = <64>;
1861			i-cache-sets = <512>;
1862			d-cache-size = <65536>;
1863			d-cache-line-size = <64>;
1864			d-cache-sets = <256>;
1865			next-level-cache = <&l2c_3>;
1866		};
1867
1868		cpu3_1: cpu@301 {
1869			compatible = "nvidia,tegra194-carmel";
1870			device_type = "cpu";
1871			reg = <0x301>;
1872			enable-method = "psci";
1873			i-cache-size = <131072>;
1874			i-cache-line-size = <64>;
1875			i-cache-sets = <512>;
1876			d-cache-size = <65536>;
1877			d-cache-line-size = <64>;
1878			d-cache-sets = <256>;
1879			next-level-cache = <&l2c_3>;
1880		};
1881
1882		cpu-map {
1883			cluster0 {
1884				core0 {
1885					cpu = <&cpu0_0>;
1886				};
1887
1888				core1 {
1889					cpu = <&cpu0_1>;
1890				};
1891			};
1892
1893			cluster1 {
1894				core0 {
1895					cpu = <&cpu1_0>;
1896				};
1897
1898				core1 {
1899					cpu = <&cpu1_1>;
1900				};
1901			};
1902
1903			cluster2 {
1904				core0 {
1905					cpu = <&cpu2_0>;
1906				};
1907
1908				core1 {
1909					cpu = <&cpu2_1>;
1910				};
1911			};
1912
1913			cluster3 {
1914				core0 {
1915					cpu = <&cpu3_0>;
1916				};
1917
1918				core1 {
1919					cpu = <&cpu3_1>;
1920				};
1921			};
1922		};
1923
1924		l2c_0: l2-cache0 {
1925			cache-size = <2097152>;
1926			cache-line-size = <64>;
1927			cache-sets = <2048>;
1928			next-level-cache = <&l3c>;
1929		};
1930
1931		l2c_1: l2-cache1 {
1932			cache-size = <2097152>;
1933			cache-line-size = <64>;
1934			cache-sets = <2048>;
1935			next-level-cache = <&l3c>;
1936		};
1937
1938		l2c_2: l2-cache2 {
1939			cache-size = <2097152>;
1940			cache-line-size = <64>;
1941			cache-sets = <2048>;
1942			next-level-cache = <&l3c>;
1943		};
1944
1945		l2c_3: l2-cache3 {
1946			cache-size = <2097152>;
1947			cache-line-size = <64>;
1948			cache-sets = <2048>;
1949			next-level-cache = <&l3c>;
1950		};
1951
1952		l3c: l3-cache {
1953			cache-size = <4194304>;
1954			cache-line-size = <64>;
1955			cache-sets = <4096>;
1956		};
1957	};
1958
1959	psci {
1960		compatible = "arm,psci-1.0";
1961		status = "okay";
1962		method = "smc";
1963	};
1964
1965	tcu: tcu {
1966		compatible = "nvidia,tegra194-tcu";
1967		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
1968		         <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
1969		mbox-names = "rx", "tx";
1970	};
1971
1972	thermal-zones {
1973		cpu {
1974			thermal-sensors = <&{/bpmp/thermal}
1975					   TEGRA194_BPMP_THERMAL_ZONE_CPU>;
1976			status = "disabled";
1977		};
1978
1979		gpu {
1980			thermal-sensors = <&{/bpmp/thermal}
1981					   TEGRA194_BPMP_THERMAL_ZONE_GPU>;
1982			status = "disabled";
1983		};
1984
1985		aux {
1986			thermal-sensors = <&{/bpmp/thermal}
1987					   TEGRA194_BPMP_THERMAL_ZONE_AUX>;
1988			status = "disabled";
1989		};
1990
1991		pllx {
1992			thermal-sensors = <&{/bpmp/thermal}
1993					   TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
1994			status = "disabled";
1995		};
1996
1997		ao {
1998			thermal-sensors = <&{/bpmp/thermal}
1999					   TEGRA194_BPMP_THERMAL_ZONE_AO>;
2000			status = "disabled";
2001		};
2002
2003		tj {
2004			thermal-sensors = <&{/bpmp/thermal}
2005					   TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2006			status = "disabled";
2007		};
2008	};
2009
2010	timer {
2011		compatible = "arm,armv8-timer";
2012		interrupts = <GIC_PPI 13
2013				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2014			     <GIC_PPI 14
2015				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2016			     <GIC_PPI 11
2017				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2018			     <GIC_PPI 10
2019				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2020		interrupt-parent = <&gic>;
2021		always-on;
2022	};
2023};
2024